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amd-drm-fixes-6.10-2024-06-06:
amdgpu: - Fix shutdown issues on some SMU 13.x platforms - Silence some UBSAN flexible array warnings -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQgO5Idg2tXNTSZAr293/aFa7yZ2AUCZmIMJQAKCRC93/aFa7yZ 2OU3AQCnUpn+zGRiA8/kkKUzvaFCxrRvdMQ7faxi2b8dvorzqgD7B+8j2gNUBnCX Zv/wskbp8DqP5eEs7xtMQuqWvUijPwA= =3Ncj -----END PGP SIGNATURE----- Merge tag 'amd-drm-fixes-6.10-2024-06-06' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.10-2024-06-06: amdgpu: - Fix shutdown issues on some SMU 13.x platforms - Silence some UBSAN flexible array warnings Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240606192348.3620805-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
2d42183110
@ -480,7 +480,7 @@ typedef struct _StateArray{
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//how many states we have
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UCHAR ucNumEntries;
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ATOM_PPLIB_STATE_V2 states[1];
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ATOM_PPLIB_STATE_V2 states[] /* __counted_by(ucNumEntries) */;
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}StateArray;
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@ -495,13 +495,12 @@ typedef struct _ClockInfoArray{
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}ClockInfoArray;
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typedef struct _NonClockInfoArray{
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//how many non-clock levels we have. normally should be same as number of states
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UCHAR ucNumEntries;
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//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
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UCHAR ucEntrySize;
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ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[];
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ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[] __counted_by(ucNumEntries);
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}NonClockInfoArray;
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typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
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@ -513,8 +512,10 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
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typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries.
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// Number of entries.
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UCHAR ucNumEntries;
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// Dynamically allocate entries.
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ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[] __counted_by(ucNumEntries);
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}ATOM_PPLIB_Clock_Voltage_Dependency_Table;
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typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
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@ -529,8 +530,10 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
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typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries.
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// Number of entries.
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UCHAR ucNumEntries;
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// Dynamically allocate entries.
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ATOM_PPLIB_Clock_Voltage_Limit_Record entries[] __counted_by(ucNumEntries);
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}ATOM_PPLIB_Clock_Voltage_Limit_Table;
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union _ATOM_PPLIB_CAC_Leakage_Record
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@ -553,8 +556,10 @@ typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record;
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typedef struct _ATOM_PPLIB_CAC_Leakage_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries.
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// Number of entries.
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UCHAR ucNumEntries;
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// Dynamically allocate entries.
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ATOM_PPLIB_CAC_Leakage_Record entries[] __counted_by(ucNumEntries);
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}ATOM_PPLIB_CAC_Leakage_Table;
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typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
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@ -568,8 +573,10 @@ typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
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typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries.
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// Number of entries.
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UCHAR ucNumEntries;
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// Dynamically allocate entries.
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ATOM_PPLIB_PhaseSheddingLimits_Record entries[] __counted_by(ucNumEntries);
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}ATOM_PPLIB_PhaseSheddingLimits_Table;
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typedef struct _VCEClockInfo{
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@ -581,7 +588,7 @@ typedef struct _VCEClockInfo{
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typedef struct _VCEClockInfoArray{
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UCHAR ucNumEntries;
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VCEClockInfo entries[1];
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VCEClockInfo entries[] __counted_by(ucNumEntries);
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}VCEClockInfoArray;
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typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
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@ -593,7 +600,7 @@ typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
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typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];
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ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_VCE_State_Record
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@ -605,7 +612,7 @@ typedef struct _ATOM_PPLIB_VCE_State_Record
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typedef struct _ATOM_PPLIB_VCE_State_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_VCE_State_Record entries[1];
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ATOM_PPLIB_VCE_State_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_VCE_State_Table;
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@ -627,7 +634,7 @@ typedef struct _UVDClockInfo{
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typedef struct _UVDClockInfoArray{
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UCHAR ucNumEntries;
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UVDClockInfo entries[1];
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UVDClockInfo entries[] __counted_by(ucNumEntries);
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}UVDClockInfoArray;
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typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
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@ -639,7 +646,7 @@ typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
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typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];
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ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_UVD_Table
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@ -658,7 +665,7 @@ typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record
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typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{
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UCHAR numEntries;
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ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[];
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ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_SAMClk_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_SAMU_Table
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@ -676,7 +683,7 @@ typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record
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typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{
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UCHAR numEntries;
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ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1];
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ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_ACPClk_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_ACP_Table
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@ -745,7 +752,7 @@ typedef struct ATOM_PPLIB_VQ_Budgeting_Record{
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typedef struct ATOM_PPLIB_VQ_Budgeting_Table {
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UCHAR revid;
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UCHAR numEntries;
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ATOM_PPLIB_VQ_Budgeting_Record entries[1];
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ATOM_PPLIB_VQ_Budgeting_Record entries[] __counted_by(numEntries);
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} ATOM_PPLIB_VQ_Budgeting_Table;
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#pragma pack()
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@ -226,7 +226,8 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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if (!en && adev->in_s4) {
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if (!en && !adev->in_s0ix) {
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if (adev->in_s4) {
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/* Adds a GFX reset as workaround just before sending the
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* MP1_UNLOAD message to prevent GC/RLC/PMFW from entering
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* an invalid state.
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@ -235,6 +236,7 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
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SMU_RESET_MODE_2, NULL);
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if (ret)
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return ret;
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}
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ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
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}
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