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include: dt-binding: clock: Rename zynqmp header file

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Rename file name of ZynqMP clk dt-bindings to align with
file name of reset and power dt-bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Jolly Shah 2019-02-27 12:51:09 -08:00 committed by Michal Simek
parent 9e98c678c2
commit 31a2d5113e
2 changed files with 19 additions and 9 deletions
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2
Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.txt
View File

@ -62,7 +62,7 @@ order to provide an optional (E)MIO clock source:
Output clocks are registered based on clock information received
from firmware. Output clocks indexes are mentioned in
include/dt-bindings/clock/xlnx,zynqmp-clk.h.
include/dt-bindings/clock/xlnx-zynqmp-clk.h.
-------
Example

26
include/dt-bindings/clock/xlnx,zynqmp-clk.h → include/dt-bindings/clock/xlnx-zynqmp-clk.h
View File

@ -54,14 +54,14 @@
#define IOU_SWITCH 42
#define GEM_TSU_REF 43
#define GEM_TSU 44
#define GEM0_REF 45
#define GEM1_REF 46
#define GEM2_REF 47
#define GEM3_REF 48
#define GEM0_TX 49
#define GEM1_TX 50
#define GEM2_TX 51
#define GEM3_TX 52
#define GEM0_TX 45
#define GEM1_TX 46
#define GEM2_TX 47
#define GEM3_TX 48
#define GEM0_RX 49
#define GEM1_RX 50
#define GEM2_RX 51
#define GEM3_RX 52
#define QSPI_REF 53
#define SDIO0_REF 54
#define SDIO1_REF 55
@ -112,5 +112,15 @@
#define VPLL_POST_SRC 100
#define CAN0_MIO 101
#define CAN1_MIO 102
#define ACPU_FULL 103
#define GEM0_REF 104
#define GEM1_REF 105
#define GEM2_REF 106
#define GEM3_REF 107
#define GEM0_REF_UNG 108
#define GEM1_REF_UNG 109
#define GEM2_REF_UNG 110
#define GEM3_REF_UNG 111
#define LPD_WDT 112
#endif