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iommufd: Add data structure for Intel VT-d stage-1 cache invalidation
This adds the data structure invalidating caches for the nested domain allocated with IOMMU_HWPT_DATA_VTD_S1 type. Link: https://lore.kernel.org/r/20240111041015.47920-8-yi.l.liu@intel.com Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Yi Liu <yi.l.liu@intel.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
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@ -623,6 +623,42 @@ enum iommu_hwpt_invalidate_data_type {
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IOMMU_HWPT_INVALIDATE_DATA_VTD_S1,
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};
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/**
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* enum iommu_hwpt_vtd_s1_invalidate_flags - Flags for Intel VT-d
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* stage-1 cache invalidation
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* @IOMMU_VTD_INV_FLAGS_LEAF: Indicates whether the invalidation applies
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* to all-levels page structure cache or just
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* the leaf PTE cache.
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*/
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enum iommu_hwpt_vtd_s1_invalidate_flags {
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IOMMU_VTD_INV_FLAGS_LEAF = 1 << 0,
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};
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/**
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* struct iommu_hwpt_vtd_s1_invalidate - Intel VT-d cache invalidation
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* (IOMMU_HWPT_INVALIDATE_DATA_VTD_S1)
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* @addr: The start address of the range to be invalidated. It needs to
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* be 4KB aligned.
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* @npages: Number of contiguous 4K pages to be invalidated.
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* @flags: Combination of enum iommu_hwpt_vtd_s1_invalidate_flags
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* @__reserved: Must be 0
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*
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* The Intel VT-d specific invalidation data for user-managed stage-1 cache
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* invalidation in nested translation. Userspace uses this structure to
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* tell the impacted cache scope after modifying the stage-1 page table.
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*
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* Invalidating all the caches related to the page table by setting @addr
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* to be 0 and @npages to be U64_MAX.
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*
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* The device TLB will be invalidated automatically if ATS is enabled.
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*/
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struct iommu_hwpt_vtd_s1_invalidate {
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__aligned_u64 addr;
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__aligned_u64 npages;
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__u32 flags;
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__u32 __reserved;
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};
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/**
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* struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE)
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* @size: sizeof(struct iommu_hwpt_invalidate)
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