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ARM SoC fixes for v5.12, part 2

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Most of the changes again are devicetree fixes, but there are also five
 trivial build fixes for issues I found when test building with gcc-11 or
 when running 'make W=1', and some OMAP platform specific code fixups.
 
 Broadcom
   - One revert for a Raspberry pi interrupt controller change that
     caused a regression.
 
 TI OMAP:
   - Remove unused duplicate sha2md5_fck clock node that can race with the
     OMAP4_SHA2MD5_CLKCTRL clock node for disable for unused clocks
 
   - Add aliases for omap4/5 mmc to put the slots back into the right
     order again
 
   - Fix typo for bionic voltage controllers that accidentally use mpu
     for all instances instead of mpu, core and iva
 
   - Fix random hangs for droid4 caused by missing fix from TI Android
     kernel tree to do a dummy smc call on cpuidle wakeup path
 
 NXP i.MX:
   - Fix a system failure on imx6qdl-phytec-pfla02 board when booting from
     SD, by adding missing vmmc supply for SD interfaces.
 
   - Fix address typo in i.MX8MM/Q IOMUXC_SD1_DATA0_GPIO2_IO2 definition.
 
 Marvell mvebu:
   - Fix storm interrupt on Turris Omnia
 
   - Enable hardware buffer management as it should be
 
 Build fixes for PXA, Freescale, Marvell, OMAP1 an Keystone.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'arm-fixes-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "Most of the changes again are devicetree fixes, but there are also
  five trivial build fixes for issues I found when test building with
  gcc-11 or when running 'make W=1', and some OMAP platform specific
  code fixups.

  Broadcom:
   - One revert for a Raspberry pi interrupt controller change that
     caused a regression.

  TI OMAP:
   - Remove unused duplicate sha2md5_fck clock node that can race with
     the OMAP4_SHA2MD5_CLKCTRL clock node for disable for unused clocks

   - Add aliases for omap4/5 mmc to put the slots back into the right
     order again

   - Fix typo for bionic voltage controllers that accidentally use mpu
     for all instances instead of mpu, core and iva

   - Fix random hangs for droid4 caused by missing fix from TI Android
     kernel tree to do a dummy smc call on cpuidle wakeup path

  NXP i.MX:
   - Fix a system failure on imx6qdl-phytec-pfla02 board when booting
     from SD, by adding missing vmmc supply for SD interfaces.

   - Fix address typo in i.MX8MM/Q IOMUXC_SD1_DATA0_GPIO2_IO2
     definition.

  Marvell mvebu:
   - Fix storm interrupt on Turris Omnia

   - Enable hardware buffer management as it should be

  ... and build fixes for PXA, Freescale, Marvell, OMAP1 and Keystone"

* tag 'arm-fixes-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: dts: turris-omnia: configure LED[2]/INTn pin as interrupt pin
  ARM: dts: turris-omnia: fix hardware buffer management
  Revert "arm64: dts: marvell: armada-cp110: Switch to per-port SATA interrupts"
  ARM: mvebu: avoid clang -Wtautological-constant warning
  ARM: pxa: mainstone: avoid -Woverride-init warning
  ARM: omap1: fix building with clang IAS
  soc/fsl: qbman: fix conflicting alignment attributes
  ARM: keystone: fix integer overflow warning
  ARM: dts: imx6: pbab01: Set vmmc supply for both SD interfaces
  arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0
  ARM: OMAP4: PM: update ROM return address for OSWR and OFF
  ARM: OMAP4: Fix PMIC voltage domains for bionic
  ARM: dts: Fix moving mmc devices with aliases for omap4 & 5
  ARM: dts: Drop duplicate sha2md5_fck to fix clk_disable race
  Revert "ARM: dts: bcm2711: Add the BSC interrupt controller"
This commit is contained in:
Linus Torvalds 2021-04-07 09:26:50 -07:00
commit 3a22981230
17 changed files with 73 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/armada-385-turris-omnia.dts
View File

@ -32,7 +32,8 @@ soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs {
@ -389,6 +390,7 @@ &mdio {
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
marvell,reg-init = <3 18 0 0x4985>;
/* irq is connected to &pcawan pin 7 */
};

12
arch/arm/boot/dts/bcm2711.dtsi
View File

@ -308,14 +308,6 @@ dvp: clock@7ef00000 {
#reset-cells = <1>;
};
bsc_intr: interrupt-controller@7ef00040 {
compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
reg = <0x7ef00040 0x30>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
aon_intr: interrupt-controller@7ef00100 {
compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
reg = <0x7ef00100 0x30>;
@ -362,8 +354,6 @@ ddc0: i2c@7ef04500 {
reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
reg-names = "bsc", "auto-i2c";
clock-frequency = <97500>;
interrupt-parent = <&bsc_intr>;
interrupts = <0>;
status = "disabled";
};
@ -405,8 +395,6 @@ ddc1: i2c@7ef09500 {
reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
reg-names = "bsc", "auto-i2c";
clock-frequency = <97500>;
interrupt-parent = <&bsc_intr>;
interrupts = <1>;
status = "disabled";
};
};

2
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View File

@ -433,6 +433,7 @@ &usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vdd_sd1_reg>;
status = "disabled";
};
@ -442,5 +443,6 @@ &usdhc3 {
&pinctrl_usdhc3_cdwp>;
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&vdd_sd0_reg>;
status = "disabled";
};

5
arch/arm/boot/dts/omap4.dtsi
View File

@ -22,6 +22,11 @@ aliases {
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
mmc0 = &mmc1;
mmc1 = &mmc2;
mmc2 = &mmc3;
mmc3 = &mmc4;
mmc4 = &mmc5;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;

8
arch/arm/boot/dts/omap44xx-clocks.dtsi
View File

@ -770,14 +770,6 @@ per_abe_nc_fclk: per_abe_nc_fclk@108 {
ti,max-div = <2>;
};
sha2md5_fck: sha2md5_fck@15c8 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l3_div_ck>;
ti,bit-shift = <1>;
reg = <0x15c8>;
};
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";

5
arch/arm/boot/dts/omap5.dtsi
View File

@ -25,6 +25,11 @@ aliases {
i2c2 = &i2c3;
i2c3 = &i2c4;
i2c4 = &i2c5;
mmc0 = &mmc1;
mmc1 = &mmc2;
mmc2 = &mmc3;
mmc3 = &mmc4;
mmc4 = &mmc5;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;

4
arch/arm/mach-keystone/keystone.c
View File

@ -65,7 +65,7 @@ static void __init keystone_init(void)
static long long __init keystone_pv_fixup(void)
{
long long offset;
phys_addr_t mem_start, mem_end;
u64 mem_start, mem_end;
mem_start = memblock_start_of_DRAM();
mem_end = memblock_end_of_DRAM();
@ -78,7 +78,7 @@ static long long __init keystone_pv_fixup(void)
if (mem_start < KEYSTONE_HIGH_PHYS_START ||
mem_end > KEYSTONE_HIGH_PHYS_END) {
pr_crit("Invalid address space for memory (%08llx-%08llx)\n",
(u64)mem_start, (u64)mem_end);
mem_start, mem_end);
return 0;
}

1
arch/arm/mach-omap1/ams-delta-fiq-handler.S
View File

@ -15,6 +15,7 @@
#include <linux/platform_data/gpio-omap.h>
#include <asm/assembler.h>
#include <asm/irq.h>
#include "ams-delta-fiq.h"
#include "board-ams-delta.h"

39
arch/arm/mach-omap2/omap-secure.c
View File

@ -9,6 +9,7 @@
*/
#include <linux/arm-smccc.h>
#include <linux/cpu_pm.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
@ -20,6 +21,7 @@
#include "common.h"
#include "omap-secure.h"
#include "soc.h"
static phys_addr_t omap_secure_memblock_base;
@ -213,3 +215,40 @@ void __init omap_secure_init(void)
{
omap_optee_init_check();
}
/*
* Dummy dispatcher call after core OSWR and MPU off. Updates the ROM return
* address after MMU has been re-enabled after CPU1 has been woken up again.
* Otherwise the ROM code will attempt to use the earlier physical return
* address that got set with MMU off when waking up CPU1. Only used on secure
* devices.
*/
static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
{
switch (cmd) {
case CPU_CLUSTER_PM_EXIT:
omap_secure_dispatcher(OMAP4_PPA_SERVICE_0,
FLAG_START_CRITICAL,
0, 0, 0, 0, 0);
break;
default:
break;
}
return NOTIFY_OK;
}
static struct notifier_block secure_notifier_block = {
.notifier_call = cpu_notifier,
};
static int __init secure_pm_init(void)
{
if (omap_type() == OMAP2_DEVICE_TYPE_GP || !soc_is_omap44xx())
return 0;
cpu_pm_register_notifier(&secure_notifier_block);
return 0;
}
omap_arch_initcall(secure_pm_init);

1
arch/arm/mach-omap2/omap-secure.h
View File

@ -50,6 +50,7 @@
#define OMAP5_DRA7_MON_SET_ACR_INDEX 0x107
/* Secure PPA(Primary Protected Application) APIs */
#define OMAP4_PPA_SERVICE_0 0x21
#define OMAP4_PPA_L2_POR_INDEX 0x23
#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25

4
arch/arm/mach-omap2/pmic-cpcap.c
View File

@ -246,10 +246,10 @@ int __init omap4_cpcap_init(void)
omap_voltage_register_pmic(voltdm, &omap443x_max8952_mpu);
if (of_machine_is_compatible("motorola,droid-bionic")) {
voltdm = voltdm_lookup("mpu");
voltdm = voltdm_lookup("core");
omap_voltage_register_pmic(voltdm, &omap_cpcap_core);
voltdm = voltdm_lookup("mpu");
voltdm = voltdm_lookup("iva");
omap_voltage_register_pmic(voltdm, &omap_cpcap_iva);
} else {
voltdm = voltdm_lookup("core");

8
arch/arm/mach-pxa/mainstone.c
View File

@ -502,16 +502,20 @@ static inline void mainstone_init_keypad(void) {}
#endif
static int mst_pcmcia0_irqs[11] = {
[0 ... 10] = -1,
[0 ... 4] = -1,
[5] = MAINSTONE_S0_CD_IRQ,
[6 ... 7] = -1,
[8] = MAINSTONE_S0_STSCHG_IRQ,
[9] = -1,
[10] = MAINSTONE_S0_IRQ,
};
static int mst_pcmcia1_irqs[11] = {
[0 ... 10] = -1,
[0 ... 4] = -1,
[5] = MAINSTONE_S1_CD_IRQ,
[6 ... 7] = -1,
[8] = MAINSTONE_S1_STSCHG_IRQ,
[9] = -1,
[10] = MAINSTONE_S1_IRQ,
};

2
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
View File

@ -124,7 +124,7 @@
#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0

2
arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
View File

@ -130,7 +130,7 @@
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0

6
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
View File

@ -310,9 +310,11 @@ CP11X_LABEL(usb3_1): usb@510000 {
};
CP11X_LABEL(sata0): sata@540000 {
compatible = "marvell,armada-8k-ahci";
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
dma-coherent;
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP11X_LABEL(clk) 1 15>,
<&CP11X_LABEL(clk) 1 16>;
#address-cells = <1>;
@ -320,12 +322,10 @@ CP11X_LABEL(sata0): sata@540000 {
status = "disabled";
sata-port@0 {
interrupts = <109 IRQ_TYPE_LEVEL_HIGH>;
reg = <0>;
};
sata-port@1 {
interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
reg = <1>;
};
};

2
drivers/bus/mvebu-mbus.c
View File

@ -618,7 +618,7 @@ mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
* This part of the memory is above 4 GB, so we don't
* care for the MBus bridge hole.
*/
if (reg_start >= 0x100000000ULL)
if ((u64)reg_start >= 0x100000000ULL)
continue;
/*

2
drivers/soc/fsl/qbman/qman.c
View File

@ -186,7 +186,7 @@ struct qm_eqcr_entry {
__be32 tag;
struct qm_fd fd;
u8 __reserved3[32];
} __packed;
} __packed __aligned(8);
#define QM_EQCR_VERB_VBIT 0x80
#define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
#define QM_EQCR_VERB_CMD_ENQUEUE 0x01