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phy: qcom-qmp-ufs: cleanup the driver
Remove the conditionals and options that are not used by any of UFS PHY devices. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-23-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Vinod Koul
parent
4856865b0d
commit
3e1865ba38
@ -599,47 +599,16 @@ struct qmp_phy_cfg {
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/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
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const struct qmp_phy_init_tbl *serdes_tbl;
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int serdes_tbl_num;
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const struct qmp_phy_init_tbl *serdes_tbl_sec;
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int serdes_tbl_num_sec;
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const struct qmp_phy_init_tbl *tx_tbl;
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int tx_tbl_num;
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const struct qmp_phy_init_tbl *tx_tbl_sec;
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int tx_tbl_num_sec;
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const struct qmp_phy_init_tbl *rx_tbl;
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int rx_tbl_num;
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const struct qmp_phy_init_tbl *rx_tbl_sec;
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int rx_tbl_num_sec;
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const struct qmp_phy_init_tbl *pcs_tbl;
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int pcs_tbl_num;
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const struct qmp_phy_init_tbl *pcs_tbl_sec;
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int pcs_tbl_num_sec;
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const struct qmp_phy_init_tbl *pcs_misc_tbl;
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int pcs_misc_tbl_num;
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const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
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int pcs_misc_tbl_num_sec;
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/* Init sequence for DP PHY block link rates */
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const struct qmp_phy_init_tbl *serdes_tbl_rbr;
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int serdes_tbl_rbr_num;
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const struct qmp_phy_init_tbl *serdes_tbl_hbr;
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int serdes_tbl_hbr_num;
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const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
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int serdes_tbl_hbr2_num;
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const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
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int serdes_tbl_hbr3_num;
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/* DP PHY callbacks */
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int (*configure_dp_phy)(struct qmp_phy *qphy);
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void (*configure_dp_tx)(struct qmp_phy *qphy);
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int (*calibrate_dp_phy)(struct qmp_phy *qphy);
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void (*dp_aux_init)(struct qmp_phy *qphy);
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/* clock ids to be requested */
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const char * const *clk_list;
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int num_clks;
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/* resets to be requested */
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const char * const *reset_list;
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int num_resets;
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/* regulators to be requested */
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const char * const *vreg_list;
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int num_vregs;
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@ -649,22 +618,9 @@ struct qmp_phy_cfg {
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unsigned int start_ctrl;
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unsigned int pwrdn_ctrl;
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unsigned int mask_com_pcs_ready;
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/* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
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unsigned int phy_status;
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/* true, if PHY has a separate PHY_COM control block */
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bool has_phy_com_ctrl;
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/* true, if PHY has a reset for individual lanes */
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bool has_lane_rst;
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/* true, if PHY needs delay after POWER_DOWN */
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bool has_pwrdn_delay;
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/* power_down delay in usec */
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int pwrdn_delay_min;
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int pwrdn_delay_max;
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/* true, if PHY has a separate DP_COM control block */
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bool has_phy_dp_com_ctrl;
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/* true, if PHY has secondary tx/rx lanes to be configured */
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bool is_dual_lane_phy;
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@ -672,11 +628,6 @@ struct qmp_phy_cfg {
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bool no_pcs_sw_reset;
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};
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struct qmp_phy_combo_cfg {
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const struct qmp_phy_cfg *usb_cfg;
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const struct qmp_phy_cfg *dp_cfg;
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};
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/**
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* struct qmp_phy - per-lane phy descriptor
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*
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@ -689,14 +640,9 @@ struct qmp_phy_combo_cfg {
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* @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
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* @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
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* @pcs_misc: iomapped memory space for lane's pcs_misc
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* @pipe_clk: pipe clock
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* @index: lane index
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* @qmp: QMP phy to which this lane belongs
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* @lane_rst: lane's reset controller
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* @mode: current PHY mode
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* @dp_aux_cfg: Display port aux config
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* @dp_opts: Display port optional config
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* @dp_clks: Display port clocks
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*/
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struct qmp_phy {
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struct phy *phy;
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@ -708,27 +654,15 @@ struct qmp_phy {
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void __iomem *tx2;
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void __iomem *rx2;
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void __iomem *pcs_misc;
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struct clk *pipe_clk;
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unsigned int index;
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struct qcom_qmp *qmp;
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struct reset_control *lane_rst;
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enum phy_mode mode;
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unsigned int dp_aux_cfg;
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struct phy_configure_opts_dp dp_opts;
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struct qmp_phy_dp_clks *dp_clks;
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};
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struct qmp_phy_dp_clks {
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struct qmp_phy *qphy;
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struct clk_hw dp_link_hw;
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struct clk_hw dp_pixel_hw;
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};
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/**
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* struct qcom_qmp - structure holding QMP phy block attributes
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*
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* @dev: device
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* @dp_com: iomapped memory space for phy's dp_com control block
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*
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* @clks: array of clocks required by phy
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* @resets: array of resets required by phy
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@ -741,10 +675,8 @@ struct qmp_phy_dp_clks {
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*/
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struct qcom_qmp {
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struct device *dev;
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void __iomem *dp_com;
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struct clk_bulk_data *clks;
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struct reset_control **resets;
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struct regulator_bulk_data *vregs;
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struct qmp_phy **phys;
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@ -871,7 +803,6 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
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.start_ctrl = SERDES_START,
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.pwrdn_ctrl = SW_PWRDN,
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.is_dual_lane_phy = false,
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.no_pcs_sw_reset = true,
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};
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@ -983,37 +914,12 @@ static void qcom_qmp_phy_ufs_configure(void __iomem *base,
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static int qcom_qmp_phy_ufs_serdes_init(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
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int serdes_tbl_num = cfg->serdes_tbl_num;
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int ret;
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qcom_qmp_phy_ufs_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
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if (cfg->serdes_tbl_sec)
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qcom_qmp_phy_ufs_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
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cfg->serdes_tbl_num_sec);
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if (cfg->has_phy_com_ctrl) {
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void __iomem *status;
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unsigned int mask, val;
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qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
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qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
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SERDES_START | PCS_START);
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status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
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mask = cfg->mask_com_pcs_ready;
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ret = readl_poll_timeout(status, val, (val & mask), 10,
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PHY_INIT_COMPLETE_TIMEOUT);
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if (ret) {
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dev_err(qmp->dev,
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"phy common block init timed-out\n");
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return ret;
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}
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}
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return 0;
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}
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@ -1022,10 +928,8 @@ static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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void __iomem *pcs = qphy->pcs;
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void __iomem *dp_com = qmp->dp_com;
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int ret, i;
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int ret;
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mutex_lock(&qmp->phy_mutex);
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if (qmp->init_count++) {
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@ -1040,71 +944,22 @@ static int qcom_qmp_phy_ufs_com_init(struct qmp_phy *qphy)
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goto err_unlock;
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}
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for (i = 0; i < cfg->num_resets; i++) {
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ret = reset_control_assert(qmp->resets[i]);
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if (ret) {
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dev_err(qmp->dev, "%s reset assert failed\n",
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cfg->reset_list[i]);
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goto err_disable_regulators;
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}
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}
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for (i = cfg->num_resets - 1; i >= 0; i--) {
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ret = reset_control_deassert(qmp->resets[i]);
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if (ret) {
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dev_err(qmp->dev, "%s reset deassert failed\n",
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qphy->cfg->reset_list[i]);
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goto err_assert_reset;
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}
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}
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ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
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if (ret)
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goto err_assert_reset;
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goto err_disable_regulators;
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if (cfg->has_phy_dp_com_ctrl) {
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qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
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SW_PWRDN);
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/* override hardware control for reset of qmp phy */
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qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
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SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
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SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
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/* Default type-c orientation, i.e CC1 */
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qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
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qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
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USB3_MODE | DP_MODE);
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/* bring both QMP USB and QMP DP PHYs PCS block out of reset */
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qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
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SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
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SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
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qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
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qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
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}
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if (cfg->has_phy_com_ctrl) {
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qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
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SW_PWRDN);
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} else {
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if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
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qphy_setbits(pcs,
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cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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cfg->pwrdn_ctrl);
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else
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qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
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cfg->pwrdn_ctrl);
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}
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if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
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qphy_setbits(pcs,
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cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
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cfg->pwrdn_ctrl);
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else
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qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
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cfg->pwrdn_ctrl);
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mutex_unlock(&qmp->phy_mutex);
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return 0;
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err_assert_reset:
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while (++i < cfg->num_resets)
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reset_control_assert(qmp->resets[i]);
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err_disable_regulators:
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regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
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err_unlock:
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@ -1117,8 +972,6 @@ static int qcom_qmp_phy_ufs_com_exit(struct qmp_phy *qphy)
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{
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struct qcom_qmp *qmp = qphy->qmp;
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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void __iomem *serdes = qphy->serdes;
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int i = cfg->num_resets;
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mutex_lock(&qmp->phy_mutex);
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if (--qmp->init_count) {
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@ -1127,17 +980,6 @@ static int qcom_qmp_phy_ufs_com_exit(struct qmp_phy *qphy)
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}
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reset_control_assert(qmp->ufs_reset);
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if (cfg->has_phy_com_ctrl) {
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qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
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SERDES_START | PCS_START);
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qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
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SW_RESET);
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qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
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SW_PWRDN);
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}
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while (--i >= 0)
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reset_control_assert(qmp->resets[i]);
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clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
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@ -1198,77 +1040,35 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy)
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void __iomem *tx = qphy->tx;
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void __iomem *rx = qphy->rx;
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void __iomem *pcs = qphy->pcs;
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void __iomem *pcs_misc = qphy->pcs_misc;
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void __iomem *status;
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unsigned int mask, val, ready;
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int ret;
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qcom_qmp_phy_ufs_serdes_init(qphy);
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if (cfg->has_lane_rst) {
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ret = reset_control_deassert(qphy->lane_rst);
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if (ret) {
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dev_err(qmp->dev, "lane%d reset deassert failed\n",
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qphy->index);
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return ret;
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}
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}
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ret = clk_prepare_enable(qphy->pipe_clk);
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if (ret) {
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dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
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goto err_reset_lane;
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}
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/* Tx, Rx, and PCS configurations */
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qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs,
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cfg->tx_tbl, cfg->tx_tbl_num, 1);
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if (cfg->tx_tbl_sec)
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qcom_qmp_phy_ufs_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
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cfg->tx_tbl_num_sec, 1);
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/* Configuration for other LANE for USB-DP combo PHY */
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if (cfg->is_dual_lane_phy) {
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qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs,
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cfg->tx_tbl, cfg->tx_tbl_num, 2);
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if (cfg->tx_tbl_sec)
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qcom_qmp_phy_ufs_configure_lane(qphy->tx2, cfg->regs,
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cfg->tx_tbl_sec,
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cfg->tx_tbl_num_sec, 2);
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}
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qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs,
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cfg->rx_tbl, cfg->rx_tbl_num, 1);
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if (cfg->rx_tbl_sec)
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qcom_qmp_phy_ufs_configure_lane(rx, cfg->regs,
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cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
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if (cfg->is_dual_lane_phy) {
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qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs,
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cfg->rx_tbl, cfg->rx_tbl_num, 2);
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if (cfg->rx_tbl_sec)
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qcom_qmp_phy_ufs_configure_lane(qphy->rx2, cfg->regs,
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cfg->rx_tbl_sec,
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cfg->rx_tbl_num_sec, 2);
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}
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qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
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if (cfg->pcs_tbl_sec)
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qcom_qmp_phy_ufs_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
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cfg->pcs_tbl_num_sec);
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ret = reset_control_deassert(qmp->ufs_reset);
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if (ret)
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goto err_disable_pipe_clk;
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qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
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cfg->pcs_misc_tbl_num);
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if (cfg->pcs_misc_tbl_sec)
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qcom_qmp_phy_ufs_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
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cfg->pcs_misc_tbl_num_sec);
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if (cfg->has_pwrdn_delay)
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usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
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return ret;
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/* Pull PHY out of reset state */
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if (!cfg->no_pcs_sw_reset)
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@ -1284,17 +1084,10 @@ static int qcom_qmp_phy_ufs_power_on(struct phy *phy)
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PHY_INIT_COMPLETE_TIMEOUT);
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if (ret) {
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dev_err(qmp->dev, "phy initialization timed-out\n");
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goto err_disable_pipe_clk;
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return ret;
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}
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return 0;
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err_disable_pipe_clk:
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clk_disable_unprepare(qphy->pipe_clk);
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err_reset_lane:
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if (cfg->has_lane_rst)
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reset_control_assert(qphy->lane_rst);
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return ret;
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}
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static int qcom_qmp_phy_ufs_power_off(struct phy *phy)
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@ -1302,8 +1095,6 @@ static int qcom_qmp_phy_ufs_power_off(struct phy *phy)
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struct qmp_phy *qphy = phy_get_drvdata(phy);
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const struct qmp_phy_cfg *cfg = qphy->cfg;
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clk_disable_unprepare(qphy->pipe_clk);
|
||||
|
||||
/* PHY reset */
|
||||
if (!cfg->no_pcs_sw_reset)
|
||||
qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
|
||||
@ -1326,10 +1117,6 @@ static int qcom_qmp_phy_ufs_power_off(struct phy *phy)
|
||||
static int qcom_qmp_phy_ufs_exit(struct phy *phy)
|
||||
{
|
||||
struct qmp_phy *qphy = phy_get_drvdata(phy);
|
||||
const struct qmp_phy_cfg *cfg = qphy->cfg;
|
||||
|
||||
if (cfg->has_lane_rst)
|
||||
reset_control_assert(qphy->lane_rst);
|
||||
|
||||
qcom_qmp_phy_ufs_com_exit(qphy);
|
||||
|
||||
@ -1387,31 +1174,6 @@ static int qcom_qmp_phy_ufs_vreg_init(struct device *dev, const struct qmp_phy_c
|
||||
return devm_regulator_bulk_get(dev, num, qmp->vregs);
|
||||
}
|
||||
|
||||
static int qcom_qmp_phy_ufs_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
|
||||
{
|
||||
struct qcom_qmp *qmp = dev_get_drvdata(dev);
|
||||
int i;
|
||||
|
||||
qmp->resets = devm_kcalloc(dev, cfg->num_resets,
|
||||
sizeof(*qmp->resets), GFP_KERNEL);
|
||||
if (!qmp->resets)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < cfg->num_resets; i++) {
|
||||
struct reset_control *rst;
|
||||
const char *name = cfg->reset_list[i];
|
||||
|
||||
rst = devm_reset_control_get_exclusive(dev, name);
|
||||
if (IS_ERR(rst)) {
|
||||
dev_err(dev, "failed to get %s reset\n", name);
|
||||
return PTR_ERR(rst);
|
||||
}
|
||||
qmp->resets[i] = rst;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int qcom_qmp_phy_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
|
||||
{
|
||||
struct qcom_qmp *qmp = dev_get_drvdata(dev);
|
||||
@ -1435,11 +1197,6 @@ static const struct phy_ops qcom_qmp_ufs_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static void qcom_qmp_reset_control_put(void *data)
|
||||
{
|
||||
reset_control_put(data);
|
||||
}
|
||||
|
||||
static
|
||||
int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id,
|
||||
void __iomem *serdes, const struct qmp_phy_cfg *cfg)
|
||||
@ -1447,7 +1204,6 @@ int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id,
|
||||
struct qcom_qmp *qmp = dev_get_drvdata(dev);
|
||||
struct phy *generic_phy;
|
||||
struct qmp_phy *qphy;
|
||||
char prop_name[MAX_PROP_NAME];
|
||||
int ret;
|
||||
|
||||
qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
|
||||
@ -1503,20 +1259,6 @@ int qcom_qmp_phy_ufs_create(struct device *dev, struct device_node *np, int id,
|
||||
if (!qphy->pcs_misc)
|
||||
dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
|
||||
|
||||
/* Get lane reset, if any */
|
||||
if (cfg->has_lane_rst) {
|
||||
snprintf(prop_name, sizeof(prop_name), "lane%d", id);
|
||||
qphy->lane_rst = of_reset_control_get_exclusive(np, prop_name);
|
||||
if (IS_ERR(qphy->lane_rst)) {
|
||||
dev_err(dev, "failed to get lane%d reset\n", id);
|
||||
return PTR_ERR(qphy->lane_rst);
|
||||
}
|
||||
ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
|
||||
qphy->lane_rst);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
generic_phy = devm_phy_create(dev, np, &qcom_qmp_ufs_ops);
|
||||
if (IS_ERR(generic_phy)) {
|
||||
ret = PTR_ERR(generic_phy);
|
||||
@ -1600,13 +1342,6 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(serdes))
|
||||
return PTR_ERR(serdes);
|
||||
|
||||
/* per PHY dp_com; if PHY has dp_com control block */
|
||||
if (cfg->has_phy_dp_com_ctrl) {
|
||||
qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(qmp->dp_com))
|
||||
return PTR_ERR(qmp->dp_com);
|
||||
}
|
||||
|
||||
expected_phys = cfg->nlanes;
|
||||
|
||||
mutex_init(&qmp->phy_mutex);
|
||||
@ -1615,10 +1350,6 @@ static int qcom_qmp_phy_ufs_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qcom_qmp_phy_ufs_reset_init(dev, cfg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = qcom_qmp_phy_ufs_vreg_init(dev, cfg);
|
||||
if (ret) {
|
||||
if (ret != -EPROBE_DEFER)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user