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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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mvebu dt64 for 6.8 (part 1)
Add devices tree for CN9130 and CN9131 COM Express Boards Fix device tree for Turris Mox and for switch nodes -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCZYMcVwAKCRALBhiOFHI7 1eErAJ9GBlkV0RajfdpdZyjBxu+ECMwvzgCgi/xiyDDd4Z/gkqop+BrcKKSds5g= =Q5PI -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmWEcIgACgkQYKtH/8kJ Uienyw/9ETdLhSNPMMZA9YHd4Cym0pLG9s4vdNLpw6ywHysY3bTj4J6x5O4Q7TAM nmXzbL0fb/npf+V9jm28cJ6g8x70BZDK/iMKP0YOgSoAIBOY3Tm+AFZPD5cagw9t UV3mPZVhjpWcHR/QHzjhChQ6pXW5yS0DRzTaEWKiHdn9x6My+c6DYO5Fpm+DPLYq TryGkczuXCASXc4graxB2Dbe/JX7IfXDyyoTmqSsU1ALIAYIOzzCovCQ96+8+xow wt4cf6hFKjp5giVC7GxAH0Mn8rlm0XNlieEgMUF0rvQVo2AnJijDIMqEsmjSTxQs yijOTz8cex63TrBZ8P5N6UrsfgGKRrY9vo6GIO8W9wiDa+xwHPyPCMv01fwZczDU YzwrLE/zUsuV8xwhJrTMff66YyPBW5X5nvOH7qrMXXMzNQ5RLdIZMTjB+lNpBVJ1 MdzdGbkmAQfYO2VY4LOBnOhAisjOs1+xwiagtpfbO/5+R7mGBTi/P28K/0y9Azb8 bAyNnz+/qspT7GYVrvdPQM5aHSAT/A1btY/X2XCY7lGpCsQIN6CoGaN7X6Oki9er 0kqy3SNDDsDlHEPkuaswH36mzoFVoxM39Wqnm5ESooKMNiHQzfsHEvfoP4JXmglA dPoVIaHQFXL+ycfxqcTWmzpDaRARn6mVzeBntktbovVHNBPuKe4= =r+JP -----END PGP SIGNATURE----- Merge tag 'mvebu-dt64-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt mvebu dt64 for 6.8 (part 1) Add devices tree for CN9130 and CN9131 COM Express Boards Fix device tree for Turris Mox and for switch nodes * tag 'mvebu-dt64-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: cn913x: add device trees for COM Express boards dt-bindings: arm64: add Marvell COM Express boards MAINTAINERS: add ac5 to list of maintained Marvell dts files arm64: dts: armada-3720-turris-mox: set irq type for RTC ARM64: dts: Add special compatibles for the Turris Mox ARM64: dts: marvell: Fix some common switch mistakes Link: https://lore.kernel.org/r/87le9obypx.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
46a51dba9f
@ -60,4 +60,26 @@ properties:
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- const: marvell,armada-ap807-quad
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- const: marvell,armada-ap807
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- description:
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Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
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Armada CN9130 COM Express CPU module
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items:
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- const: marvell,cn9130-ac5x-carrier
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- const: marvell,rd-ac5x-carrier
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- const: marvell,cn9130-cpu-module
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- const: marvell,cn9130
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- const: marvell,armada-ap807-quad
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- const: marvell,armada-ap807
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- description:
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Alleycat5X (98DX35xx) Reference Design as COM Express Carrier plus
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Armada CN9131 COM Express CPU module
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items:
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- const: marvell,cn9131-ac5x-carrier
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- const: marvell,rd-ac5x-carrier
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- const: marvell,cn9131-cpu-module
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- const: marvell,cn9131
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- const: marvell,armada-ap807-quad
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- const: marvell,armada-ap807
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additionalProperties: true
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@ -2332,8 +2332,7 @@ F: arch/arm/boot/dts/marvell/armada*
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F: arch/arm/boot/dts/marvell/kirkwood*
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F: arch/arm/configs/mvebu_*_defconfig
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F: arch/arm/mach-mvebu/
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F: arch/arm64/boot/dts/marvell/armada*
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F: arch/arm64/boot/dts/marvell/cn913*
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F: arch/arm64/boot/dts/marvell/
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F: drivers/clk/mvebu/
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F: drivers/cpufreq/armada-37xx-cpufreq.c
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F: drivers/cpufreq/armada-8k-cpufreq.c
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@ -26,4 +26,5 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
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44
arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
Normal file
44
arch/arm64/boot/dts/marvell/ac5x-rd-carrier-cn9131.dts
Normal file
@ -0,0 +1,44 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2023 Marvell International Ltd.
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*
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* Device tree for the AC5X RD Type 7 Com Express carrier board,
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* Utilizing the CN913x COM Express CPU module board.
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* This specific carrier board in this mode of operation (external)
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* only maintains a PCIe link with the CPU module,
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* which does not require any special DTS definitions.
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*
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* AC5X RD works here in external mode (switch selectable at the back of the
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* board), and connect via an external cable a kit
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* which would allow it to use an external CN9131 CPU COM Express module,
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* mounted on top of an interposer kit.
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*
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* So in this case, once the switch is set to external mode as explained above,
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* the AC5X RD becomes part of the carrier solution.
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*
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* When the board boots in the external CPU mode, the internal CPU is disabled,
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* and only the switch portion of the SOC acts as a PCIe end-point, Hence there
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* is no need to describe this internal (disabled CPU) in the device tree.
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*
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* There is no CPU booting in this mode on the carrier, only on the
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* CN9131 COM Express CPU module.
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* What runs the Linux is the CN9131 on the COM Express CPU module,
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* And it accesses the switch end-point on the AC5X RD portion of the carrier
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* via PCIe.
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*/
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#include "cn9131-db-comexpress.dtsi"
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#include "ac5x-rd-carrier.dtsi"
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/ {
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model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board with CN9131 CPU module";
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compatible = "marvell,cn9131-ac5x-carrier", "marvell,rd-ac5x-carrier",
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"marvell,cn9131-cpu-module", "marvell,cn9131",
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"marvell,armada-ap807-quad", "marvell,armada-ap807";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x2 0x00000000>;
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};
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};
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34
arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
Normal file
34
arch/arm64/boot/dts/marvell/ac5x-rd-carrier.dtsi
Normal file
@ -0,0 +1,34 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2023 Marvell International Ltd.
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*
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* Device tree for the AC5X RD Type 7 Com Express carrier board,
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* This specific board in external mode (see below) only maintains
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* a PCIe link with the COM Express CPU module, which does not
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* require any special DTS definitions.
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*
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* AC5X RD can either work as you would expect, as a complete standalone
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* box using the internal CPU, or you can move the switch on the back of
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* the box to "external" mode, and connect via an external cable a kit
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* which would allow it to use an external CPU COM Express module,
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* mounted on top of an interposer kit.
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*
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* So in this case, once the switch is set to external mode as explained above,
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* the AC5X RD becomes part of the carrier solution.
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* This is a development/reference solution, not a full commercial solution,
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* hence it was designed with the flexibility to be configured in different
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* modes of operation.
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*
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* When the board boots in the external CPU mode, the internal CPU is disabled,
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* and only the switch portion of the SOC acts as a PCIe end-point, Hence there
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* is no need to describe this internal (disabled CPU) in the device tree.
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*
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* There is no CPU booting in this mode on the carrier,
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* only on the COM Express CPU module.
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*/
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/ {
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model = "Marvell Armada AC5X RD COM EXPRESS type 7 carrier board";
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compatible = "marvell,rd-ac5x-carrier";
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};
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@ -126,32 +126,32 @@ &switch0 {
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reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
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ports {
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switch0port1: port@1 {
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ethernet-ports {
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switch0port1: ethernet-port@1 {
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reg = <1>;
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label = "lan0";
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phy-handle = <&switch0phy0>;
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};
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switch0port2: port@2 {
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switch0port2: ethernet-port@2 {
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reg = <2>;
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label = "lan1";
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phy-handle = <&switch0phy1>;
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};
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switch0port3: port@3 {
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switch0port3: ethernet-port@3 {
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reg = <3>;
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label = "lan2";
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phy-handle = <&switch0phy2>;
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};
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switch0port4: port@4 {
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switch0port4: ethernet-port@4 {
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reg = <4>;
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label = "lan3";
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phy-handle = <&switch0phy3>;
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};
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switch0port5: port@5 {
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switch0port5: ethernet-port@5 {
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reg = <5>;
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label = "wan";
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phy-handle = <&extphy>;
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@ -160,7 +160,7 @@ switch0port5: port@5 {
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};
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mdio {
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switch0phy3: switch0phy3@14 {
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switch0phy3: ethernet-phy@14 {
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reg = <0x14>;
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};
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};
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@ -145,19 +145,17 @@ &usb2 {
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};
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&mdio {
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switch0: switch0@1 {
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switch0: ethernet-switch@1 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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dsa,member = <0 0>;
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ports {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0port0: port@0 {
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switch0port0: ethernet-port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <ð0>;
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@ -168,19 +166,19 @@ fixed-link {
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};
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};
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switch0port1: port@1 {
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switch0port1: ethernet-port@1 {
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reg = <1>;
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label = "wan";
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phy-handle = <&switch0phy0>;
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};
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switch0port2: port@2 {
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switch0port2: ethernet-port@2 {
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reg = <2>;
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label = "lan0";
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phy-handle = <&switch0phy1>;
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};
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switch0port3: port@3 {
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switch0port3: ethernet-port@3 {
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reg = <3>;
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label = "lan1";
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phy-handle = <&switch0phy2>;
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@ -192,13 +190,13 @@ mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: switch0phy0@11 {
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switch0phy0: ethernet-phy@11 {
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reg = <0x11>;
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};
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switch0phy1: switch0phy1@12 {
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switch0phy1: ethernet-phy@12 {
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reg = <0x12>;
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};
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switch0phy2: switch0phy2@13 {
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switch0phy2: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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@ -152,31 +152,29 @@ &uart0 {
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};
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&mdio {
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switch0: switch0@1 {
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switch0: ethernet-switch@1 {
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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dsa,member = <0 0>;
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ports: ports {
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ports: ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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ethernet-port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <ð0>;
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};
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port@1 {
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ethernet-port@1 {
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reg = <1>;
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label = "wan";
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phy-handle = <&switch0phy0>;
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};
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port@2 {
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ethernet-port@2 {
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reg = <2>;
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label = "lan0";
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phy-handle = <&switch0phy1>;
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@ -185,7 +183,7 @@ port@2 {
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nvmem-cell-names = "mac-address";
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};
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port@3 {
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ethernet-port@3 {
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reg = <3>;
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label = "lan1";
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phy-handle = <&switch0phy2>;
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@ -199,13 +197,13 @@ mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: switch0phy0@11 {
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switch0phy0: ethernet-phy@11 {
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reg = <0x11>;
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};
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switch0phy1: switch0phy1@12 {
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switch0phy1: ethernet-phy@12 {
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reg = <0x12>;
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};
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switch0phy2: switch0phy2@13 {
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switch0phy2: ethernet-phy@13 {
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reg = <0x13>;
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};
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};
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@ -130,7 +130,7 @@ rtc@6f {
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compatible = "microchip,mcp7940x";
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reg = <0x6f>;
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interrupt-parent = <&gpiosb>;
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interrupts = <5 0>; /* GPIO2_5 */
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interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO2_5 */
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};
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};
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@ -304,9 +304,15 @@ phy1: ethernet-phy@1 {
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reg = <1>;
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};
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/* switch nodes are enabled by U-Boot if modules are present */
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/*
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* NOTE: switch nodes are enabled by U-Boot if modules are present
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* DO NOT change this node name (switch0@10) even if it is not following
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* conventions! Deployed U-Boot binaries are explicitly looking for
|
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* this node in order to augment the device tree!
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* Also do not touch the "ports" or "port@n" nodes. These are also ABI.
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*/
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switch0@10 {
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compatible = "marvell,mv88e6190";
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compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";
|
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reg = <0x10>;
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dsa,member = <0 0>;
|
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interrupt-parent = <&moxtet>;
|
||||
@ -317,35 +323,35 @@ mdio {
|
||||
#address-cells = <1>;
|
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#size-cells = <0>;
|
||||
|
||||
switch0phy1: switch0phy1@1 {
|
||||
switch0phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@2 {
|
||||
switch0phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@3 {
|
||||
switch0phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy4: switch0phy4@4 {
|
||||
switch0phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch0phy5: switch0phy5@5 {
|
||||
switch0phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy6: switch0phy6@6 {
|
||||
switch0phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy7: switch0phy7@7 {
|
||||
switch0phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy8: switch0phy8@8 {
|
||||
switch0phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
@ -430,8 +436,9 @@ port-sfp@a {
|
||||
};
|
||||
};
|
||||
|
||||
/* NOTE: this node name is ABI, don't change it! */
|
||||
switch0@2 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";
|
||||
reg = <0x2>;
|
||||
dsa,member = <0 0>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
@ -442,19 +449,19 @@ mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy1_topaz: switch0phy1@11 {
|
||||
switch0phy1_topaz: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch0phy2_topaz: switch0phy2@12 {
|
||||
switch0phy2_topaz: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch0phy3_topaz: switch0phy3@13 {
|
||||
switch0phy3_topaz: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch0phy4_topaz: switch0phy4@14 {
|
||||
switch0phy4_topaz: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
@ -497,8 +504,9 @@ port@5 {
|
||||
};
|
||||
};
|
||||
|
||||
/* NOTE: this node name is ABI, don't change it! */
|
||||
switch1@11 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";
|
||||
reg = <0x11>;
|
||||
dsa,member = <0 1>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
@ -509,35 +517,35 @@ mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch1phy1: switch1phy1@1 {
|
||||
switch1phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch1phy2: switch1phy2@2 {
|
||||
switch1phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch1phy3: switch1phy3@3 {
|
||||
switch1phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch1phy4: switch1phy4@4 {
|
||||
switch1phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch1phy5: switch1phy5@5 {
|
||||
switch1phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch1phy6: switch1phy6@6 {
|
||||
switch1phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch1phy7: switch1phy7@7 {
|
||||
switch1phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch1phy8: switch1phy8@8 {
|
||||
switch1phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
@ -622,8 +630,9 @@ port-sfp@a {
|
||||
};
|
||||
};
|
||||
|
||||
/* NOTE: this node name is ABI, don't change it! */
|
||||
switch1@2 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";
|
||||
reg = <0x2>;
|
||||
dsa,member = <0 1>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
@ -634,19 +643,19 @@ mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch1phy1_topaz: switch1phy1@11 {
|
||||
switch1phy1_topaz: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch1phy2_topaz: switch1phy2@12 {
|
||||
switch1phy2_topaz: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch1phy3_topaz: switch1phy3@13 {
|
||||
switch1phy3_topaz: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch1phy4_topaz: switch1phy4@14 {
|
||||
switch1phy4_topaz: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
@ -689,8 +698,9 @@ port@5 {
|
||||
};
|
||||
};
|
||||
|
||||
/* NOTE: this node name is ABI, don't change it! */
|
||||
switch2@12 {
|
||||
compatible = "marvell,mv88e6190";
|
||||
compatible = "marvell,turris-mox-mv88e6190", "marvell,mv88e6190";
|
||||
reg = <0x12>;
|
||||
dsa,member = <0 2>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
@ -701,35 +711,35 @@ mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch2phy1: switch2phy1@1 {
|
||||
switch2phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch2phy2: switch2phy2@2 {
|
||||
switch2phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch2phy3: switch2phy3@3 {
|
||||
switch2phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch2phy4: switch2phy4@4 {
|
||||
switch2phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch2phy5: switch2phy5@5 {
|
||||
switch2phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch2phy6: switch2phy6@6 {
|
||||
switch2phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch2phy7: switch2phy7@7 {
|
||||
switch2phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch2phy8: switch2phy8@8 {
|
||||
switch2phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
@ -805,8 +815,9 @@ port-sfp@a {
|
||||
};
|
||||
};
|
||||
|
||||
/* NOTE: this node name is ABI, don't change it! */
|
||||
switch2@2 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
compatible = "marvell,turris-mox-mv88e6085", "marvell,mv88e6085";
|
||||
reg = <0x2>;
|
||||
dsa,member = <0 2>;
|
||||
interrupt-parent = <&moxtet>;
|
||||
@ -817,19 +828,19 @@ mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch2phy1_topaz: switch2phy1@11 {
|
||||
switch2phy1_topaz: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch2phy2_topaz: switch2phy2@12 {
|
||||
switch2phy2_topaz: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch2phy3_topaz: switch2phy3@13 {
|
||||
switch2phy3_topaz: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch2phy4_topaz: switch2phy4@14 {
|
||||
switch2phy4_topaz: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -301,10 +301,8 @@ eth2phy: ethernet-phy@1 {
|
||||
};
|
||||
|
||||
/* 88E6141 Topaz switch */
|
||||
switch: switch@3 {
|
||||
switch: ethernet-switch@3 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
@ -314,35 +312,35 @@ switch: switch@3 {
|
||||
interrupt-parent = <&cp0_gpio1>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
swport1: port@1 {
|
||||
swport1: ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan0";
|
||||
phy-handle = <&swphy1>;
|
||||
};
|
||||
|
||||
swport2: port@2 {
|
||||
swport2: ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan1";
|
||||
phy-handle = <&swphy2>;
|
||||
};
|
||||
|
||||
swport3: port@3 {
|
||||
swport3: ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan2";
|
||||
phy-handle = <&swphy3>;
|
||||
};
|
||||
|
||||
swport4: port@4 {
|
||||
swport4: ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan3";
|
||||
phy-handle = <&swphy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&cp0_eth1>;
|
||||
@ -355,19 +353,19 @@ mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
swphy1: swphy1@17 {
|
||||
swphy1: ethernet-phy@17 {
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
swphy2: swphy2@18 {
|
||||
swphy2: ethernet-phy@18 {
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
swphy3: swphy3@19 {
|
||||
swphy3: ethernet-phy@19 {
|
||||
reg = <19>;
|
||||
};
|
||||
|
||||
swphy4: swphy4@20 {
|
||||
swphy4: ethernet-phy@20 {
|
||||
reg = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -497,42 +497,42 @@ ge_phy: ethernet-phy@0 {
|
||||
reset-deassert-us = <10000>;
|
||||
};
|
||||
|
||||
switch0: switch0@4 {
|
||||
switch0: ethernet-switch@4 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_switch_reset_pins>;
|
||||
reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
phy-handle = <&switch0phy0>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&cp1_eth2>;
|
||||
@ -545,19 +545,19 @@ mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: switch0phy0@11 {
|
||||
switch0phy0: ethernet-phy@11 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
switch0phy1: switch0phy1@12 {
|
||||
switch0phy1: ethernet-phy@12 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@13 {
|
||||
switch0phy2: ethernet-phy@13 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@14 {
|
||||
switch0phy3: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -207,11 +207,9 @@ phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
switch6: switch0@6 {
|
||||
switch6: ethernet-switch@6 {
|
||||
/* Actual device is MV88E6393X */
|
||||
compatible = "marvell,mv88e6190";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
interrupt-parent = <&cp0_gpio1>;
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
|
||||
@ -220,59 +218,59 @@ switch6: switch0@6 {
|
||||
|
||||
dsa,member = <0 0>;
|
||||
|
||||
ports {
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@1 {
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "p1";
|
||||
phy-handle = <&switch0phy1>;
|
||||
};
|
||||
|
||||
port@2 {
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "p2";
|
||||
phy-handle = <&switch0phy2>;
|
||||
};
|
||||
|
||||
port@3 {
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "p3";
|
||||
phy-handle = <&switch0phy3>;
|
||||
};
|
||||
|
||||
port@4 {
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "p4";
|
||||
phy-handle = <&switch0phy4>;
|
||||
};
|
||||
|
||||
port@5 {
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "p5";
|
||||
phy-handle = <&switch0phy5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "p6";
|
||||
phy-handle = <&switch0phy6>;
|
||||
};
|
||||
|
||||
port@7 {
|
||||
ethernet-port@7 {
|
||||
reg = <7>;
|
||||
label = "p7";
|
||||
phy-handle = <&switch0phy7>;
|
||||
};
|
||||
|
||||
port@8 {
|
||||
ethernet-port@8 {
|
||||
reg = <8>;
|
||||
label = "p8";
|
||||
phy-handle = <&switch0phy8>;
|
||||
};
|
||||
|
||||
port@9 {
|
||||
ethernet-port@9 {
|
||||
reg = <9>;
|
||||
label = "p9";
|
||||
phy-mode = "10gbase-r";
|
||||
@ -280,7 +278,7 @@ port@9 {
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@a {
|
||||
ethernet-port@a {
|
||||
reg = <10>;
|
||||
ethernet = <&cp0_eth0>;
|
||||
phy-mode = "10gbase-r";
|
||||
@ -293,35 +291,35 @@ mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy1: switch0phy1@1 {
|
||||
switch0phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
switch0phy2: switch0phy2@2 {
|
||||
switch0phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy3: switch0phy3@3 {
|
||||
switch0phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy4: switch0phy4@4 {
|
||||
switch0phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
switch0phy5: switch0phy5@5 {
|
||||
switch0phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
|
||||
switch0phy6: switch0phy6@6 {
|
||||
switch0phy6: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
switch0phy7: switch0phy7@7 {
|
||||
switch0phy7: ethernet-phy@7 {
|
||||
reg = <0x7>;
|
||||
};
|
||||
|
||||
switch0phy8: switch0phy8@8 {
|
||||
switch0phy8: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
96
arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
Normal file
96
arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
Normal file
@ -0,0 +1,96 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2023 Marvell International Ltd.
|
||||
*
|
||||
* Device tree for the CN9130-DB Com Express CPU module board.
|
||||
*/
|
||||
|
||||
#include "cn9130-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
|
||||
compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
|
||||
"marvell,armada-ap807-quad", "marvell,armada-ap807";
|
||||
|
||||
};
|
||||
|
||||
&ap0_reg_sd_vccq {
|
||||
regulator-max-microvolt = <1800000>;
|
||||
states = <1800000 0x1 1800000 0x0>;
|
||||
/delete-property/ gpios;
|
||||
};
|
||||
|
||||
&cp0_reg_usb3_vbus0 {
|
||||
/delete-property/ gpio;
|
||||
};
|
||||
|
||||
&cp0_reg_usb3_vbus1 {
|
||||
/delete-property/ gpio;
|
||||
};
|
||||
|
||||
&cp0_reg_sd_vcc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_reg_sd_vccq {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_eth0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_eth1 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cp0_eth2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&cp0_ge_mdio_pins>;
|
||||
phy0: ethernet-phy@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp0_ge_mdio_pins: ge-mdio-pins {
|
||||
marvell,pins = "mpp40", "mpp41";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy0>;
|
||||
phy-names = "usb";
|
||||
/delete-property/ phys;
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy1>;
|
||||
phy-names = "usb";
|
||||
/delete-property/ phys;
|
||||
};
|
||||
108
arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
Normal file
108
arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi
Normal file
@ -0,0 +1,108 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2023 Marvell International Ltd.
|
||||
*
|
||||
* Device tree for the CN9131-DB Com Express CPU module board.
|
||||
*/
|
||||
|
||||
#include "cn9131-db.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada CN9131-DB COM EXPRESS type 7 CPU module board";
|
||||
compatible = "marvell,cn9131-cpu-module", "marvell,cn9131", "marvell,cn9130",
|
||||
"marvell,armada-ap807-quad", "marvell,armada-ap807";
|
||||
|
||||
};
|
||||
|
||||
&ap0_reg_sd_vccq {
|
||||
regulator-max-microvolt = <1800000>;
|
||||
states = <1800000 0x1 1800000 0x0>;
|
||||
/delete-property/ gpios;
|
||||
};
|
||||
|
||||
&cp0_reg_usb3_vbus0 {
|
||||
/delete-property/ gpio;
|
||||
};
|
||||
|
||||
&cp0_reg_usb3_vbus1 {
|
||||
/delete-property/ gpio;
|
||||
};
|
||||
|
||||
&cp1_reg_usb3_vbus0 {
|
||||
/delete-property/ gpio;
|
||||
};
|
||||
|
||||
&cp0_reg_sd_vcc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_reg_sd_vccq {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_eth0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_eth1 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
&cp0_eth2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&cp0_ge_mdio_pins>;
|
||||
phy0: ethernet-phy@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp0_ge_mdio_pins: ge-mdio-pins {
|
||||
marvell,pins = "mpp40", "mpp41";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_sdhci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_usb3_0 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy0>;
|
||||
phy-names = "usb";
|
||||
/delete-property/ phys;
|
||||
};
|
||||
|
||||
&cp0_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp0_usb3_0_phy1>;
|
||||
phy-names = "usb";
|
||||
/delete-property/ phys;
|
||||
};
|
||||
|
||||
&cp1_usb3_1 {
|
||||
status = "okay";
|
||||
usb-phy = <&cp1_usb3_0_phy0>;
|
||||
/* Generic PHY, providing serdes lanes */
|
||||
phys = <&cp1_comphy3 1>;
|
||||
phy-names = "usb";
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user