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- fix for boot issue on single core Lantiq Danube devices

Browse Source 
- fix for boot issue on Loongson64 platforms
 - fix for improper FPU setup
 - fix missing prototypes issues
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Merge tag 'mips-fixes_6.8_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS fixes from Thomas Bogendoerfer:

 - fix boot issue on single core Lantiq Danube devices

 - fix boot issue on Loongson64 platforms

 - fix improper FPU setup

 - fix missing prototypes issues

* tag 'mips-fixes_6.8_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  mips: Call lose_fpu(0) before initializing fcr31 in mips_set_personality_nan
  MIPS: loongson64: set nid for reserved memblock region
  Revert "MIPS: loongson64: set nid for reserved memblock region"
  MIPS: lantiq: register smp_ops on non-smp platforms
  MIPS: loongson64: set nid for reserved memblock region
  MIPS: reserve exception vector space ONLY ONCE
  MIPS: BCM63XX: Fix missing prototypes
  MIPS: sgi-ip32: Fix missing prototypes
  MIPS: sgi-ip30: Fix missing prototypes
  MIPS: fw arc: Fix missing prototypes
  MIPS: sgi-ip27: Fix missing prototypes
  MIPS: Alchemy: Fix missing prototypes
  MIPS: Cobalt: Fix missing prototypes
This commit is contained in:
Linus Torvalds 2024-01-28 10:43:06 -08:00
commit 4854cf9c61
34 changed files with 83 additions and 230 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/mips/alchemy/common/prom.c
View File

@ -40,6 +40,7 @@
#include <linux/string.h>
#include <asm/bootinfo.h>
#include <prom.h>
int prom_argc;
char **prom_argv;

4
arch/mips/alchemy/common/setup.c
View File

@ -30,13 +30,11 @@
#include <linux/mm.h>
#include <linux/dma-map-ops.h> /* for dma_default_coherent */
#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <au1000.h>
extern void __init board_setup(void);
extern void __init alchemy_set_lpj(void);
static bool alchemy_dma_coherent(void)
{
switch (alchemy_get_cputype()) {

2
arch/mips/bcm63xx/boards/board_bcm963xx.c
View File

@ -702,7 +702,7 @@ static struct ssb_sprom bcm63xx_sprom = {
.boardflags_hi = 0x0000,
};
int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
static int bcm63xx_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
{
if (bus->bustype == SSB_BUSTYPE_PCI) {
memcpy(out, &bcm63xx_sprom, sizeof(struct ssb_sprom));

2
arch/mips/bcm63xx/dev-rng.c
View File

@ -26,7 +26,7 @@ static struct platform_device bcm63xx_rng_device = {
.resource = rng_resources,
};
int __init bcm63xx_rng_register(void)
static int __init bcm63xx_rng_register(void)
{
if (!BCMCPU_IS_6368())
return -ENODEV;

1
arch/mips/bcm63xx/dev-uart.c
View File

@ -10,6 +10,7 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <bcm63xx_cpu.h>
#include <bcm63xx_dev_uart.h>
static struct resource uart0_resources[] = {
{

2
arch/mips/bcm63xx/dev-wdt.c
View File

@ -34,7 +34,7 @@ static struct platform_device bcm63xx_wdt_device = {
},
};
int __init bcm63xx_wdt_register(void)
static int __init bcm63xx_wdt_register(void)
{
wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT);
wdt_resources[0].end = wdt_resources[0].start;

2
arch/mips/bcm63xx/irq.c
View File

@ -72,7 +72,7 @@ static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
*/
#define BUILD_IPIC_INTERNAL(width) \
void __dispatch_internal_##width(int cpu) \
static void __dispatch_internal_##width(int cpu) \
{ \
u32 pending[width / 32]; \
unsigned int src, tgt; \

2
arch/mips/bcm63xx/setup.c
View File

@ -159,7 +159,7 @@ void __init plat_mem_setup(void)
board_setup();
}
int __init bcm63xx_register_devices(void)
static int __init bcm63xx_register_devices(void)
{
/* register gpiochip */
bcm63xx_gpio_init();

2
arch/mips/bcm63xx/timer.c
View File

@ -178,7 +178,7 @@ int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
EXPORT_SYMBOL(bcm63xx_timer_set);
int bcm63xx_timer_init(void)
static int bcm63xx_timer_init(void)
{
int ret, irq;
u32 reg;

3
arch/mips/cobalt/setup.c
View File

@ -23,9 +23,6 @@
#include <cobalt.h>
extern void cobalt_machine_restart(char *command);
extern void cobalt_machine_halt(void);
const char *get_system_type(void)
{
switch (cobalt_board_id) {

2
arch/mips/fw/arc/memory.c
View File

@ -37,7 +37,7 @@ static unsigned int nr_prom_mem __initdata;
*/
#define ARC_PAGE_SHIFT 12
struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current)
static struct linux_mdesc * __init ArcGetMemoryDescriptor(struct linux_mdesc *Current)
{
return (struct linux_mdesc *) ARC_CALL1(get_mdesc, Current);
}

3
arch/mips/include/asm/mach-au1x00/au1000.h
View File

@ -597,6 +597,9 @@
#include <asm/cpu.h>
void alchemy_set_lpj(void);
void board_setup(void);
/* helpers to access the SYS_* registers */
static inline unsigned long alchemy_rdsys(int regofs)
{

3
arch/mips/include/asm/mach-cobalt/cobalt.h
View File

@ -19,4 +19,7 @@ extern int cobalt_board_id;
#define COBALT_BRD_ID_QUBE2 0x5
#define COBALT_BRD_ID_RAQ2 0x6
void cobalt_machine_halt(void);
void cobalt_machine_restart(char *command);
#endif /* __ASM_COBALT_H */

6
arch/mips/kernel/elf.c
View File

@ -11,6 +11,7 @@
#include <asm/cpu-features.h>
#include <asm/cpu-info.h>
#include <asm/fpu.h>
#ifdef CONFIG_MIPS_FP_SUPPORT
@ -309,6 +310,11 @@ void mips_set_personality_nan(struct arch_elf_state *state)
struct cpuinfo_mips *c = &boot_cpu_data;
struct task_struct *t = current;
/* Do this early so t->thread.fpu.fcr31 won't be clobbered in case
* we are preempted before the lose_fpu(0) in start_thread.
*/
lose_fpu(0);
t->thread.fpu.fcr31 = c->fpu_csr31;
switch (state->nan_2008) {
case 0:

8
arch/mips/kernel/traps.c
View File

@ -2007,7 +2007,13 @@ unsigned long vi_handlers[64];
void reserve_exception_space(phys_addr_t addr, unsigned long size)
{
memblock_reserve(addr, size);
/*
* reserve exception space on CPUs other than CPU0
* is too late, since memblock is unavailable when APs
* up
*/
if (smp_processor_id() == 0)
memblock_reserve(addr, size);
}
void __init *set_except_vector(int n, void *addr)

7
arch/mips/lantiq/prom.c
View File

@ -108,10 +108,9 @@ void __init prom_init(void)
prom_init_cmdline();
#if defined(CONFIG_MIPS_MT_SMP)
if (cpu_has_mipsmt) {
lantiq_smp_ops = vsmp_smp_ops;
lantiq_smp_ops = vsmp_smp_ops;
if (cpu_has_mipsmt)
lantiq_smp_ops.init_secondary = lantiq_init_secondary;
register_smp_ops(&lantiq_smp_ops);
}
register_smp_ops(&lantiq_smp_ops);
#endif
}

3
arch/mips/loongson64/init.c
View File

@ -103,6 +103,9 @@ void __init szmem(unsigned int node)
if (loongson_sysconf.vgabios_addr)
memblock_reserve(virt_to_phys((void *)loongson_sysconf.vgabios_addr),
SZ_256K);
/* set nid for reserved memory */
memblock_set_node((u64)node << 44, (u64)(node + 1) << 44,
&memblock.reserved, node);
}
#ifndef CONFIG_NUMA

2
arch/mips/loongson64/numa.c
View File

@ -132,6 +132,8 @@ static void __init node_mem_init(unsigned int node)
/* Reserve pfn range 0~node[0]->node_start_pfn */
memblock_reserve(0, PAGE_SIZE * start_pfn);
/* set nid for reserved memory on node 0 */
memblock_set_node(0, 1ULL << 44, &memblock.reserved, 0);
}
}

2
arch/mips/sgi-ip27/Makefile
View File

@ -5,7 +5,7 @@
obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o \
ip27-klnuma.o ip27-memory.o ip27-nmi.o ip27-reset.o ip27-timer.o \
ip27-hubio.o ip27-xtalk.o
ip27-xtalk.o
obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o
obj-$(CONFIG_SMP) += ip27-smp.o

4
arch/mips/sgi-ip27/ip27-berr.c
View File

@ -22,6 +22,8 @@
#include <asm/traps.h>
#include <linux/uaccess.h>
#include "ip27-common.h"
static void dump_hub_information(unsigned long errst0, unsigned long errst1)
{
static char *err_type[2][8] = {
@ -57,7 +59,7 @@ static void dump_hub_information(unsigned long errst0, unsigned long errst1)
[st0.pi_stat0_fmt.s0_err_type] ? : "invalid");
}
int ip27_be_handler(struct pt_regs *regs, int is_fixup)
static int ip27_be_handler(struct pt_regs *regs, int is_fixup)
{
unsigned long errst0, errst1;
int data = regs->cp0_cause & 4;

2
arch/mips/sgi-ip27/ip27-common.h
View File

@ -10,6 +10,7 @@ extern void hub_rt_clock_event_init(void);
extern void hub_rtc_init(nasid_t nasid);
extern void install_cpu_nmi_handler(int slice);
extern void install_ipi(void);
extern void ip27_be_init(void);
extern void ip27_reboot_setup(void);
extern const struct plat_smp_ops ip27_smp_ops;
extern unsigned long node_getfirstfree(nasid_t nasid);
@ -17,4 +18,5 @@ extern void per_cpu_init(void);
extern void replicate_kernel_text(void);
extern void setup_replication_mask(void);
#endif /* __IP27_COMMON_H */

185
arch/mips/sgi-ip27/ip27-hubio.c
View File

@ -1,185 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 1992-1997, 2000-2003 Silicon Graphics, Inc.
* Copyright (C) 2004 Christoph Hellwig.
*
* Support functions for the HUB ASIC - mostly PIO mapping related.
*/
#include <linux/bitops.h>
#include <linux/string.h>
#include <linux/mmzone.h>
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include <asm/sn/agent.h>
#include <asm/sn/io.h>
#include <asm/xtalk/xtalk.h>
static int force_fire_and_forget = 1;
/**
* hub_pio_map - establish a HUB PIO mapping
*
* @nasid: nasid to perform PIO mapping on
* @widget: widget ID to perform PIO mapping for
* @xtalk_addr: xtalk_address that needs to be mapped
* @size: size of the PIO mapping
*
**/
unsigned long hub_pio_map(nasid_t nasid, xwidgetnum_t widget,
unsigned long xtalk_addr, size_t size)
{
unsigned i;
/* use small-window mapping if possible */
if ((xtalk_addr % SWIN_SIZE) + size <= SWIN_SIZE)
return NODE_SWIN_BASE(nasid, widget) + (xtalk_addr % SWIN_SIZE);
if ((xtalk_addr % BWIN_SIZE) + size > BWIN_SIZE) {
printk(KERN_WARNING "PIO mapping at hub %d widget %d addr 0x%lx"
" too big (%ld)\n",
nasid, widget, xtalk_addr, size);
return 0;
}
xtalk_addr &= ~(BWIN_SIZE-1);
for (i = 0; i < HUB_NUM_BIG_WINDOW; i++) {
if (test_and_set_bit(i, hub_data(nasid)->h_bigwin_used))
continue;
/*
* The code below does a PIO write to setup an ITTE entry.
*
* We need to prevent other CPUs from seeing our updated
* memory shadow of the ITTE (in the piomap) until the ITTE
* entry is actually set up; otherwise, another CPU might
* attempt a PIO prematurely.
*
* Also, the only way we can know that an entry has been
* received by the hub and can be used by future PIO reads/
* writes is by reading back the ITTE entry after writing it.
*
* For these two reasons, we PIO read back the ITTE entry
* after we write it.
*/
IIO_ITTE_PUT(nasid, i, HUB_PIO_MAP_TO_MEM, widget, xtalk_addr);
__raw_readq(IIO_ITTE_GET(nasid, i));
return NODE_BWIN_BASE(nasid, widget) + (xtalk_addr % BWIN_SIZE);
}
printk(KERN_WARNING "unable to establish PIO mapping for at"
" hub %d widget %d addr 0x%lx\n",
nasid, widget, xtalk_addr);
return 0;
}
/*
* hub_setup_prb(nasid, prbnum, credits, conveyor)
*
* Put a PRB into fire-and-forget mode if conveyor isn't set. Otherwise,
* put it into conveyor belt mode with the specified number of credits.
*/
static void hub_setup_prb(nasid_t nasid, int prbnum, int credits)
{
union iprb_u prb;
int prb_offset;
/*
* Get the current register value.
*/
prb_offset = IIO_IOPRB(prbnum);
prb.iprb_regval = REMOTE_HUB_L(nasid, prb_offset);
/*
* Clear out some fields.
*/
prb.iprb_ovflow = 1;
prb.iprb_bnakctr = 0;
prb.iprb_anakctr = 0;
/*
* Enable or disable fire-and-forget mode.
*/
prb.iprb_ff = force_fire_and_forget ? 1 : 0;
/*
* Set the appropriate number of PIO credits for the widget.
*/
prb.iprb_xtalkctr = credits;
/*
* Store the new value to the register.
*/
REMOTE_HUB_S(nasid, prb_offset, prb.iprb_regval);
}
/**
* hub_set_piomode - set pio mode for a given hub
*
* @nasid: physical node ID for the hub in question
*
* Put the hub into either "PIO conveyor belt" mode or "fire-and-forget" mode.
* To do this, we have to make absolutely sure that no PIOs are in progress
* so we turn off access to all widgets for the duration of the function.
*
* XXX - This code should really check what kind of widget we're talking
* to. Bridges can only handle three requests, but XG will do more.
* How many can crossbow handle to widget 0? We're assuming 1.
*
* XXX - There is a bug in the crossbow that link reset PIOs do not
* return write responses. The easiest solution to this problem is to
* leave widget 0 (xbow) in fire-and-forget mode at all times. This
* only affects pio's to xbow registers, which should be rare.
**/
static void hub_set_piomode(nasid_t nasid)
{
u64 ii_iowa;
union hubii_wcr_u ii_wcr;
unsigned i;
ii_iowa = REMOTE_HUB_L(nasid, IIO_OUTWIDGET_ACCESS);
REMOTE_HUB_S(nasid, IIO_OUTWIDGET_ACCESS, 0);
ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid, IIO_WCR);
if (ii_wcr.iwcr_dir_con) {
/*
* Assume a bridge here.
*/
hub_setup_prb(nasid, 0, 3);
} else {
/*
* Assume a crossbow here.
*/
hub_setup_prb(nasid, 0, 1);
}
/*
* XXX - Here's where we should take the widget type into
* when account assigning credits.
*/
for (i = HUB_WIDGET_ID_MIN; i <= HUB_WIDGET_ID_MAX; i++)
hub_setup_prb(nasid, i, 3);
REMOTE_HUB_S(nasid, IIO_OUTWIDGET_ACCESS, ii_iowa);
}
/*
* hub_pio_init - PIO-related hub initialization
*
* @hub: hubinfo structure for our hub
*/
void hub_pio_init(nasid_t nasid)
{
unsigned i;
/* initialize big window piomaps for this hub */
bitmap_zero(hub_data(nasid)->h_bigwin_used, HUB_NUM_BIG_WINDOW);
for (i = 0; i < HUB_NUM_BIG_WINDOW; i++)
IIO_ITTE_DISABLE(nasid, i);
hub_set_piomode(nasid);
}

2
arch/mips/sgi-ip27/ip27-irq.c
View File

@ -23,6 +23,8 @@
#include <asm/sn/intr.h>
#include <asm/sn/irq_alloc.h>
#include "ip27-common.h"
struct hub_irq_data {
u64 *irq_mask[2];
cpuid_t cpu;

1
arch/mips/sgi-ip27/ip27-memory.c
View File

@ -23,6 +23,7 @@
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/sections.h>
#include <asm/sgialib.h>
#include <asm/sn/arch.h>
#include <asm/sn/agent.h>

25
arch/mips/sgi-ip27/ip27-nmi.c
View File

@ -11,6 +11,8 @@
#include <asm/sn/arch.h>
#include <asm/sn/agent.h>
#include "ip27-common.h"
#if 0
#define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n)
#else
@ -23,16 +25,7 @@
typedef unsigned long machreg_t;
static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;
/*
* Let's see what else we need to do here. Set up sp, gp?
*/
void nmi_dump(void)
{
void cont_nmi_dump(void);
cont_nmi_dump();
}
static void nmi_dump(void);
void install_cpu_nmi_handler(int slice)
{
@ -53,7 +46,7 @@ void install_cpu_nmi_handler(int slice)
* into the eframe format for the node under consideration.
*/
void nmi_cpu_eframe_save(nasid_t nasid, int slice)
static void nmi_cpu_eframe_save(nasid_t nasid, int slice)
{
struct reg_struct *nr;
int i;
@ -129,7 +122,7 @@ void nmi_cpu_eframe_save(nasid_t nasid, int slice)
pr_emerg("\n");
}
void nmi_dump_hub_irq(nasid_t nasid, int slice)
static void nmi_dump_hub_irq(nasid_t nasid, int slice)
{
u64 mask0, mask1, pend0, pend1;
@ -153,7 +146,7 @@ void nmi_dump_hub_irq(nasid_t nasid, int slice)
* Copy the cpu registers which have been saved in the IP27prom format
* into the eframe format for the node under consideration.
*/
void nmi_node_eframe_save(nasid_t nasid)
static void nmi_node_eframe_save(nasid_t nasid)
{
int slice;
@ -170,8 +163,7 @@ void nmi_node_eframe_save(nasid_t nasid)
/*
* Save the nmi cpu registers for all cpus in the system.
*/
void
nmi_eframes_save(void)
static void nmi_eframes_save(void)
{
nasid_t nasid;
@ -179,8 +171,7 @@ nmi_eframes_save(void)
nmi_node_eframe_save(nasid);
}
void
cont_nmi_dump(void)
static void nmi_dump(void)
{
#ifndef REAL_NMI_SIGNAL
static atomic_t nmied_cpus = ATOMIC_INIT(0);

1
arch/mips/sgi-ip30/ip30-console.c
View File

@ -3,6 +3,7 @@
#include <linux/io.h>
#include <asm/sn/ioc3.h>
#include <asm/setup.h>
static inline struct ioc3_uartregs *console_uart(void)
{

1
arch/mips/sgi-ip30/ip30-setup.c
View File

@ -14,6 +14,7 @@
#include <linux/percpu.h>
#include <linux/memblock.h>
#include <asm/bootinfo.h>
#include <asm/smp-ops.h>
#include <asm/sgialib.h>
#include <asm/time.h>

6
arch/mips/sgi-ip32/crime.c
View File

@ -18,6 +18,8 @@
#include <asm/ip32/crime.h>
#include <asm/ip32/mace.h>
#include "ip32-common.h"
struct sgi_crime __iomem *crime;
struct sgi_mace __iomem *mace;
@ -39,7 +41,7 @@ void __init crime_init(void)
id, rev, field, (unsigned long) CRIME_BASE);
}
irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
irqreturn_t crime_memerr_intr(int irq, void *dev_id)
{
unsigned long stat, addr;
int fatal = 0;
@ -90,7 +92,7 @@ irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
return IRQ_HANDLED;
}
irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id)
irqreturn_t crime_cpuerr_intr(int irq, void *dev_id)
{
unsigned long stat = crime->cpu_error_stat & CRIME_CPU_ERROR_MASK;
unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;

2
arch/mips/sgi-ip32/ip32-berr.c
View File

@ -18,6 +18,8 @@
#include <asm/ptrace.h>
#include <asm/tlbdebug.h>
#include "ip32-common.h"
static int ip32_be_handler(struct pt_regs *regs, int is_fixup)
{
int data = regs->cp0_cause & 4;

15
arch/mips/sgi-ip32/ip32-common.h Normal file
View File

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __IP32_COMMON_H
#define __IP32_COMMON_H
#include <linux/init.h>
#include <linux/interrupt.h>
void __init crime_init(void);
irqreturn_t crime_memerr_intr(int irq, void *dev_id);
irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
void __init ip32_be_init(void);
void ip32_prepare_poweroff(void);
#endif /* __IP32_COMMON_H */

6
arch/mips/sgi-ip32/ip32-irq.c
View File

@ -28,6 +28,8 @@
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>
#include "ip32-common.h"
/* issue a PIO read to make sure no PIO writes are pending */
static inline void flush_crime_bus(void)
{
@ -107,10 +109,6 @@ static inline void flush_mace_bus(void)
* is quite different anyway.
*/
/* Some initial interrupts to set up */
extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
/*
* This is for pure CRIME interrupts - ie not MACE. The advantage?
* We get to split the register in half and do faster lookups.

1
arch/mips/sgi-ip32/ip32-memory.c
View File

@ -15,6 +15,7 @@
#include <asm/ip32/crime.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/sgialib.h>
extern void crime_init(void);

2
arch/mips/sgi-ip32/ip32-reset.c
View File

@ -29,6 +29,8 @@
#include <asm/ip32/crime.h>
#include <asm/ip32/ip32_ints.h>
#include "ip32-common.h"
#define POWERDOWN_TIMEOUT 120
/*
* Blink frequency during reboot grace period and when panicked.

3
arch/mips/sgi-ip32/ip32-setup.c
View File

@ -26,8 +26,7 @@
#include <asm/ip32/mace.h>
#include <asm/ip32/ip32_ints.h>
extern void ip32_be_init(void);
extern void crime_init(void);
#include "ip32-common.h"
#ifdef CONFIG_SGI_O2MACE_ETH
/*