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Staging: rtl8192e: Code style fixes for r819xE_phy.h
Signed-off-by: Radu Voicilas <rvoicilas@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Radu Voicilas
Greg Kroah-Hartman
parent
1719e1190a
commit
4db3d5e4e7
@ -1,43 +1,46 @@
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#ifndef _R819XU_PHY_H
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#define _R819XU_PHY_H
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/* Channel switch:The size of command tables for switch channel*/
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/* Channel switch: the size of command tables for switch channel */
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#define MAX_PRECMD_CNT 16
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#define MAX_RFDEPENDCMD_CNT 16
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#define MAX_POSTCMD_CNT 16
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#ifdef RTL8190P
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#define MACPHY_Array_PGLength 21
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#define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG
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#define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array
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#define Rtl819XMACPHY_Array_PG Rtl8190PciMACPHY_Array_PG
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#define Rtl819XMACPHY_Array Rtl8190PciMACPHY_Array
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#define RadioC_ArrayLength 246
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#define RadioD_ArrayLength 78
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#define Rtl819XRadioA_Array Rtl8190PciRadioA_Array
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#define Rtl819XRadioB_Array Rtl8190PciRadioB_Array
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#define Rtl819XRadioC_Array Rtl8190PciRadioC_Array
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#define Rtl819XRadioD_Array Rtl8190PciRadioD_Array
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#define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array
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#define PHY_REGArrayLength 280
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#define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray
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#define PHY_REG_1T2RArrayLength 280
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#define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray
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#define Rtl819XRadioA_Array Rtl8190PciRadioA_Array
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#define Rtl819XRadioB_Array Rtl8190PciRadioB_Array
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#define Rtl819XRadioC_Array Rtl8190PciRadioC_Array
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#define Rtl819XRadioD_Array Rtl8190PciRadioD_Array
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#define Rtl819XAGCTAB_Array Rtl8190PciAGCTAB_Array
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#define PHY_REGArrayLength 280
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#define Rtl819XPHY_REGArray Rtl8190PciPHY_REGArray
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#define PHY_REG_1T2RArrayLength 280
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#define Rtl819XPHY_REG_1T2RArray Rtl8190PciPHY_REG_1T2RArray
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#endif
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#ifdef RTL8192E
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#define MACPHY_Array_PGLength 30
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#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
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#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
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#define RadioC_ArrayLength 1
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#define RadioD_ArrayLength 1
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#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
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#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
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#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
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#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
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#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
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#define PHY_REGArrayLength 1
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#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
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#define PHY_REG_1T2RArrayLength 296
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#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
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#endif
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#ifdef RTL8192E
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#define MACPHY_Array_PGLength 30
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#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
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#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
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#define RadioC_ArrayLength 1
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#define RadioD_ArrayLength 1
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#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
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#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
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#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
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#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
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#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
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#define PHY_REGArrayLength 1
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#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
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#define PHY_REG_1T2RArrayLength 296
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#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
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#endif
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#define AGCTAB_ArrayLength 384
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#define MACPHY_ArrayLength 18
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@ -45,7 +48,7 @@
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#define RadioB_ArrayLength 78
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typedef enum _SwChnlCmdID{
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typedef enum _SwChnlCmdID {
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CmdID_End,
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CmdID_SetTxPowerLevel,
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CmdID_BBRegWrite10,
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@ -53,16 +56,15 @@ typedef enum _SwChnlCmdID{
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CmdID_WritePortUshort,
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CmdID_WritePortUchar,
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CmdID_RF_WriteReg,
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}SwChnlCmdID;
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} SwChnlCmdID;
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/*--------------------------------Define structure--------------------------------*/
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/* 1. Switch channel related */
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typedef struct _SwChnlCmd{
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SwChnlCmdID CmdID;
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u32 Para1;
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u32 Para2;
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u32 msDelay;
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}__attribute__ ((packed)) SwChnlCmd;
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/* switch channel data structure */
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typedef struct _SwChnlCmd {
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SwChnlCmdID CmdID;
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u32 Para1;
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u32 Para2;
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u32 msDelay;
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} __attribute__ ((packed)) SwChnlCmd;
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extern u32 rtl819XMACPHY_Array_PG[];
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extern u32 rtl819XPHY_REG_1T2RArray[];
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@ -72,54 +74,90 @@ extern u32 rtl819XRadioB_Array[];
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extern u32 rtl819XRadioC_Array[];
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extern u32 rtl819XRadioD_Array[];
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typedef enum _HW90_BLOCK{
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typedef enum _HW90_BLOCK {
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HW90_BLOCK_MAC = 0,
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HW90_BLOCK_PHY0 = 1,
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HW90_BLOCK_PHY1 = 2,
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HW90_BLOCK_RF = 3,
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HW90_BLOCK_MAXIMUM = 4, // Never use this
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}HW90_BLOCK_E, *PHW90_BLOCK_E;
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/* Don't ever use this. */
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HW90_BLOCK_MAXIMUM = 4,
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} HW90_BLOCK_E, *PHW90_BLOCK_E;
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typedef enum _RF90_RADIO_PATH{
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RF90_PATH_A = 0, //Radio Path A
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RF90_PATH_B = 1, //Radio Path B
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RF90_PATH_C = 2, //Radio Path C
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RF90_PATH_D = 3, //Radio Path D
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RF90_PATH_MAX //Max RF number 92 support
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}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
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typedef enum _RF90_RADIO_PATH {
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/* Radio paths */
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RF90_PATH_A = 0,
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RF90_PATH_B = 1,
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RF90_PATH_C = 2,
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RF90_PATH_D = 3,
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#define bMaskByte0 0xff
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#define bMaskByte1 0xff00
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#define bMaskByte2 0xff0000
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#define bMaskByte3 0xff000000
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#define bMaskHWord 0xffff0000
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#define bMaskLWord 0x0000ffff
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#define bMaskDWord 0xffffffff
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/* Max RF number 92 support */
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RF90_PATH_MAX
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} RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
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#define bMaskByte0 0xff
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#define bMaskByte1 0xff00
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#define bMaskByte2 0xff0000
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#define bMaskByte3 0xff000000
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#define bMaskHWord 0xffff0000
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#define bMaskLWord 0x0000ffff
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#define bMaskDWord 0xffffffff
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/*extern u32 rtl8192_CalculateBitShift(u32 dwBitMask);
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extern u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
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RF90_RADIO_PATH_E eRFPath, u32 Offset);
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extern void rtl8192_phy_RFSerialWrite(struct net_device *dev,
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RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
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extern void rtl8192_InitBBRFRegDef(struct net_device *dev);
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extern RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device *dev); */
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extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath);
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extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr,
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u32 dwBitMask, u32 dwData);
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extern u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr,
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u32 dwBitMask);
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extern void rtl8192_phy_SetRFReg(struct net_device *dev,
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RF90_RADIO_PATH_E eRFPath, u32 RegAddr,
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u32 BitMask, u32 Data);
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extern u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
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RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
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extern void rtl8192_phy_configmac(struct net_device *dev);
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extern void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType);
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extern RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device *dev,
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HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
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extern RT_STATUS rtl8192_BBConfig(struct net_device *dev);
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extern void rtl8192_phy_getTxPower(struct net_device *dev);
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extern void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel);
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//extern u32 rtl8192_CalculateBitShift(u32 dwBitMask);
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extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath);
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extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData);
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extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask);
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//extern u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
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//extern void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
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extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
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extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
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extern void rtl8192_phy_configmac(struct net_device* dev);
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extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType);
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//extern void rtl8192_InitBBRFRegDef(struct net_device* dev);
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extern RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
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//extern RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev);
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extern RT_STATUS rtl8192_BBConfig(struct net_device* dev);
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extern void rtl8192_phy_getTxPower(struct net_device* dev);
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extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel);
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extern RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev);
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extern void rtl8192_phy_updateInitGain(struct net_device* dev);
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extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath);
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extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel);
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extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
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extern void rtl8192_phy_updateInitGain(struct net_device* dev);
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extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
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RF90_RADIO_PATH_E eRFPath);
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extern u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel);
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extern void rtl8192_SetBWMode(struct net_device *dev,
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HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset);
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extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
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extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
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extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
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#endif
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#endif /* _R819XU_PHY_H */
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