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[MTD] [NAND] sh_flctl: add support for Renesas SuperH FLCTL
Several Renesas SuperH CPU has FLCTL. The FLCTL support NAND Flash. This driver support SH7723. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Yoshihiro Shimoda
David Woodhouse
parent
3fc2389847
commit
6028aa01f7
@ -407,4 +407,11 @@ config MTD_NAND_MXC
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This enables the driver for the NAND flash controller on the
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MXC processors.
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config MTD_NAND_SH_FLCTL
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tristate "Support for NAND on Renesas SuperH FLCTL"
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depends on MTD_NAND && SUPERH && CPU_SUBTYPE_SH7723
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help
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Several Renesas SuperH CPU has FLCTL. This option enables support
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for NAND Flash using FLCTL. This driver support SH7723.
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endif # MTD_NAND
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@ -33,6 +33,7 @@ obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
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obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
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obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
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obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o
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obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o
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obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o
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nand-objs := nand_base.o nand_bbt.o
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301
drivers/mtd/nand/sh_flctl.c
Normal file
301
drivers/mtd/nand/sh_flctl.c
Normal file
@ -0,0 +1,301 @@
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/*
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* SuperH FLCTL nand controller
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*
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* Copyright © 2008 Renesas Solutions Corp.
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* Copyright © 2008 Atom Create Engineering Co., Ltd.
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*
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* Based on fsl_elbc_nand.c, Copyright © 2006-2007 Freescale Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/sh_flctl.h>
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static struct nand_ecclayout flctl_4secc_oob_16 = {
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.eccbytes = 10,
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.eccpos = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9},
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.oobfree = {
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{.offset = 12,
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. length = 4} },
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};
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static struct nand_ecclayout flctl_4secc_oob_64 = {
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.eccbytes = 10,
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.eccpos = {48, 49, 50, 51, 52, 53, 54, 55, 56, 57},
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.oobfree = {
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{.offset = 60,
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. length = 4} },
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};
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static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
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static struct nand_bbt_descr flctl_4secc_smallpage = {
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.options = NAND_BBT_SCAN2NDPAGE,
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.offs = 11,
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.len = 1,
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.pattern = scan_ff_pattern,
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};
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static struct nand_bbt_descr flctl_4secc_largepage = {
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.options = 0,
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.offs = 58,
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.len = 2,
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.pattern = scan_ff_pattern,
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};
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static void empty_fifo(struct sh_flctl *flctl)
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{
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writel(0x000c0000, FLINTDMACR(flctl)); /* FIFO Clear */
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writel(0x00000000, FLINTDMACR(flctl)); /* Clear Error flags */
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}
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static void start_translation(struct sh_flctl *flctl)
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{
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writeb(TRSTRT, FLTRCR(flctl));
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}
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static void wait_completion(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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while (timeout--) {
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if (readb(FLTRCR(flctl)) & TREND) {
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writeb(0x0, FLTRCR(flctl));
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return;
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}
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udelay(1);
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}
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printk(KERN_ERR "wait_completion(): Timeout occured \n");
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writeb(0x0, FLTRCR(flctl));
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}
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static void set_addr(struct mtd_info *mtd, int column, int page_addr)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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uint32_t addr = 0;
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if (column == -1) {
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addr = page_addr; /* ERASE1 */
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} else if (page_addr != -1) {
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/* SEQIN, READ0, etc.. */
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if (flctl->page_size) {
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addr = column & 0x0FFF;
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addr |= (page_addr & 0xff) << 16;
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addr |= ((page_addr >> 8) & 0xff) << 24;
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/* big than 128MB */
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if (flctl->rw_ADRCNT == ADRCNT2_E) {
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uint32_t addr2;
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addr2 = (page_addr >> 16) & 0xff;
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writel(addr2, FLADR2(flctl));
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}
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} else {
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addr = column;
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addr |= (page_addr & 0xff) << 8;
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addr |= ((page_addr >> 8) & 0xff) << 16;
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addr |= ((page_addr >> 16) & 0xff) << 24;
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}
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}
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writel(addr, FLADR(flctl));
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}
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static void wait_rfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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while (timeout--) {
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uint32_t val;
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/* check FIFO */
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val = readl(FLDTCNTR(flctl)) >> 16;
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if (val & 0xFF)
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return;
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udelay(1);
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}
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printk(KERN_ERR "wait_rfifo_ready(): Timeout occured \n");
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}
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static void wait_wfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t len, timeout = LOOP_TIMEOUT_MAX;
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while (timeout--) {
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/* check FIFO */
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len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF;
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if (len >= 4)
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return;
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udelay(1);
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}
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printk(KERN_ERR "wait_wfifo_ready(): Timeout occured \n");
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}
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static int wait_recfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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int checked[4];
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void __iomem *ecc_reg[4];
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int i;
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uint32_t data, size;
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memset(checked, 0, sizeof(checked));
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while (timeout--) {
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size = readl(FLDTCNTR(flctl)) >> 24;
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if (size & 0xFF)
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return 0; /* success */
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if (readl(FL4ECCCR(flctl)) & _4ECCFA)
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return 1; /* can't correct */
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udelay(1);
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if (!(readl(FL4ECCCR(flctl)) & _4ECCEND))
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continue;
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/* start error correction */
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ecc_reg[0] = FL4ECCRESULT0(flctl);
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ecc_reg[1] = FL4ECCRESULT1(flctl);
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ecc_reg[2] = FL4ECCRESULT2(flctl);
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ecc_reg[3] = FL4ECCRESULT3(flctl);
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for (i = 0; i < 3; i++) {
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data = readl(ecc_reg[i]);
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if (data != INIT_FL4ECCRESULT_VAL && !checked[i]) {
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uint8_t org;
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int index;
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index = data >> 16;
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org = flctl->done_buff[index];
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flctl->done_buff[index] = org ^ (data & 0xFF);
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checked[i] = 1;
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}
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}
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writel(0, FL4ECCCR(flctl));
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}
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printk(KERN_ERR "wait_recfifo_ready(): Timeout occured \n");
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return 1; /* timeout */
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}
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static void wait_wecfifo_ready(struct sh_flctl *flctl)
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{
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uint32_t timeout = LOOP_TIMEOUT_MAX;
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uint32_t len;
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while (timeout--) {
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/* check FLECFIFO */
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len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF;
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if (len >= 4)
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return;
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udelay(1);
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}
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printk(KERN_ERR "wait_wecfifo_ready(): Timeout occured \n");
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}
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static void read_datareg(struct sh_flctl *flctl, int offset)
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{
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unsigned long data;
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unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
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wait_completion(flctl);
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data = readl(FLDATAR(flctl));
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*buf = le32_to_cpu(data);
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}
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static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
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{
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int i, len_4align;
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unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
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void *fifo_addr = (void *)FLDTFIFO(flctl);
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len_4align = (rlen + 3) / 4;
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for (i = 0; i < len_4align; i++) {
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wait_rfifo_ready(flctl);
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buf[i] = readl(fifo_addr);
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buf[i] = be32_to_cpu(buf[i]);
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}
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}
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static int read_ecfiforeg(struct sh_flctl *flctl, uint8_t *buff)
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{
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int i;
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unsigned long *ecc_buf = (unsigned long *)buff;
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void *fifo_addr = (void *)FLECFIFO(flctl);
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for (i = 0; i < 4; i++) {
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if (wait_recfifo_ready(flctl))
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return 1;
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ecc_buf[i] = readl(fifo_addr);
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ecc_buf[i] = be32_to_cpu(ecc_buf[i]);
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}
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return 0;
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}
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static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
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{
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int i, len_4align;
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unsigned long *data = (unsigned long *)&flctl->done_buff[offset];
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void *fifo_addr = (void *)FLDTFIFO(flctl);
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len_4align = (rlen + 3) / 4;
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for (i = 0; i < len_4align; i++) {
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wait_wfifo_ready(flctl);
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writel(cpu_to_be32(data[i]), fifo_addr);
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}
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}
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static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val)
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{
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struct sh_flctl *flctl = mtd_to_flctl(mtd);
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uint32_t flcmncr_val = readl(FLCMNCR(flctl));
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uint32_t flcmdcr_val, addr_len_bytes = 0;
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/* Set SNAND bit if page size is 2048byte */
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if (flctl->page_size)
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flcmncr_val |= SNAND_E;
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else
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flcmncr_val &= ~SNAND_E;
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/* default FLCMDCR val */
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flcmdcr_val = DOCMD1_E | DOADR_E;
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/* Set for FLCMDCR */
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switch (cmd) {
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case NAND_CMD_ERASE1:
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addr_len_bytes = flctl->erase_ADRCNT;
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flcmdcr_val |= DOCMD2_E;
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break;
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case NAND_CMD_READ0:
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case NAND_CMD_READOOB:
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addr_len_bytes = flctl->rw_ADRCNT;
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flcmdcr_val |= CDSRC_E;
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break;
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case NAND_CMD_SEQIN:
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/* This case is that cmd is READ0 or READ1 or READ00 */
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flcmdcr_val &= ~DOADR_E; /* ONLY execute 1st cmd */
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break;
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case NAND_CMD_PAGEPROG:
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addr_len_bytes = flctl->rw_ADRCNT;
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125
include/linux/mtd/sh_flctl.h
Normal file
125
include/linux/mtd/sh_flctl.h
Normal file
@ -0,0 +1,125 @@
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/*
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* SuperH FLCTL nand controller
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*
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* Copyright © 2008 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SH_FLCTL_H__
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#define __SH_FLCTL_H__
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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/* FLCTL registers */
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#define FLCMNCR(f) (f->reg + 0x0)
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#define FLCMDCR(f) (f->reg + 0x4)
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#define FLCMCDR(f) (f->reg + 0x8)
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#define FLADR(f) (f->reg + 0xC)
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#define FLADR2(f) (f->reg + 0x3C)
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#define FLDATAR(f) (f->reg + 0x10)
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#define FLDTCNTR(f) (f->reg + 0x14)
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#define FLINTDMACR(f) (f->reg + 0x18)
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#define FLBSYTMR(f) (f->reg + 0x1C)
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#define FLBSYCNT(f) (f->reg + 0x20)
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#define FLDTFIFO(f) (f->reg + 0x24)
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#define FLECFIFO(f) (f->reg + 0x28)
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#define FLTRCR(f) (f->reg + 0x2C)
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#define FL4ECCRESULT0(f) (f->reg + 0x80)
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#define FL4ECCRESULT1(f) (f->reg + 0x84)
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#define FL4ECCRESULT2(f) (f->reg + 0x88)
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#define FL4ECCRESULT3(f) (f->reg + 0x8C)
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#define FL4ECCCR(f) (f->reg + 0x90)
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#define FL4ECCCNT(f) (f->reg + 0x94)
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#define FLERRADR(f) (f->reg + 0x98)
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/* FLCMNCR control bits */
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#define ECCPOS2 (0x1 << 25)
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#define _4ECCCNTEN (0x1 << 24)
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#define _4ECCEN (0x1 << 23)
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#define _4ECCCORRECT (0x1 << 22)
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#define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/
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#define QTSEL_E (0x1 << 17)
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#define ENDIAN (0x1 << 16) /* 1 = little endian */
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#define FCKSEL_E (0x1 << 15)
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#define ECCPOS_00 (0x00 << 12)
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#define ECCPOS_01 (0x01 << 12)
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#define ECCPOS_02 (0x02 << 12)
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#define ACM_SACCES_MODE (0x01 << 10)
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#define NANWF_E (0x1 << 9)
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#define SE_D (0x1 << 8) /* Spare area disable */
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#define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */
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#define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */
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#define TYPESEL_SET (0x1 << 0)
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/* FLCMDCR control bits */
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#define ADRCNT2_E (0x1 << 31) /* 5byte address enable */
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#define ADRMD_E (0x1 << 26) /* Sector address access */
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#define CDSRC_E (0x1 << 25) /* Data buffer selection */
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#define DOSR_E (0x1 << 24) /* Status read check */
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#define SELRW (0x1 << 21) /* 0:read 1:write */
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#define DOADR_E (0x1 << 20) /* Address stage execute */
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#define ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */
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#define ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */
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#define ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */
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#define ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */
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#define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */
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#define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */
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/* FLTRCR control bits */
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#define TRSTRT (0x1 << 0) /* translation start */
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#define TREND (0x1 << 1) /* translation end */
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/* FL4ECCCR control bits */
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#define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */
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#define _4ECCEND (0x1 << 1) /* 4 symbols end */
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#define _4ECCEXST (0x1 << 0) /* 4 symbols exist */
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#define INIT_FL4ECCRESULT_VAL 0x03FF03FF
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#define LOOP_TIMEOUT_MAX 0x00010000
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#define mtd_to_flctl(mtd) container_of(mtd, struct sh_flctl, mtd)
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struct sh_flctl {
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struct mtd_info mtd;
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struct nand_chip chip;
|
||||
void __iomem *reg;
|
||||
|
||||
uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */
|
||||
int read_bytes;
|
||||
int index;
|
||||
int seqin_column; /* column in SEQIN cmd */
|
||||
int seqin_page_addr; /* page_addr in SEQIN cmd */
|
||||
uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */
|
||||
int erase1_page_addr; /* page_addr in ERASE1 cmd */
|
||||
uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */
|
||||
uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */
|
||||
|
||||
int hwecc_cant_correct[4];
|
||||
|
||||
unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */
|
||||
unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */
|
||||
};
|
||||
|
||||
struct sh_flctl_platform_data {
|
||||
struct mtd_partition *parts;
|
||||
int nr_parts;
|
||||
unsigned long flcmncr_val;
|
||||
|
||||
unsigned has_hwecc:1;
|
||||
};
|
||||
|
||||
#endif /* __SH_FLCTL_H__ */
|
||||
Loading…
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Reference in New Issue
Block a user