dt-bindings: power: Add r8a77961 SYSC power domain definitions

Add power domain indices for the R-Car M3-W+ (R8A77961) SoC.

Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s
Manual (Jul. 31, 2019).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Link: https://lore.kernel.org/r/20191023122911.12166-6-geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2019-10-23 14:29:11 +02:00
parent 54ecb8f702
commit 640f9606dc

View File

@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2019 Glider bvba
*/
#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A77961_PD_CA57_CPU0 0
#define R8A77961_PD_CA57_CPU1 1
#define R8A77961_PD_CA53_CPU0 5
#define R8A77961_PD_CA53_CPU1 6
#define R8A77961_PD_CA53_CPU2 7
#define R8A77961_PD_CA53_CPU3 8
#define R8A77961_PD_CA57_SCU 12
#define R8A77961_PD_CR7 13
#define R8A77961_PD_A3VC 14
#define R8A77961_PD_3DG_A 17
#define R8A77961_PD_3DG_B 18
#define R8A77961_PD_CA53_SCU 21
#define R8A77961_PD_A3IR 24
#define R8A77961_PD_A2VC1 26
/* Always-on power area */
#define R8A77961_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */