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ARM: dts: qcom: sdx55: Add PCIe bridge node

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On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-20-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Manivannan Sadhasivam 2024-03-21 16:46:40 +05:30 committed by Bjorn Andersson
parent 27cb9eccf9
commit 669841a2ef
1 changed files with 10 additions and 0 deletions
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10
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
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@ -378,6 +378,16 @@
phy-names = "pciephy";
status = "disabled";
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie_ep: pcie-ep@1c00000 {