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dt-bindings: clock: add QCOM SM6350 display clock bindings
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-1-konrad.dybcio@somainline.org
This commit is contained in:
Konrad Dybcio
Bjorn Andersson
parent
809b482896
commit
6914b82f37
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SM6350
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maintainers:
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- Konrad Dybcio <konrad.dybcio@somainline.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SM6350.
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See also dt-bindings/clock/qcom,dispcc-sm6350.h.
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properties:
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compatible:
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const: qcom,sm6350-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: Byte clock from DSI PHY
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- description: Pixel clock from DSI PHY
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: gcc_disp_gpll0_clk
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm6350.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@af00000 {
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compatible = "qcom,sm6350-dispcc";
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reg = <0x0af00000 0x20000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK>,
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<&dsi_phy 0>,
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<&dsi_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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48
include/dt-bindings/clock/qcom,dispcc-sm6350.h
Normal file
48
include/dt-bindings/clock/qcom,dispcc-sm6350.h
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@ -0,0 +1,48 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
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/* DISP_CC clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define DISP_CC_MDSS_DP_AUX_CLK 7
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#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8
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#define DISP_CC_MDSS_DP_CRYPTO_CLK 9
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#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10
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#define DISP_CC_MDSS_DP_LINK_CLK 11
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#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12
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#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13
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#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14
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#define DISP_CC_MDSS_DP_PIXEL_CLK 15
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#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16
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#define DISP_CC_MDSS_ESC0_CLK 17
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#define DISP_CC_MDSS_ESC0_CLK_SRC 18
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#define DISP_CC_MDSS_MDP_CLK 19
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#define DISP_CC_MDSS_MDP_CLK_SRC 20
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#define DISP_CC_MDSS_MDP_LUT_CLK 21
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 22
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#define DISP_CC_MDSS_PCLK0_CLK 23
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 24
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#define DISP_CC_MDSS_ROT_CLK 25
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#define DISP_CC_MDSS_ROT_CLK_SRC 26
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#define DISP_CC_MDSS_RSCC_AHB_CLK 27
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 28
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#define DISP_CC_MDSS_VSYNC_CLK 29
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 30
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#define DISP_CC_SLEEP_CLK 31
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#define DISP_CC_XO_CLK 32
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/* GDSCs */
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#define MDSS_GDSC 0
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#endif
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