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powerpc updates for 6.4

Browse Source 
- Add support for building the kernel using PC-relative addressing on Power10.
 
  - Allow HV KVM guests on Power10 to use prefixed instructions.
 
  - Unify support for the P2020 CPU (85xx) into a single machine description.
 
  - Always build the 64-bit kernel with 128-bit long double.
 
  - Drop support for several obsolete 2000's era development boards as
    identified by Paul Gortmaker.
 
  - A series fixing VFIO on Power since some generic changes.
 
  - Various other small features and fixes.
 
 Thanks to: Alexey Kardashevskiy, Andrew Donnellan, Benjamin Gray, Bo Liu,
 Christophe Leroy, Dan Carpenter, David Binderman, Ira Weiny, Joel Stanley,
 Kajol Jain, Kautuk Consul, Liang He, Luis Chamberlain, Masahiro Yamada, Michael
 Neuling, Nathan Chancellor, Nathan Lynch, Nicholas Miehlbradt, Nicholas Piggin,
 Nick Desaulniers, Nysal Jan K.A, Pali Rohár, Paul Gortmaker, Paul Mackerras,
 Petr Vaněk, Randy Dunlap, Rob Herring, Sachin Sant, Sean Christopherson, Segher
 Boessenkool, Timothy Pearson.
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Merge tag 'powerpc-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux

Pull powerpc updates from Michael Ellerman:

 - Add support for building the kernel using PC-relative addressing on
   Power10.

 - Allow HV KVM guests on Power10 to use prefixed instructions.

 - Unify support for the P2020 CPU (85xx) into a single machine
   description.

 - Always build the 64-bit kernel with 128-bit long double.

 - Drop support for several obsolete 2000's era development boards as
   identified by Paul Gortmaker.

 - A series fixing VFIO on Power since some generic changes.

 - Various other small features and fixes.

Thanks to Alexey Kardashevskiy, Andrew Donnellan, Benjamin Gray, Bo Liu,
Christophe Leroy, Dan Carpenter, David Binderman, Ira Weiny, Joel
Stanley, Kajol Jain, Kautuk Consul, Liang He, Luis Chamberlain, Masahiro
Yamada, Michael Neuling, Nathan Chancellor, Nathan Lynch, Nicholas
Miehlbradt, Nicholas Piggin, Nick Desaulniers, Nysal Jan K.A, Pali
Rohár, Paul Gortmaker, Paul Mackerras, Petr Vaněk, Randy Dunlap, Rob
Herring, Sachin Sant, Sean Christopherson, Segher Boessenkool, and
Timothy Pearson.

* tag 'powerpc-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (156 commits)
  powerpc/64s: Disable pcrel code model on Clang
  powerpc: Fix merge conflict between pcrel and copy_thread changes
  powerpc/configs/powernv: Add IGB=y
  powerpc/configs/64s: Drop JFS Filesystem
  powerpc/configs/64s: Use EXT4 to mount EXT2 filesystems
  powerpc/configs: Make pseries_defconfig an alias for ppc64le_guest
  powerpc/configs: Make pseries_le an alias for ppc64le_guest
  powerpc/configs: Incorporate generic kvm_guest.config into guest configs
  powerpc/configs: Add IBMVETH=y and IBMVNIC=y to guest configs
  powerpc/configs/64s: Enable Device Mapper options
  powerpc/configs/64s: Enable PSTORE
  powerpc/configs/64s: Enable VLAN support
  powerpc/configs/64s: Enable BLK_DEV_NVME
  powerpc/configs/64s: Drop REISERFS
  powerpc/configs/64s: Use SHA512 for module signatures
  powerpc/configs/64s: Enable IO_STRICT_DEVMEM
  powerpc/configs/64s: Enable SCHEDSTATS
  powerpc/configs/64s: Enable DEBUG_VM & other options
  powerpc/configs/64s: Enable EMULATED_STATS
  powerpc/configs/64s: Enable KUNIT and most tests
  ...
This commit is contained in:
Linus Torvalds 2023-04-28 16:24:32 -07:00
commit 70cc1b5307
279 changed files with 2690 additions and 9528 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
MAINTAINERS
View File

@ -9900,6 +9900,11 @@ F: drivers/crypto/vmx/ghash*
F: drivers/crypto/vmx/ppc-xlate.pl
F: drivers/crypto/vmx/vmx.c
IBM Power VFIO Support
M: Timothy Pearson <tpearson@raptorengineering.com>
S: Supported
F: drivers/vfio/vfio_iommu_spapr_tce.c
IBM ServeRAID RAID DRIVER
S: Orphan
F: drivers/scsi/ips.*

20
arch/powerpc/Kconfig
View File

@ -4,6 +4,17 @@ source "arch/powerpc/platforms/Kconfig.cputype"
config CC_HAS_ELFV2
def_bool PPC64 && $(cc-option, -mabi=elfv2)
config CC_HAS_PREFIXED
def_bool PPC64 && $(cc-option, -mcpu=power10 -mprefixed)
config CC_HAS_PCREL
# Clang has a bug (https://github.com/llvm/llvm-project/issues/62372)
# where pcrel code is not generated if -msoft-float, -mno-altivec, or
# -mno-vsx options are also given. Without these options, fp/vec
# instructions are generated from regular kernel code. So Clang can't
# do pcrel yet.
def_bool PPC64 && CC_IS_GCC && $(cc-option, -mcpu=power10 -mpcrel)
config 32BIT
bool
default y if PPC32
@ -158,6 +169,7 @@ config PPC
select ARCH_USE_CMPXCHG_LOCKREF if PPC64
select ARCH_USE_MEMTEST
select ARCH_USE_QUEUED_RWLOCKS if PPC_QUEUED_SPINLOCKS
select ARCH_WANT_DEFAULT_BPF_JIT
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
select ARCH_WANT_IPC_PARSE_VERSION
select ARCH_WANT_IRQS_OFF_ACTIVATE_MM
@ -201,6 +213,7 @@ config PPC
select HAVE_ARCH_KCSAN if PPC_BOOK3S_64
select HAVE_ARCH_KFENCE if ARCH_SUPPORTS_DEBUG_PAGEALLOC
select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
select HAVE_ARCH_WITHIN_STACK_FRAMES
select HAVE_ARCH_KGDB
select HAVE_ARCH_MMAP_RND_BITS
select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
@ -292,10 +305,6 @@ config PPC
# Please keep this list sorted alphabetically.
#
config PPC_LONG_DOUBLE_128
depends on PPC64 && ALTIVEC
def_bool $(success,test "$(shell,echo __LONG_DOUBLE_128__ | $(CC) -E -P -)" = 1)
config PPC_BARRIER_NOSPEC
bool
default y
@ -618,8 +627,7 @@ config PPC64_BIG_ENDIAN_ELF_ABI_V2
bool "Build big-endian kernel using ELF ABI V2 (EXPERIMENTAL)"
depends on PPC64 && CPU_BIG_ENDIAN
depends on CC_HAS_ELFV2
depends on LD_IS_BFD && LD_VERSION >= 22400
default n
depends on LD_VERSION >= 22400 || LLD_VERSION >= 150000
help
This builds the kernel image using the "Power Architecture 64-Bit ELF
V2 ABI Specification", which has a reduced stack overhead and faster

105
arch/powerpc/Makefile
View File

@ -107,6 +107,7 @@ LDFLAGS_vmlinux-$(CONFIG_RELOCATABLE) += -z notext
LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-y)
ifdef CONFIG_PPC64
ifndef CONFIG_PPC_KERNEL_PCREL
ifeq ($(call cc-option-yn,-mcmodel=medium),y)
# -mcmodel=medium breaks modules because it uses 32bit offsets from
# the TOC pointer to create pointers where possible. Pointers into the
@ -121,20 +122,20 @@ else
export NO_MINIMAL_TOC := -mno-minimal-toc
endif
endif
endif
CFLAGS-$(CONFIG_PPC64) := $(call cc-option,-mtraceback=no)
ifndef CONFIG_CC_IS_CLANG
ifdef CONFIG_PPC64_ELF_ABI_V2
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2,$(call cc-option,-mcall-aixdesc))
AFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2)
else
ifndef CONFIG_CC_IS_CLANG
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv1)
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcall-aixdesc)
AFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv1)
endif
endif
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,$(call cc-option,-mminimal-toc))
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mno-pointers-to-nested-functions)
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mlong-double-128)
# Clang unconditionally reserves r2 on ppc32 and does not support the flag
# https://bugs.llvm.org/show_bug.cgi?id=39555
@ -181,8 +182,16 @@ ifdef CONFIG_476FPE_ERR46
endif
# No prefix or pcrel
ifdef CONFIG_PPC_KERNEL_PREFIXED
KBUILD_CFLAGS += $(call cc-option,-mprefixed)
else
KBUILD_CFLAGS += $(call cc-option,-mno-prefixed)
endif
ifdef CONFIG_PPC_KERNEL_PCREL
KBUILD_CFLAGS += $(call cc-option,-mpcrel)
else
KBUILD_CFLAGS += $(call cc-option,-mno-pcrel)
endif
# No AltiVec or VSX or MMA instructions when building kernel
KBUILD_CFLAGS += $(call cc-option,-mno-altivec)
@ -238,110 +247,118 @@ bootwrapper_install:
$(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
include $(srctree)/scripts/Makefile.defconf
PHONY += pseries_le_defconfig
pseries_le_defconfig:
$(call merge_into_defconfig,pseries_defconfig,le)
PHONY += ppc64le_defconfig
generated_configs += ppc64le_defconfig
ppc64le_defconfig:
$(call merge_into_defconfig,ppc64_defconfig,le)
PHONY += ppc64le_guest_defconfig
generated_configs += ppc64le_guest_defconfig
ppc64le_guest_defconfig:
$(call merge_into_defconfig,ppc64_defconfig,le guest)
$(call merge_into_defconfig,ppc64_defconfig,le guest kvm_guest)
PHONY += ppc64_guest_defconfig
generated_configs += ppc64_guest_defconfig
ppc64_guest_defconfig:
$(call merge_into_defconfig,ppc64_defconfig,be guest)
$(call merge_into_defconfig,ppc64_defconfig,be guest kvm_guest)
PHONY += powernv_be_defconfig
generated_configs += pseries_le_defconfig
pseries_le_defconfig: ppc64le_guest_defconfig
generated_configs += pseries_defconfig
pseries_defconfig: ppc64le_guest_defconfig
generated_configs += powernv_be_defconfig
powernv_be_defconfig:
$(call merge_into_defconfig,powernv_defconfig,be)
PHONY += mpc85xx_defconfig
generated_configs += mpc85xx_defconfig
mpc85xx_defconfig:
$(call merge_into_defconfig,mpc85xx_base.config,\
85xx-32bit 85xx-hw fsl-emb-nonhw)
PHONY += mpc85xx_smp_defconfig
generated_configs += mpc85xx_smp_defconfig
mpc85xx_smp_defconfig:
$(call merge_into_defconfig,mpc85xx_base.config,\
85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw)
PHONY += corenet32_smp_defconfig
generated_configs += corenet32_smp_defconfig
corenet32_smp_defconfig:
$(call merge_into_defconfig,corenet_base.config,\
85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw dpaa)
PHONY += corenet64_smp_defconfig
generated_configs += corenet64_smp_defconfig
corenet64_smp_defconfig:
$(call merge_into_defconfig,corenet_base.config,\
85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw dpaa)
PHONY += mpc86xx_defconfig
generated_configs += mpc86xx_defconfig
mpc86xx_defconfig:
$(call merge_into_defconfig,mpc86xx_base.config,\
86xx-hw fsl-emb-nonhw)
PHONY += mpc86xx_smp_defconfig
generated_configs += mpc86xx_smp_defconfig
mpc86xx_smp_defconfig:
$(call merge_into_defconfig,mpc86xx_base.config,\
86xx-smp 86xx-hw fsl-emb-nonhw)
PHONY += ppc32_allmodconfig
generated_configs += ppc32_allmodconfig
ppc32_allmodconfig:
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/book3s_32.config \
-f $(srctree)/Makefile allmodconfig
PHONY += ppc_defconfig
generated_configs += ppc_defconfig
ppc_defconfig:
$(call merge_into_defconfig,book3s_32.config,)
PHONY += ppc64le_allmodconfig
generated_configs += ppc64le_allmodconfig
ppc64le_allmodconfig:
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/le.config \
-f $(srctree)/Makefile allmodconfig
PHONY += ppc64le_allnoconfig
generated_configs += ppc64le_allnoconfig
ppc64le_allnoconfig:
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/ppc64le.config \
-f $(srctree)/Makefile allnoconfig
PHONY += ppc64_book3e_allmodconfig
generated_configs += ppc64_book3e_allmodconfig
ppc64_book3e_allmodconfig:
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/85xx-64bit.config \
-f $(srctree)/Makefile allmodconfig
PHONY += ppc32_randconfig
generated_configs += ppc32_randconfig
ppc32_randconfig:
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/32-bit.config \
-f $(srctree)/Makefile randconfig
PHONY += ppc64_randconfig
generated_configs += ppc64_randconfig
ppc64_randconfig:
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/64-bit.config \
-f $(srctree)/Makefile randconfig
PHONY += $(generated_configs)
define archhelp
@echo '* zImage - Build default images selected by kernel config'
@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
@echo ' uImage - U-Boot native image format'
@echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
@echo ' versions which do not support device trees'
@echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
@echo ' simpleImage.<dt> - Firmware independent image.'
@echo ' treeImage.<dt> - Support for older IBM 4xx firmware (not U-Boot)'
@echo ' install - Install kernel using'
@echo ' (your) ~/bin/$(INSTALLKERNEL) or'
@echo ' (distribution) /sbin/$(INSTALLKERNEL) or'
@echo ' install to $$(INSTALL_PATH) and run lilo'
@echo ' *_defconfig - Select default config from arch/$(ARCH)/configs'
@echo ''
@echo ' Targets with <dt> embed a device tree blob inside the image'
@echo ' These targets support board with firmware that does not'
@echo ' support passing a device tree directly. Replace <dt> with the'
@echo ' name of a dts file from the arch/$(ARCH)/boot/dts/ directory'
@echo ' (minus the .dts extension).'
echo '* zImage - Build default images selected by kernel config'
echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
echo ' uImage - U-Boot native image format'
echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
echo ' versions which do not support device trees'
echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
echo ' simpleImage.<dt> - Firmware independent image.'
echo ' treeImage.<dt> - Support for older IBM 4xx firmware (not U-Boot)'
echo ' install - Install kernel using'
echo ' (your) ~/bin/$(INSTALLKERNEL) or'
echo ' (distribution) /sbin/$(INSTALLKERNEL) or'
echo ' install to $$(INSTALL_PATH) and run lilo'
echo ' *_defconfig - Select default config from arch/$(ARCH)/configs'
echo ''
echo ' Targets with <dt> embed a device tree blob inside the image'
echo ' These targets support board with firmware that does not'
echo ' support passing a device tree directly. Replace <dt> with the'
echo ' name of a dts file from the arch/$(ARCH)/boot/dts/ directory'
echo ' (minus the .dts extension).'
echo
$(foreach cfg,$(generated_configs),
printf " %-27s - Build for %s\\n" $(cfg) $(subst _defconfig,,$(cfg));)
endef
PHONY += install

16
arch/powerpc/boot/Makefile
View File

@ -34,12 +34,17 @@ endif
BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-fno-strict-aliasing -O2 -msoft-float -mno-altivec -mno-vsx \
$(call cc-option,-mno-prefixed) $(call cc-option,-mno-pcrel) \
$(call cc-option,-mno-mma) \
$(call cc-option,-mno-spe) $(call cc-option,-mspe=no) \
-pipe -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
$(LINUXINCLUDE)
ifdef CONFIG_PPC64_BOOT_WRAPPER
BOOTCFLAGS += -m64
ifdef CONFIG_PPC64_ELF_ABI_V2
BOOTCFLAGS += $(call cc-option,-mabi=elfv2)
endif
else
BOOTCFLAGS += -m32
endif
@ -61,9 +66,6 @@ BOOTCFLAGS += -mbig-endian
else
BOOTCFLAGS += -mlittle-endian
endif
ifdef CONFIG_PPC64_ELF_ABI_V2
BOOTCFLAGS += $(call cc-option,-mabi=elfv2)
endif
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -nostdinc
@ -164,7 +166,7 @@ src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c \
gamecube-head.S gamecube.c \
wii-head.S wii.c holly.c \
fixed-head.S mvme5100.c
@ -327,17 +329,12 @@ image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b
image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200
# Board ports in arch/powerpc/platform/82xx/Kconfig
image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
image-$(CONFIG_PQ2FADS) += cuImage.pq2fads
image-$(CONFIG_EP8248E) += dtbImage.ep8248e
# Board ports in arch/powerpc/platform/83xx/Kconfig
image-$(CONFIG_MPC832x_MDS) += cuImage.mpc832x_mds
image-$(CONFIG_MPC832x_RDB) += cuImage.mpc832x_rdb
image-$(CONFIG_MPC834x_ITX) += cuImage.mpc8349emitx \
cuImage.mpc8349emitxgp
image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
# Board ports in arch/powerpc/platform/85xx/Kconfig
@ -361,7 +358,6 @@ image-$(CONFIG_MVME7100) += dtbImage.mvme7100
# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
image-$(CONFIG_STORCENTER) += cuImage.storcenter
image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
image-$(CONFIG_GAMECUBE) += dtbImage.gamecube
image-$(CONFIG_WII) += dtbImage.wii
image-$(CONFIG_MVME5100) += dtbImage.mvme5100

4
arch/powerpc/boot/crt0.S
View File

@ -51,7 +51,7 @@ _zimage_start:
_zimage_start_lib:
/* Work out the offset between the address we were linked at
and the address where we're running. */
bl .+4
bcl 20,31,.+4
p_base: mflr r10 /* r10 now points to runtime addr of p_base */
#ifndef __powerpc64__
/* grab the link address of the dynamic section in r11 */
@ -274,7 +274,7 @@ prom:
mtsrr1 r10
/* Load FW address, set LR to label 1, and jump to FW */
bl 0f
bcl 20,31,0f
0: mflr r10
addi r11,r10,(1f-0b)
mtlr r11

43
arch/powerpc/boot/cuboot-mpc7448hpc2.c
View File

@ -1,43 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
*
* Author: Roy Zang <tie-fei.zang@freescale.com>
*
* Description:
* Old U-boot compatibility for mpc7448hpc2 board
* Based on the code of Scott Wood <scottwood@freescale.com>
* for 83xx and 85xx.
*/
#include "ops.h"
#include "stdio.h"
#include "cuboot.h"
#define TARGET_HAS_ETH1
#include "ppcboot.h"
static bd_t bd;
extern char _dtb_start[], _dtb_end[];
static void platform_fixups(void)
{
void *tsi;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
tsi = find_node_by_devtype(NULL, "tsi-bridge");
if (tsi)
setprop(tsi, "bus-frequency", &bd.bi_busfreq,
sizeof(bd.bi_busfreq));
}
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
fdt_init(_dtb_start);
serial_console_init();
platform_ops.fixups = platform_fixups;
}

394
arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
View File

@ -1,394 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8641 HPCN Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
*/
/include/ "mpc8641si-pre.dtsi"
/ {
model = "MPC8641HPCN";
compatible = "fsl,mpc8641hpcn";
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; // 1G at 0x0
};
lbc: localbus@ffe05000 {
reg = <0xffe05000 0x1000>;
ranges = <0 0 0xef800000 0x00800000
2 0 0xffdf8000 0x00008000
3 0 0xffdf0000 0x00008000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x00800000>;
bank-width = <2>;
device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x00300000>;
};
partition@300000 {
label = "firmware b";
reg = <0x00300000 0x00100000>;
read-only;
};
partition@400000 {
label = "fs";
reg = <0x00400000 0x00300000>;
};
partition@700000 {
label = "firmware a";
reg = <0x00700000 0x00100000>;
read-only;
};
};
};
soc: soc8641@ffe00000 {
ranges = <0x00000000 0xffe00000 0x00100000>;
enet0: ethernet@24000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
mdio@24520 {
phy0: ethernet-phy@0 {
interrupts = <10 1 0 0>;
reg = <0>;
};
phy1: ethernet-phy@1 {
interrupts = <10 1 0 0>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupts = <10 1 0 0>;
reg = <2>;
};
phy3: ethernet-phy@3 {
interrupts = <10 1 0 0>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet1: ethernet@25000 {
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
mdio@25520 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet2: ethernet@26000 {
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
};
mdio@26520 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet3: ethernet@27000 {
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
phy-connection-type = "rgmii-id";
};
mdio@27520 {
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
rmu: rmu@d3000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,srio-rmu";
reg = <0xd3000 0x500>;
ranges = <0x0 0xd3000 0x500>;
message-unit@0 {
compatible = "fsl,srio-msg-unit";
reg = <0x0 0x100>;
interrupts = <
53 2 0 0 /* msg1_tx_irq */
54 2 0 0>;/* msg1_rx_irq */
};
message-unit@100 {
compatible = "fsl,srio-msg-unit";
reg = <0x100 0x100>;
interrupts = <
55 2 0 0 /* msg2_tx_irq */
56 2 0 0>;/* msg2_rx_irq */
};
doorbell-unit@400 {
compatible = "fsl,srio-dbell-unit";
reg = <0x400 0x80>;
interrupts = <
49 2 0 0 /* bell_outb_irq */
50 2 0 0>;/* bell_inb_irq */
};
port-write-unit@4e0 {
compatible = "fsl,srio-port-write-unit";
reg = <0x4e0 0x20>;
interrupts = <48 2 0 0>;
};
};
};
pci0: pcie@ffe08000 {
reg = <0xffe08000 0x1000>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
interrupt-map-mask = <0xff00 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */
0x8800 0 0 1 &mpic 2 1 0 0
0x8800 0 0 2 &mpic 3 1 0 0
0x8800 0 0 3 &mpic 4 1 0 0
0x8800 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 1 - PCI slot 1 */
0x8900 0 0 1 &mpic 2 1 0 0
0x8900 0 0 2 &mpic 3 1 0 0
0x8900 0 0 3 &mpic 4 1 0 0
0x8900 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 2 - PCI slot 1 */
0x8a00 0 0 1 &mpic 2 1 0 0
0x8a00 0 0 2 &mpic 3 1 0 0
0x8a00 0 0 3 &mpic 4 1 0 0
0x8a00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 3 - PCI slot 1 */
0x8b00 0 0 1 &mpic 2 1 0 0
0x8b00 0 0 2 &mpic 3 1 0 0
0x8b00 0 0 3 &mpic 4 1 0 0
0x8b00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 4 - PCI slot 1 */
0x8c00 0 0 1 &mpic 2 1 0 0
0x8c00 0 0 2 &mpic 3 1 0 0
0x8c00 0 0 3 &mpic 4 1 0 0
0x8c00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 5 - PCI slot 1 */
0x8d00 0 0 1 &mpic 2 1 0 0
0x8d00 0 0 2 &mpic 3 1 0 0
0x8d00 0 0 3 &mpic 4 1 0 0
0x8d00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 6 - PCI slot 1 */
0x8e00 0 0 1 &mpic 2 1 0 0
0x8e00 0 0 2 &mpic 3 1 0 0
0x8e00 0 0 3 &mpic 4 1 0 0
0x8e00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 7 - PCI slot 1 */
0x8f00 0 0 1 &mpic 2 1 0 0
0x8f00 0 0 2 &mpic 3 1 0 0
0x8f00 0 0 3 &mpic 4 1 0 0
0x8f00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x12 func 0 - PCI slot 2 */
0x9000 0 0 1 &mpic 3 1 0 0
0x9000 0 0 2 &mpic 4 1 0 0
0x9000 0 0 3 &mpic 1 1 0 0
0x9000 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 1 - PCI slot 2 */
0x9100 0 0 1 &mpic 3 1 0 0
0x9100 0 0 2 &mpic 4 1 0 0
0x9100 0 0 3 &mpic 1 1 0 0
0x9100 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 2 - PCI slot 2 */
0x9200 0 0 1 &mpic 3 1 0 0
0x9200 0 0 2 &mpic 4 1 0 0
0x9200 0 0 3 &mpic 1 1 0 0
0x9200 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 3 - PCI slot 2 */
0x9300 0 0 1 &mpic 3 1 0 0
0x9300 0 0 2 &mpic 4 1 0 0
0x9300 0 0 3 &mpic 1 1 0 0
0x9300 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 4 - PCI slot 2 */
0x9400 0 0 1 &mpic 3 1 0 0
0x9400 0 0 2 &mpic 4 1 0 0
0x9400 0 0 3 &mpic 1 1 0 0
0x9400 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 5 - PCI slot 2 */
0x9500 0 0 1 &mpic 3 1 0 0
0x9500 0 0 2 &mpic 4 1 0 0
0x9500 0 0 3 &mpic 1 1 0 0
0x9500 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 6 - PCI slot 2 */
0x9600 0 0 1 &mpic 3 1 0 0
0x9600 0 0 2 &mpic 4 1 0 0
0x9600 0 0 3 &mpic 1 1 0 0
0x9600 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 7 - PCI slot 2 */
0x9700 0 0 1 &mpic 3 1 0 0
0x9700 0 0 2 &mpic 4 1 0 0
0x9700 0 0 3 &mpic 1 1 0 0
0x9700 0 0 4 &mpic 2 1 0 0
// IDSEL 0x1c USB
0xe000 0 0 1 &i8259 12 2
0xe100 0 0 2 &i8259 9 2
0xe200 0 0 3 &i8259 10 2
0xe300 0 0 4 &i8259 11 2
// IDSEL 0x1d Audio
0xe800 0 0 1 &i8259 6 2
// IDSEL 0x1e Legacy
0xf000 0 0 1 &i8259 7 2
0xf100 0 0 1 &i8259 7 2
// IDSEL 0x1f IDE/SATA
0xf800 0 0 1 &i8259 14 2
0xf900 0 0 1 &i8259 5 2
>;
pcie@0 {
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x20000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00010000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x02000000 0x0 0x80000000
0x02000000 0x0 0x80000000
0x0 0x20000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00010000>;
isa@1e {
device_type = "isa";
#size-cells = <1>;
#address-cells = <2>;
reg = <0xf000 0 0 0 0>;
ranges = <1 0 0x01000000 0 0
0x00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <1 0x20 2
1 0xa0 2
1 0x4d0 2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <9 2 0 0>;
};
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 0x60 1 1 0x64 1>;
interrupts = <1 3 12 3>;
interrupt-parent = <&i8259>;
keyboard@0 {
reg = <0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible =
"pnpPNP,b00";
reg = <1 0x70 2>;
};
gpio@400 {
reg = <1 0x400 0x80>;
};
};
};
};
};
pci1: pcie@ffe09000 {
reg = <0xffe09000 0x1000>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0x0 0xa0000000
0x02000000 0x0 0xa0000000
0x0 0x20000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00010000>;
};
};
/*
* Only one of Rapid IO or PCI can be present due to HW limitations and
* due to the fact that the 2 now share address space in the new memory
* map. The most likely case is that we have PCI, so comment out the
* rapidio node. Leave it here for reference.
rapidio@ffec0000 {
reg = <0xffec0000 0x11000>;
compatible = "fsl,srio";
interrupts = <48 2 0 0>;
#address-cells = <2>;
#size-cells = <2>;
fsl,srio-rmu-handle = <&rmu>;
ranges;
port1 {
#address-cells = <2>;
#size-cells = <2>;
cell-index = <1>;
ranges = <0 0 0x80000000 0 0x20000000>;
};
};
*/
};
/include/ "mpc8641si-post.dtsi"

337
arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts
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@ -1,337 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8641 HPCN Device Tree Source
*
* Copyright 2008-2009 Freescale Semiconductor Inc.
*/
/include/ "mpc8641si-pre.dtsi"
/ {
model = "MPC8641HPCN";
compatible = "fsl,mpc8641hpcn";
#address-cells = <2>;
#size-cells = <2>;
memory {
device_type = "memory";
reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
};
lbc: localbus@fffe05000 {
reg = <0x0f 0xffe05000 0x0 0x1000>;
ranges = <0 0 0xf 0xef800000 0x00800000
2 0 0xf 0xffdf8000 0x00008000
3 0 0xf 0xffdf0000 0x00008000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x00800000>;
bank-width = <2>;
device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x00000000 0x00300000>;
};
partition@300000 {
label = "firmware b";
reg = <0x00300000 0x00100000>;
read-only;
};
partition@400000 {
label = "fs";
reg = <0x00400000 0x00300000>;
};
partition@700000 {
label = "firmware a";
reg = <0x00700000 0x00100000>;
read-only;
};
};
};
soc: soc8641@fffe00000 {
ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
enet0: ethernet@24000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
mdio@24520 {
phy0: ethernet-phy@0 {
interrupts = <10 1 0 0>;
reg = <0>;
};
phy1: ethernet-phy@1 {
interrupts = <10 1 0 0>;
reg = <1>;
};
phy2: ethernet-phy@2 {
interrupts = <10 1 0 0>;
reg = <2>;
};
phy3: ethernet-phy@3 {
interrupts = <10 1 0 0>;
reg = <3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet1: ethernet@25000 {
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
mdio@25520 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet2: ethernet@26000 {
tbi-handle = <&tbi2>;
phy-handle = <&phy2>;
phy-connection-type = "rgmii-id";
};
mdio@26520 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet3: ethernet@27000 {
tbi-handle = <&tbi3>;
phy-handle = <&phy3>;
phy-connection-type = "rgmii-id";
};
mdio@27520 {
tbi3: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
pci0: pcie@fffe08000 {
reg = <0x0f 0xffe08000 0x0 0x1000>;
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
interrupt-map-mask = <0xff00 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */
0x8800 0 0 1 &mpic 2 1 0 0
0x8800 0 0 2 &mpic 3 1 0 0
0x8800 0 0 3 &mpic 4 1 0 0
0x8800 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 1 - PCI slot 1 */
0x8900 0 0 1 &mpic 2 1 0 0
0x8900 0 0 2 &mpic 3 1 0 0
0x8900 0 0 3 &mpic 4 1 0 0
0x8900 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 2 - PCI slot 1 */
0x8a00 0 0 1 &mpic 2 1 0 0
0x8a00 0 0 2 &mpic 3 1 0 0
0x8a00 0 0 3 &mpic 4 1 0 0
0x8a00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 3 - PCI slot 1 */
0x8b00 0 0 1 &mpic 2 1 0 0
0x8b00 0 0 2 &mpic 3 1 0 0
0x8b00 0 0 3 &mpic 4 1 0 0
0x8b00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 4 - PCI slot 1 */
0x8c00 0 0 1 &mpic 2 1 0 0
0x8c00 0 0 2 &mpic 3 1 0 0
0x8c00 0 0 3 &mpic 4 1 0 0
0x8c00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 5 - PCI slot 1 */
0x8d00 0 0 1 &mpic 2 1 0 0
0x8d00 0 0 2 &mpic 3 1 0 0
0x8d00 0 0 3 &mpic 4 1 0 0
0x8d00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 6 - PCI slot 1 */
0x8e00 0 0 1 &mpic 2 1 0 0
0x8e00 0 0 2 &mpic 3 1 0 0
0x8e00 0 0 3 &mpic 4 1 0 0
0x8e00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 7 - PCI slot 1 */
0x8f00 0 0 1 &mpic 2 1 0 0
0x8f00 0 0 2 &mpic 3 1 0 0
0x8f00 0 0 3 &mpic 4 1 0 0
0x8f00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x12 func 0 - PCI slot 2 */
0x9000 0 0 1 &mpic 3 1 0 0
0x9000 0 0 2 &mpic 4 1 0 0
0x9000 0 0 3 &mpic 1 1 0 0
0x9000 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 1 - PCI slot 2 */
0x9100 0 0 1 &mpic 3 1 0 0
0x9100 0 0 2 &mpic 4 1 0 0
0x9100 0 0 3 &mpic 1 1 0 0
0x9100 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 2 - PCI slot 2 */
0x9200 0 0 1 &mpic 3 1 0 0
0x9200 0 0 2 &mpic 4 1 0 0
0x9200 0 0 3 &mpic 1 1 0 0
0x9200 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 3 - PCI slot 2 */
0x9300 0 0 1 &mpic 3 1 0 0
0x9300 0 0 2 &mpic 4 1 0 0
0x9300 0 0 3 &mpic 1 1 0 0
0x9300 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 4 - PCI slot 2 */
0x9400 0 0 1 &mpic 3 1 0 0
0x9400 0 0 2 &mpic 4 1 0 0
0x9400 0 0 3 &mpic 1 1 0 0
0x9400 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 5 - PCI slot 2 */
0x9500 0 0 1 &mpic 3 1 0 0
0x9500 0 0 2 &mpic 4 1 0 0
0x9500 0 0 3 &mpic 1 1 0 0
0x9500 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 6 - PCI slot 2 */
0x9600 0 0 1 &mpic 3 1 0 0
0x9600 0 0 2 &mpic 4 1 0 0
0x9600 0 0 3 &mpic 1 1 0 0
0x9600 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 7 - PCI slot 2 */
0x9700 0 0 1 &mpic 3 1 0 0
0x9700 0 0 2 &mpic 4 1 0 0
0x9700 0 0 3 &mpic 1 1 0 0
0x9700 0 0 4 &mpic 2 1 0 0
// IDSEL 0x1c USB
0xe000 0 0 1 &i8259 12 2
0xe100 0 0 2 &i8259 9 2
0xe200 0 0 3 &i8259 10 2
0xe300 0 0 4 &i8259 11 2
// IDSEL 0x1d Audio
0xe800 0 0 1 &i8259 6 2
// IDSEL 0x1e Legacy
0xf000 0 0 1 &i8259 7 2
0xf100 0 0 1 &i8259 7 2
// IDSEL 0x1f IDE/SATA
0xf800 0 0 1 &i8259 14 2
0xf900 0 0 1 &i8259 5 2
>;
pcie@0 {
ranges = <0x02000000 0x0 0xe0000000
0x02000000 0x0 0xe0000000
0x0 0x20000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00010000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x02000000 0x0 0xe0000000
0x02000000 0x0 0xe0000000
0x0 0x20000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00010000>;
isa@1e {
device_type = "isa";
#size-cells = <1>;
#address-cells = <2>;
reg = <0xf000 0 0 0 0>;
ranges = <1 0 0x01000000 0 0
0x00001000>;
interrupt-parent = <&i8259>;
i8259: interrupt-controller@20 {
reg = <1 0x20 2
1 0xa0 2
1 0x4d0 2>;
interrupt-controller;
device_type = "interrupt-controller";
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "chrp,iic";
interrupts = <9 2 0 0>;
};
i8042@60 {
#size-cells = <0>;
#address-cells = <1>;
reg = <1 0x60 1 1 0x64 1>;
interrupts = <1 3 12 3>;
interrupt-parent = <&i8259>;
keyboard@0 {
reg = <0>;
compatible = "pnpPNP,303";
};
mouse@1 {
reg = <1>;
compatible = "pnpPNP,f03";
};
};
rtc@70 {
compatible =
"pnpPNP,b00";
reg = <1 0x70 2>;
};
gpio@400 {
reg = <1 0x400 0x80>;
};
};
};
};
};
pci1: pcie@fffe09000 {
reg = <0x0f 0xffe09000 0x0 0x1000>;
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0x0 0xe0000000
0x02000000 0x0 0xe0000000
0x0 0x20000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00010000>;
};
};
};
/include/ "mpc8641si-post.dtsi"

192
arch/powerpc/boot/dts/mpc7448hpc2.dts
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@ -1,192 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC7448HPC2 (Taiga) board Device Tree Source
*
* Copyright 2006, 2008 Freescale Semiconductor Inc.
* 2006 Roy Zang <Roy Zang at freescale.com>.
*/
/dts-v1/;
/ {
model = "mpc7448hpc2";
compatible = "mpc74xx";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells =<0>;
PowerPC,7448@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <0x8000>; // L1, 32K bytes
i-cache-size = <0x8000>; // L1, 32K bytes
timebase-frequency = <0>; // 33 MHz, from uboot
clock-frequency = <0>; // From U-Boot
bus-frequency = <0>; // From U-Boot
};
};
memory {
device_type = "memory";
reg = <0x0 0x20000000 // DDR2 512M at 0
>;
};
tsi108@c0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "tsi-bridge";
ranges = <0x0 0xc0000000 0x10000>;
reg = <0xc0000000 0x10000>;
bus-frequency = <0>;
i2c@7000 {
interrupt-parent = <&mpic>;
interrupts = <14 0>;
reg = <0x7000 0x400>;
device_type = "i2c";
compatible = "tsi108-i2c";
};
MDIO: mdio@6000 {
compatible = "tsi108-mdio";
reg = <0x6000 0x50>;
#address-cells = <1>;
#size-cells = <0>;
phy8: ethernet-phy@8 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <0x8>;
};
phy9: ethernet-phy@9 {
interrupt-parent = <&mpic>;
interrupts = <2 1>;
reg = <0x9>;
};
};
enet0: ethernet@6200 {
linux,network-index = <0>;
#size-cells = <0>;
device_type = "network";
compatible = "tsi108-ethernet";
reg = <0x6000 0x200>;
address = [ 00 06 D2 00 00 01 ];
interrupts = <16 2>;
interrupt-parent = <&mpic>;
mdio-handle = <&MDIO>;
phy-handle = <&phy8>;
};
enet1: ethernet@6600 {
linux,network-index = <1>;
#address-cells = <1>;
#size-cells = <0>;
device_type = "network";
compatible = "tsi108-ethernet";
reg = <0x6400 0x200>;
address = [ 00 06 D2 00 00 02 ];
interrupts = <17 2>;
interrupt-parent = <&mpic>;
mdio-handle = <&MDIO>;
phy-handle = <&phy9>;
};
serial0: serial@7808 {
device_type = "serial";
compatible = "ns16550";
reg = <0x7808 0x200>;
clock-frequency = <1064000000>;
interrupts = <12 0>;
interrupt-parent = <&mpic>;
};
serial1: serial@7c08 {
device_type = "serial";
compatible = "ns16550";
reg = <0x7c08 0x200>;
clock-frequency = <1064000000>;
interrupts = <13 0>;
interrupt-parent = <&mpic>;
};
mpic: pic@7400 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x7400 0x400>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
pci0: pci@1000 {
compatible = "tsi108-pci";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0x1000 0x1000>;
bus-range = <0 0>;
ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
clock-frequency = <133333332>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 */
0x800 0x0 0x0 0x1 &RT0 0x24 0x0
0x800 0x0 0x0 0x2 &RT0 0x25 0x0
0x800 0x0 0x0 0x3 &RT0 0x26 0x0
0x800 0x0 0x0 0x4 &RT0 0x27 0x0
/* IDSEL 0x12 */
0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
/* IDSEL 0x13 */
0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
/* IDSEL 0x14 */
0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
>;
RT0: router@1180 {
clock-frequency = <0>;
interrupt-controller;
device_type = "pic-router";
#address-cells = <0>;
#interrupt-cells = <2>;
big-endian;
interrupts = <23 2>;
interrupt-parent = <&mpic>;
};
};
};
};

263
arch/powerpc/boot/dts/mpc8272ads.dts
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@ -1,263 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8272 ADS Device Tree Source
*
* Copyright 2005,2008 Freescale Semiconductor Inc.
*/
/dts-v1/;
/ {
model = "MPC8272ADS";
compatible = "fsl,mpc8272ads";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &eth0;
ethernet1 = &eth1;
serial0 = &scc1;
serial1 = &scc4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8272@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <16384>;
i-cache-size = <16384>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0>;
};
localbus@f0010100 {
compatible = "fsl,mpc8272-localbus",
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xf0010100 0x40>;
ranges = <0x0 0x0 0xff800000 0x00800000
0x1 0x0 0xf4500000 0x8000
0x3 0x0 0xf8200000 0x8000>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0x0 0x0 0x00800000>;
bank-width = <4>;
device-width = <1>;
};
board-control@1,0 {
reg = <0x1 0x0 0x20>;
compatible = "fsl,mpc8272ads-bcsr";
};
PCI_PIC: interrupt-controller@3,0 {
compatible = "fsl,mpc8272ads-pci-pic",
"fsl,pq2ads-pci-pic";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0x3 0x0 0x8>;
interrupt-parent = <&PIC>;
interrupts = <20 8>;
};
};
pci@f0010800 {
device_type = "pci";
reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
clock-frequency = <66666666>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x16 */
0xb000 0x0 0x0 0x1 &PCI_PIC 0
0xb000 0x0 0x0 0x2 &PCI_PIC 1
0xb000 0x0 0x0 0x3 &PCI_PIC 2
0xb000 0x0 0x0 0x4 &PCI_PIC 3
/* IDSEL 0x17 */
0xb800 0x0 0x0 0x1 &PCI_PIC 4
0xb800 0x0 0x0 0x2 &PCI_PIC 5
0xb800 0x0 0x0 0x3 &PCI_PIC 6
0xb800 0x0 0x0 0x4 &PCI_PIC 7
/* IDSEL 0x18 */
0xc000 0x0 0x0 0x1 &PCI_PIC 8
0xc000 0x0 0x0 0x2 &PCI_PIC 9
0xc000 0x0 0x0 0x3 &PCI_PIC 10
0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
interrupt-parent = <&PIC>;
interrupts = <18 8>;
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
};
soc@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8272", "fsl,pq2-soc";
ranges = <0x0 0xf0000000 0x53000>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <0xf0000000 0x53000>;
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
reg = <0x119c0 0x30>;
ranges;
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0x0 0x2000 0x9800 0x800>;
};
};
brg@119f0 {
compatible = "fsl,mpc8272-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <0x119f0 0x10 0x115f0 0x10>;
};
scc1: serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <0x11a00 0x20 0x8000 0x100>;
interrupts = <40 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0x800000>;
};
scc4: serial@11a60 {
device_type = "serial";
compatible = "fsl,mpc8272-scc-uart",
"fsl,cpm2-scc-uart";
reg = <0x11a60 0x20 0x8300 0x100>;
interrupts = <43 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <4>;
fsl,cpm-command = <0xce00000>;
};
usb@11b60 {
compatible = "fsl,mpc8272-cpm-usb";
reg = <0x11b60 0x40 0x8b00 0x100>;
interrupts = <11 8>;
interrupt-parent = <&PIC>;
mode = "peripheral";
};
mdio@10d40 {
compatible = "fsl,mpc8272ads-mdio-bitbang",
"fsl,mpc8272-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
reg = <0x10d40 0x14>;
#address-cells = <1>;
#size-cells = <0>;
fsl,mdio-pin = <18>;
fsl,mdc-pin = <19>;
PHY0: ethernet-phy@0 {
interrupt-parent = <&PIC>;
interrupts = <23 8>;
reg = <0x0>;
};
PHY1: ethernet-phy@1 {
interrupt-parent = <&PIC>;
interrupts = <23 8>;
reg = <0x3>;
};
};
eth0: ethernet@11300 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <32 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
fsl,cpm-command = <0x12000300>;
};
eth1: ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8272-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <33 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
fsl,cpm-command = <0x16200300>;
};
i2c@11860 {
compatible = "fsl,mpc8272-i2c",
"fsl,cpm2-i2c";
reg = <0x11860 0x20 0x8afc 0x2>;
interrupts = <1 8>;
interrupt-parent = <&PIC>;
fsl,cpm-command = <0x29600000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x10c00 0x80>;
compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
};
crypto@30000 {
compatible = "fsl,sec1.0";
reg = <0x40000 0x13000>;
interrupts = <47 0x8>;
interrupt-parent = <&PIC>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x7e>;
fsl,descriptor-types-mask = <0x1010415>;
};
};
chosen {
stdout-path = "/soc/cpm/serial@11a00";
};
};

436
arch/powerpc/boot/dts/mpc832x_mds.dts
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@ -1,436 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8323E EMDS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
*
* To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
* this:
*
* 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
* 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
* next to the serial ports.
* 3) Solder a wire from U61-22 to P19K-22.
*
* Note that there's a typo in the schematic. The board labels the last column
* of pins "P19K", but in the schematic, that column is called "P19J". So if
* you're going by the schematic, the pin is called "P19J-K22".
*/
/dts-v1/;
/ {
model = "MPC8323EMDS";
compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8323@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <16384>; // L1, 16K
i-cache-size = <16384>; // L1, 16K
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
bcsr@f8000000 {
compatible = "fsl,mpc8323mds-bcsr";
reg = <0xf8000000 0x8000>;
};
soc8323@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <132000000>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
pmc: power@b00 {
compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 0x8>;
interrupt-parent = <&ipic>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <3>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
crypto@30000 {
compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
fsl,num-channels = <1>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x4c>;
fsl,descriptor-types-mask = <0x0122003f>;
sleep = <&pmc 0x03000000>;
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x700 0x100>;
device_type = "ipic";
};
par_io@1400 {
reg = <0x1400 0x100>;
device_type = "par_io";
num-ports = <7>;
pio3: ucc_pin@3 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
0 13 2 0 1 0 /* RX_CLK (CLK9) */
3 24 2 0 1 0 /* TX_CLK (CLK10) */
1 0 1 0 1 0 /* TxD0 */
1 1 1 0 1 0 /* TxD1 */
1 2 1 0 1 0 /* TxD2 */
1 3 1 0 1 0 /* TxD3 */
1 4 2 0 1 0 /* RxD0 */
1 5 2 0 1 0 /* RxD1 */
1 6 2 0 1 0 /* RxD2 */
1 7 2 0 1 0 /* RxD3 */
1 8 2 0 1 0 /* RX_ER */
1 9 1 0 1 0 /* TX_ER */
1 10 2 0 1 0 /* RX_DV */
1 11 2 0 1 0 /* COL */
1 12 1 0 1 0 /* TX_EN */
1 13 2 0 1 0>; /* CRS */
};
pio4: ucc_pin@4 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 31 2 0 1 0 /* RX_CLK (CLK7) */
3 6 2 0 1 0 /* TX_CLK (CLK8) */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 20 1 0 1 0 /* TxD2 */
1 21 1 0 1 0 /* TxD3 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 24 2 0 1 0 /* RxD2 */
1 25 2 0 1 0 /* RxD3 */
1 26 2 0 1 0 /* RX_ER */
1 27 1 0 1 0 /* TX_ER */
1 28 2 0 1 0 /* RX_DV */
1 29 2 0 1 0 /* COL */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0>; /* CRS */
};
pio5: ucc_pin@5 {
pio-map = <
/*
* open has
* port pin dir drain sel irq
*/
2 0 1 0 2 0 /* TxD5 */
2 8 2 0 2 0 /* RxD5 */
2 29 2 0 0 0 /* CTS5 */
2 31 1 0 2 0 /* RTS5 */
2 24 2 0 0 0 /* CD */
>;
};
};
};
qe@e0100000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0x0 0xe0100000 0x00100000>;
reg = <0xe0100000 0x480>;
brg-frequency = <0>;
bus-frequency = <198000000>;
fsl,qe-num-riscs = <1>;
fsl,qe-num-snums = <28>;
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x00010000 0x00004000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0x4000>;
};
};
spi@4c0 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x4c0 0x40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "cpu";
};
spi@500 {
cell-index = <1>;
compatible = "fsl,spi";
reg = <0x500 0x40>;
interrupts = <1>;
interrupt-parent = <&qeic>;
mode = "cpu";
};
usb@6c0 {
compatible = "qe_udc";
reg = <0x6c0 0x40 0x8b00 0x100>;
interrupts = <11>;
interrupt-parent = <&qeic>;
mode = "slave";
};
enet0: ucc@2200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <3>;
reg = <0x2200 0x200>;
interrupts = <34>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "clk9";
tx-clock-name = "clk10";
phy-handle = <&phy3>;
pio-handle = <&pio3>;
};
enet1: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "clk7";
tx-clock-name = "clk8";
phy-handle = <&phy4>;
pio-handle = <&pio4>;
};
ucc@2400 {
device_type = "serial";
compatible = "ucc_uart";
cell-index = <5>; /* The UCC number, 1-7*/
port-number = <0>; /* Which ttyQEx device */
soft-uart; /* We need Soft-UART */
reg = <0x2400 0x200>;
interrupts = <40>; /* From Table 18-12 */
interrupt-parent = < &qeic >;
/*
* For Soft-UART, we need to set TX to 1X, which
* means specifying separate clock sources.
*/
rx-clock-name = "brg5";
tx-clock-name = "brg6";
pio-handle = < &pio5 >;
};
mdio@2320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2320 0x18>;
compatible = "fsl,ucc-mdio";
phy3: ethernet-phy@3 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x3>;
};
phy4: ethernet-phy@4 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x4>;
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
big-endian;
interrupts = <32 0x8 33 0x8>; //high:32 low:33
interrupt-parent = <&ipic>;
};
};
pci0: pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
0x8800 0x0 0x0 0x1 &ipic 20 0x8
0x8800 0x0 0x0 0x2 &ipic 21 0x8
0x8800 0x0 0x0 0x3 &ipic 22 0x8
0x8800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x12 AD18 */
0x9000 0x0 0x0 0x1 &ipic 22 0x8
0x9000 0x0 0x0 0x2 &ipic 23 0x8
0x9000 0x0 0x0 0x3 &ipic 20 0x8
0x9000 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x13 AD19 */
0x9800 0x0 0x0 0x1 &ipic 23 0x8
0x9800 0x0 0x0 0x2 &ipic 20 0x8
0x9800 0x0 0x0 0x3 &ipic 21 0x8
0x9800 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x15 AD21*/
0xa800 0x0 0x0 0x1 &ipic 20 0x8
0xa800 0x0 0x0 0x2 &ipic 21 0x8
0xa800 0x0 0x0 0x3 &ipic 22 0x8
0xa800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x16 AD22*/
0xb000 0x0 0x0 0x1 &ipic 23 0x8
0xb000 0x0 0x0 0x2 &ipic 20 0x8
0xb000 0x0 0x0 0x3 &ipic 21 0x8
0xb000 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x17 AD23*/
0xb800 0x0 0x0 0x1 &ipic 22 0x8
0xb800 0x0 0x0 0x2 &ipic 23 0x8
0xb800 0x0 0x0 0x3 &ipic 20 0x8
0xb800 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x18 AD24*/
0xc000 0x0 0x0 0x1 &ipic 21 0x8
0xc000 0x0 0x0 0x2 &ipic 22 0x8
0xc000 0x0 0x0 0x3 &ipic 23 0x8
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100 /* internal registers */
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
sleep = <&pmc 0x00010000>;
};
};

403
arch/powerpc/boot/dts/mpc834x_mds.dts
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@ -1,403 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8349E MDS Device Tree Source
*
* Copyright 2005, 2006 Freescale Semiconductor Inc.
*/
/dts-v1/;
/ {
model = "MPC8349EMDS";
compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8349@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; // 256MB at 0
};
bcsr@e2400000 {
compatible = "fsl,mpc8349mds-bcsr";
reg = <0xe2400000 0x8000>;
};
soc8349@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <15 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
};
spi@7000 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <16 0x8>;
interrupt-parent = <&ipic>;
mode = "cpu";
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <3>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
/* phy type (ULPI or SERIAL) are only types supported for MPH */
/* port = 0 or 1 */
usb@22000 {
compatible = "fsl-usb2-mph";
reg = <0x22000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <39 0x8>;
phy_type = "ulpi";
port0;
};
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
dr_mode = "otg";
phy_type = "ulpi";
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <32 0x8 33 0x8 34 0x8>;
interrupt-parent = <&ipic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
linux,network-index = <0>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy0: ethernet-phy@0 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x1>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "TSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 0x8 36 0x8 37 0x8>;
interrupt-parent = <&ipic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy1>;
linux,network-index = <1>;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
};
crypto@30000 {
compatible = "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x7e>;
fsl,descriptor-types-mask = <0x01010ebf>;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x700 0x100>;
device_type = "ipic";
};
};
pci0: pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 */
0x8800 0x0 0x0 0x1 &ipic 20 0x8
0x8800 0x0 0x0 0x2 &ipic 21 0x8
0x8800 0x0 0x0 0x3 &ipic 22 0x8
0x8800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x12 */
0x9000 0x0 0x0 0x1 &ipic 22 0x8
0x9000 0x0 0x0 0x2 &ipic 23 0x8
0x9000 0x0 0x0 0x3 &ipic 20 0x8
0x9000 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x13 */
0x9800 0x0 0x0 0x1 &ipic 23 0x8
0x9800 0x0 0x0 0x2 &ipic 20 0x8
0x9800 0x0 0x0 0x3 &ipic 21 0x8
0x9800 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &ipic 20 0x8
0xa800 0x0 0x0 0x2 &ipic 21 0x8
0xa800 0x0 0x0 0x3 &ipic 22 0x8
0xa800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x16 */
0xb000 0x0 0x0 0x1 &ipic 23 0x8
0xb000 0x0 0x0 0x2 &ipic 20 0x8
0xb000 0x0 0x0 0x3 &ipic 21 0x8
0xb000 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x17 */
0xb800 0x0 0x0 0x1 &ipic 22 0x8
0xb800 0x0 0x0 0x2 &ipic 23 0x8
0xb800 0x0 0x0 0x3 &ipic 20 0x8
0xb800 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x18 */
0xc000 0x0 0x0 0x1 &ipic 21 0x8
0xc000 0x0 0x0 0x2 &ipic 22 0x8
0xc000 0x0 0x0 0x3 &ipic 23 0x8
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0 0>;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100 /* internal registers */
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci1: pci@e0008600 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 */
0x8800 0x0 0x0 0x1 &ipic 20 0x8
0x8800 0x0 0x0 0x2 &ipic 21 0x8
0x8800 0x0 0x0 0x3 &ipic 22 0x8
0x8800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x12 */
0x9000 0x0 0x0 0x1 &ipic 22 0x8
0x9000 0x0 0x0 0x2 &ipic 23 0x8
0x9000 0x0 0x0 0x3 &ipic 20 0x8
0x9000 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x13 */
0x9800 0x0 0x0 0x1 &ipic 23 0x8
0x9800 0x0 0x0 0x2 &ipic 20 0x8
0x9800 0x0 0x0 0x3 &ipic 21 0x8
0x9800 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &ipic 20 0x8
0xa800 0x0 0x0 0x2 &ipic 21 0x8
0xa800 0x0 0x0 0x3 &ipic 22 0x8
0xa800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x16 */
0xb000 0x0 0x0 0x1 &ipic 23 0x8
0xb000 0x0 0x0 0x2 &ipic 20 0x8
0xb000 0x0 0x0 0x3 &ipic 21 0x8
0xb000 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x17 */
0xb800 0x0 0x0 0x1 &ipic 22 0x8
0xb800 0x0 0x0 0x2 &ipic 23 0x8
0xb800 0x0 0x0 0x3 &ipic 20 0x8
0xb800 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x18 */
0xc000 0x0 0x0 0x1 &ipic 21 0x8
0xc000 0x0 0x0 0x2 &ipic 22 0x8
0xc000 0x0 0x0 0x3 &ipic 23 0x8
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
interrupt-parent = <&ipic>;
interrupts = <67 0x8>;
bus-range = <0 0>;
ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008600 0x100 /* internal registers */
0xe0008380 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};

481
arch/powerpc/boot/dts/mpc836x_mds.dts
View File

@ -1,481 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8360E EMDS Device Tree Source
*
* Copyright 2006 Freescale Semiconductor Inc.
*/
/*
/memreserve/ 00000000 1000000;
*/
/dts-v1/;
/ {
model = "MPC8360MDS";
compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8360@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <32768>; // L1, 32K
i-cache-size = <32768>; // L1, 32K
timebase-frequency = <66000000>;
bus-frequency = <264000000>;
clock-frequency = <528000000>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
ranges = <0 0 0xfe000000 0x02000000
1 0 0xf8000000 0x00008000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x2000000>;
bank-width = <2>;
device-width = <1>;
};
bcsr@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8360mds-bcsr";
reg = <1 0 0x8000>;
ranges = <0 1 0 0x8000>;
bcsr13: gpio-controller@d {
#gpio-cells = <2>;
compatible = "fsl,mpc8360mds-bcsr-gpio";
reg = <0xd 1>;
gpio-controller;
};
};
};
soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <264000000>;
wdt@200 {
device_type = "watchdog";
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
pmc: power@b00 {
compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 0x8>;
interrupt-parent = <&ipic>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <15 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <264000000>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <264000000>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <3>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
crypto@30000 {
compatible = "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x7e>;
fsl,descriptor-types-mask = <0x01010ebf>;
sleep = <&pmc 0x03000000>;
};
ipic: pic@700 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x700 0x100>;
device_type = "ipic";
};
par_io@1400 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1400 0x100>;
ranges = <0 0x1400 0x100>;
device_type = "par_io";
num-ports = <7>;
qe_pio_b: gpio-controller@18 {
#gpio-cells = <2>;
compatible = "fsl,mpc8360-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0x18 0x18>;
gpio-controller;
};
pio1: ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 3 1 0 1 0 /* TxD0 */
0 4 1 0 1 0 /* TxD1 */
0 5 1 0 1 0 /* TxD2 */
0 6 1 0 1 0 /* TxD3 */
1 6 1 0 3 0 /* TxD4 */
1 7 1 0 1 0 /* TxD5 */
1 9 1 0 2 0 /* TxD6 */
1 10 1 0 2 0 /* TxD7 */
0 9 2 0 1 0 /* RxD0 */
0 10 2 0 1 0 /* RxD1 */
0 11 2 0 1 0 /* RxD2 */
0 12 2 0 1 0 /* RxD3 */
0 13 2 0 1 0 /* RxD4 */
1 1 2 0 2 0 /* RxD5 */
1 0 2 0 2 0 /* RxD6 */
1 4 2 0 2 0 /* RxD7 */
0 7 1 0 1 0 /* TX_EN */
0 8 1 0 1 0 /* TX_ER */
0 15 2 0 1 0 /* RX_DV */
0 16 2 0 1 0 /* RX_ER */
0 0 2 0 1 0 /* RX_CLK */
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
2 8 2 0 1 0>; /* GTX125 - CLK9 */
};
pio2: ucc_pin@2 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 17 1 0 1 0 /* TxD0 */
0 18 1 0 1 0 /* TxD1 */
0 19 1 0 1 0 /* TxD2 */
0 20 1 0 1 0 /* TxD3 */
1 2 1 0 1 0 /* TxD4 */
1 3 1 0 2 0 /* TxD5 */
1 5 1 0 3 0 /* TxD6 */
1 8 1 0 3 0 /* TxD7 */
0 23 2 0 1 0 /* RxD0 */
0 24 2 0 1 0 /* RxD1 */
0 25 2 0 1 0 /* RxD2 */
0 26 2 0 1 0 /* RxD3 */
0 27 2 0 1 0 /* RxD4 */
1 12 2 0 2 0 /* RxD5 */
1 13 2 0 3 0 /* RxD6 */
1 11 2 0 2 0 /* RxD7 */
0 21 1 0 1 0 /* TX_EN */
0 22 1 0 1 0 /* TX_ER */
0 29 2 0 1 0 /* RX_DV */
0 30 2 0 1 0 /* RX_ER */
0 31 2 0 1 0 /* RX_CLK */
2 2 1 0 2 0 /* GTX_CLK - CLK10 */
2 3 2 0 1 0 /* GTX125 - CLK4 */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0>; /* MDC */
};
};
};
qe@e0100000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0x0 0xe0100000 0x00100000>;
reg = <0xe0100000 0x480>;
brg-frequency = <0>;
bus-frequency = <396000000>;
fsl,qe-num-riscs = <2>;
fsl,qe-num-snums = <28>;
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x00010000 0x0000c000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0xc000>;
};
};
timer@440 {
compatible = "fsl,mpc8360-qe-gtm",
"fsl,qe-gtm", "fsl,gtm";
reg = <0x440 0x40>;
clock-frequency = <132000000>;
interrupts = <12 13 14 15>;
interrupt-parent = <&qeic>;
};
spi@4c0 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x4c0 0x40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "cpu";
};
spi@500 {
cell-index = <1>;
compatible = "fsl,spi";
reg = <0x500 0x40>;
interrupts = <1>;
interrupt-parent = <&qeic>;
mode = "cpu";
};
usb@6c0 {
compatible = "fsl,mpc8360-qe-usb",
"fsl,mpc8323-qe-usb";
reg = <0x6c0 0x40 0x8b00 0x100>;
interrupts = <11>;
interrupt-parent = <&qeic>;
fsl,fullspeed-clock = "clk21";
fsl,lowspeed-clock = "brg9";
gpios = <&qe_pio_b 2 0 /* USBOE */
&qe_pio_b 3 0 /* USBTP */
&qe_pio_b 8 0 /* USBTN */
&qe_pio_b 9 0 /* USBRP */
&qe_pio_b 11 0 /* USBRN */
&bcsr13 5 0 /* SPEED */
&bcsr13 4 1>; /* POWER */
};
enet0: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk9";
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio1>;
};
enet1: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <2>;
reg = <0x3000 0x200>;
interrupts = <33>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk4";
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio2>;
};
mdio@2120 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2120 0x18>;
compatible = "fsl,ucc-mdio";
phy0: ethernet-phy@0 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x1>;
};
tbi-phy@2 {
device_type = "tbi-phy";
reg = <0x2>;
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
big-endian;
interrupts = <32 0x8 33 0x8>; // high:32 low:33
interrupt-parent = <&ipic>;
};
};
pci0: pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 AD17 */
0x8800 0x0 0x0 0x1 &ipic 20 0x8
0x8800 0x0 0x0 0x2 &ipic 21 0x8
0x8800 0x0 0x0 0x3 &ipic 22 0x8
0x8800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x12 AD18 */
0x9000 0x0 0x0 0x1 &ipic 22 0x8
0x9000 0x0 0x0 0x2 &ipic 23 0x8
0x9000 0x0 0x0 0x3 &ipic 20 0x8
0x9000 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x13 AD19 */
0x9800 0x0 0x0 0x1 &ipic 23 0x8
0x9800 0x0 0x0 0x2 &ipic 20 0x8
0x9800 0x0 0x0 0x3 &ipic 21 0x8
0x9800 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x15 AD21*/
0xa800 0x0 0x0 0x1 &ipic 20 0x8
0xa800 0x0 0x0 0x2 &ipic 21 0x8
0xa800 0x0 0x0 0x3 &ipic 22 0x8
0xa800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x16 AD22*/
0xb000 0x0 0x0 0x1 &ipic 23 0x8
0xb000 0x0 0x0 0x2 &ipic 20 0x8
0xb000 0x0 0x0 0x3 &ipic 21 0x8
0xb000 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x17 AD23*/
0xb800 0x0 0x0 0x1 &ipic 22 0x8
0xb800 0x0 0x0 0x2 &ipic 23 0x8
0xb800 0x0 0x0 0x3 &ipic 20 0x8
0xb800 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x18 AD24*/
0xc000 0x0 0x0 0x1 &ipic 21 0x8
0xc000 0x0 0x0 0x2 &ipic 22 0x8
0xc000 0x0 0x0 0x3 &ipic 23 0x8
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0 0>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
clock-frequency = <66666666>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100 /* internal registers */
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
sleep = <&pmc 0x00010000>;
};
};

505
arch/powerpc/boot/dts/mpc8377_mds.dts
View File

@ -1,505 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8377E MDS Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
*/
/dts-v1/;
/ {
model = "fsl,mpc8377emds";
compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8377@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512MB at 0
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <77 0x8>;
interrupt-parent = <&ipic>;
// booting from NOR flash
ranges = <0 0x0 0xfe000000 0x02000000
1 0x0 0xf8000000 0x00008000
3 0x0 0xe0600000 0x00008000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
fs@100000 {
reg = <0x100000 0x800000>;
};
kernel@1d00000 {
reg = <0x1d00000 0x200000>;
};
dtb@1f00000 {
reg = <0x1f00000 0x100000>;
};
};
bcsr@1,0 {
reg = <1 0x0 0x8000>;
compatible = "fsl,mpc837xmds-bcsr";
};
nand@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8377-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <3 0x0 0x8000>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
kernel@100000 {
reg = <0x100000 0x300000>;
};
fs@400000 {
reg = <0x400000 0x1c00000>;
};
};
};
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>;
wdt@200 {
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
sleep-nexus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
sleep = <&pmc 0x0c000000>;
ranges;
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
interrupts = <19 0x8>;
interrupt-parent = <&ipic>;
};
};
sdhci@2e000 {
compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
sdhci,wp-inverted;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <15 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
};
spi@7000 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <16 0x8>;
interrupt-parent = <&ipic>;
mode = "cpu";
};
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
dr_mode = "host";
phy_type = "ulpi";
sleep = <&pmc 0x00c00000>;
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <32 0x8 33 0x8 34 0x8>;
phy-connection-type = "mii";
interrupt-parent = <&ipic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy2>;
sleep = <&pmc 0xc0000000>;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy2: ethernet-phy@2 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x2>;
};
phy3: ethernet-phy@3 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 0x8 36 0x8 37 0x8>;
phy-connection-type = "mii";
interrupt-parent = <&ipic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy3>;
sleep = <&pmc 0x30000000>;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <0x47 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&ipic>;
interrupts = <0x47 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&ipic>;
interrupts = <0x47 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&ipic>;
interrupts = <0x47 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <3>;
interrupt-parent = <&ipic>;
interrupts = <0x47 8>;
};
};
crypto@30000 {
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
"fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x9fe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
sleep = <&pmc 0x03000000>;
};
sata@18000 {
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
interrupts = <44 0x8>;
interrupt-parent = <&ipic>;
sleep = <&pmc 0x000000c0>;
};
sata@19000 {
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
interrupts = <45 0x8>;
interrupt-parent = <&ipic>;
sleep = <&pmc 0x00000030>;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: pic@700 {
compatible = "fsl,ipic";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x700 0x100>;
};
pmc: power@b00 {
compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 0x8>;
interrupt-parent = <&ipic>;
};
};
pci0: pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 */
0x8800 0x0 0x0 0x1 &ipic 20 0x8
0x8800 0x0 0x0 0x2 &ipic 21 0x8
0x8800 0x0 0x0 0x3 &ipic 22 0x8
0x8800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x12 */
0x9000 0x0 0x0 0x1 &ipic 22 0x8
0x9000 0x0 0x0 0x2 &ipic 23 0x8
0x9000 0x0 0x0 0x3 &ipic 20 0x8
0x9000 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x13 */
0x9800 0x0 0x0 0x1 &ipic 23 0x8
0x9800 0x0 0x0 0x2 &ipic 20 0x8
0x9800 0x0 0x0 0x3 &ipic 21 0x8
0x9800 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &ipic 20 0x8
0xa800 0x0 0x0 0x2 &ipic 21 0x8
0xa800 0x0 0x0 0x3 &ipic 22 0x8
0xa800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x16 */
0xb000 0x0 0x0 0x1 &ipic 23 0x8
0xb000 0x0 0x0 0x2 &ipic 20 0x8
0xb000 0x0 0x0 0x3 &ipic 21 0x8
0xb000 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x17 */
0xb800 0x0 0x0 0x1 &ipic 22 0x8
0xb800 0x0 0x0 0x2 &ipic 23 0x8
0xb800 0x0 0x0 0x3 &ipic 20 0x8
0xb800 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x18 */
0xc000 0x0 0x0 0x1 &ipic 21 0x8
0xc000 0x0 0x0 0x2 &ipic 22 0x8
0xc000 0x0 0x0 0x3 &ipic 23 0x8
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
sleep = <&pmc 0x00010000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100 /* internal registers */
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci1: pcie@e0009000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
reg = <0xe0009000 0x00001000>;
ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0 0 0 1 &ipic 1 8
0 0 0 2 &ipic 1 8
0 0 0 3 &ipic 1 8
0 0 0 4 &ipic 1 8>;
sleep = <&pmc 0x00300000>;
clock-frequency = <0>;
pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
reg = <0 0 0 0 0>;
ranges = <0x02000000 0 0xa8000000
0x02000000 0 0xa8000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00800000>;
};
};
pci2: pcie@e000a000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
reg = <0xe000a000 0x00001000>;
ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0 0 0 1 &ipic 2 8
0 0 0 2 &ipic 2 8
0 0 0 3 &ipic 2 8
0 0 0 4 &ipic 2 8>;
sleep = <&pmc 0x000c0000>;
clock-frequency = <0>;
pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
reg = <0 0 0 0 0>;
ranges = <0x02000000 0 0xc8000000
0x02000000 0 0xc8000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00800000>;
};
};
};

489
arch/powerpc/boot/dts/mpc8378_mds.dts
View File

@ -1,489 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8378E MDS Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
*/
/dts-v1/;
/ {
model = "fsl,mpc8378emds";
compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8378@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512MB at 0
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <77 0x8>;
interrupt-parent = <&ipic>;
// booting from NOR flash
ranges = <0 0x0 0xfe000000 0x02000000
1 0x0 0xf8000000 0x00008000
3 0x0 0xe0600000 0x00008000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
fs@100000 {
reg = <0x100000 0x800000>;
};
kernel@1d00000 {
reg = <0x1d00000 0x200000>;
};
dtb@1f00000 {
reg = <0x1f00000 0x100000>;
};
};
bcsr@1,0 {
reg = <1 0x0 0x8000>;
compatible = "fsl,mpc837xmds-bcsr";
};
nand@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8378-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <3 0x0 0x8000>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
kernel@100000 {
reg = <0x100000 0x300000>;
};
fs@400000 {
reg = <0x400000 0x1c00000>;
};
};
};
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>;
wdt@200 {
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
sleep-nexus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
sleep = <&pmc 0x0c000000>;
ranges;
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
interrupts = <19 0x8>;
interrupt-parent = <&ipic>;
};
};
sdhci@2e000 {
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
sdhci,wp-inverted;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <15 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
};
spi@7000 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <16 0x8>;
interrupt-parent = <&ipic>;
mode = "cpu";
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <3>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
dr_mode = "host";
phy_type = "ulpi";
sleep = <&pmc 0x00c00000>;
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <32 0x8 33 0x8 34 0x8>;
phy-connection-type = "mii";
interrupt-parent = <&ipic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy2>;
sleep = <&pmc 0xc0000000>;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy2: ethernet-phy@2 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x2>;
};
phy3: ethernet-phy@3 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 0x8 36 0x8 37 0x8>;
phy-connection-type = "mii";
interrupt-parent = <&ipic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy3>;
sleep = <&pmc 0x30000000>;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
};
crypto@30000 {
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
"fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x9fe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
sleep = <&pmc 0x03000000>;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: pic@700 {
compatible = "fsl,ipic";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x700 0x100>;
};
pmc: power@b00 {
compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 0x8>;
interrupt-parent = <&ipic>;
};
};
pci0: pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 */
0x8800 0x0 0x0 0x1 &ipic 20 0x8
0x8800 0x0 0x0 0x2 &ipic 21 0x8
0x8800 0x0 0x0 0x3 &ipic 22 0x8
0x8800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x12 */
0x9000 0x0 0x0 0x1 &ipic 22 0x8
0x9000 0x0 0x0 0x2 &ipic 23 0x8
0x9000 0x0 0x0 0x3 &ipic 20 0x8
0x9000 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x13 */
0x9800 0x0 0x0 0x1 &ipic 23 0x8
0x9800 0x0 0x0 0x2 &ipic 20 0x8
0x9800 0x0 0x0 0x3 &ipic 21 0x8
0x9800 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &ipic 20 0x8
0xa800 0x0 0x0 0x2 &ipic 21 0x8
0xa800 0x0 0x0 0x3 &ipic 22 0x8
0xa800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x16 */
0xb000 0x0 0x0 0x1 &ipic 23 0x8
0xb000 0x0 0x0 0x2 &ipic 20 0x8
0xb000 0x0 0x0 0x3 &ipic 21 0x8
0xb000 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x17 */
0xb800 0x0 0x0 0x1 &ipic 22 0x8
0xb800 0x0 0x0 0x2 &ipic 23 0x8
0xb800 0x0 0x0 0x3 &ipic 20 0x8
0xb800 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x18 */
0xc000 0x0 0x0 0x1 &ipic 21 0x8
0xc000 0x0 0x0 0x2 &ipic 22 0x8
0xc000 0x0 0x0 0x3 &ipic 23 0x8
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
clock-frequency = <0>;
sleep = <&pmc 0x00010000>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100 /* internal registers */
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
pci1: pcie@e0009000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
reg = <0xe0009000 0x00001000>;
ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0 0 0 1 &ipic 1 8
0 0 0 2 &ipic 1 8
0 0 0 3 &ipic 1 8
0 0 0 4 &ipic 1 8>;
sleep = <&pmc 0x00300000>;
clock-frequency = <0>;
pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
reg = <0 0 0 0 0>;
ranges = <0x02000000 0 0xa8000000
0x02000000 0 0xa8000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00800000>;
};
};
pci2: pcie@e000a000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
reg = <0xe000a000 0x00001000>;
ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0 0 0 1 &ipic 2 8
0 0 0 2 &ipic 2 8
0 0 0 3 &ipic 2 8
0 0 0 4 &ipic 2 8>;
sleep = <&pmc 0x000c0000>;
clock-frequency = <0>;
pcie@0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
reg = <0 0 0 0 0>;
ranges = <0x02000000 0 0xc8000000
0x02000000 0 0xc8000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00800000>;
};
};
};

455
arch/powerpc/boot/dts/mpc8379_mds.dts
View File

@ -1,455 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC8379E MDS Device Tree Source
*
* Copyright 2007 Freescale Semiconductor Inc.
*/
/dts-v1/;
/ {
model = "fsl,mpc8379emds";
compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8379@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>;
i-cache-size = <32768>;
timebase-frequency = <0>;
bus-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512MB at 0
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <77 0x8>;
interrupt-parent = <&ipic>;
// booting from NOR flash
ranges = <0 0x0 0xfe000000 0x02000000
1 0x0 0xf8000000 0x00008000
3 0x0 0xe0600000 0x00008000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
fs@100000 {
reg = <0x100000 0x800000>;
};
kernel@1d00000 {
reg = <0x1d00000 0x200000>;
};
dtb@1f00000 {
reg = <0x1f00000 0x100000>;
};
};
bcsr@1,0 {
reg = <1 0x0 0x8000>;
compatible = "fsl,mpc837xmds-bcsr";
};
nand@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8379-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <3 0x0 0x8000>;
u-boot@0 {
reg = <0x0 0x100000>;
read-only;
};
kernel@100000 {
reg = <0x100000 0x300000>;
};
fs@400000 {
reg = <0x400000 0x1c00000>;
};
};
};
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>;
wdt@200 {
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
};
sleep-nexus {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
sleep = <&pmc 0x0c000000>;
ranges;
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
interrupts = <19 0x8>;
interrupt-parent = <&ipic>;
};
};
sdhci@2e000 {
compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
reg = <0x2e000 0x1000>;
interrupts = <42 0x8>;
interrupt-parent = <&ipic>;
sdhci,wp-inverted;
/* Filled in by U-Boot */
clock-frequency = <0>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <15 0x8>;
interrupt-parent = <&ipic>;
dfsrr;
};
spi@7000 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <16 0x8>;
interrupt-parent = <&ipic>;
mode = "cpu";
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x28>;
cell-index = <3>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
usb@23000 {
compatible = "fsl-usb2-dr";
reg = <0x23000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&ipic>;
interrupts = <38 0x8>;
dr_mode = "host";
phy_type = "ulpi";
sleep = <&pmc 0x00c00000>;
};
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <32 0x8 33 0x8 34 0x8>;
phy-connection-type = "mii";
interrupt-parent = <&ipic>;
tbi-handle = <&tbi0>;
phy-handle = <&phy2>;
sleep = <&pmc 0xc0000000>;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x520 0x20>;
phy2: ethernet-phy@2 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x2>;
};
phy3: ethernet-phy@3 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x3>;
};
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
enet1: ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 0x8 36 0x8 37 0x8>;
phy-connection-type = "mii";
interrupt-parent = <&ipic>;
tbi-handle = <&tbi1>;
phy-handle = <&phy3>;
sleep = <&pmc 0x30000000>;
fsl,magic-packet;
mdio@520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x520 0x20>;
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
};
crypto@30000 {
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
"fsl,sec2.1", "fsl,sec2.0";
reg = <0x30000 0x10000>;
interrupts = <11 0x8>;
interrupt-parent = <&ipic>;
fsl,num-channels = <4>;
fsl,channel-fifo-len = <24>;
fsl,exec-units-mask = <0x9fe>;
fsl,descriptor-types-mask = <0x3ab0ebf>;
sleep = <&pmc 0x03000000>;
};
sata@18000 {
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
reg = <0x18000 0x1000>;
interrupts = <44 0x8>;
interrupt-parent = <&ipic>;
sleep = <&pmc 0x000000c0>;
};
sata@19000 {
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
reg = <0x19000 0x1000>;
interrupts = <45 0x8>;
interrupt-parent = <&ipic>;
sleep = <&pmc 0x00000030>;
};
sata@1a000 {
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
reg = <0x1a000 0x1000>;
interrupts = <46 0x8>;
interrupt-parent = <&ipic>;
sleep = <&pmc 0x0000000c>;
};
sata@1b000 {
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
reg = <0x1b000 0x1000>;
interrupts = <47 0x8>;
interrupt-parent = <&ipic>;
sleep = <&pmc 0x00000003>;
};
/* IPIC
* interrupts cell = <intr #, sense>
* sense values match linux IORESOURCE_IRQ_* defines:
* sense == 8: Level, low assertion
* sense == 2: Edge, high-to-low change
*/
ipic: pic@700 {
compatible = "fsl,ipic";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x700 0x100>;
};
pmc: power@b00 {
compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 0x8>;
interrupt-parent = <&ipic>;
};
};
pci0: pci@e0008500 {
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x11 */
0x8800 0x0 0x0 0x1 &ipic 20 0x8
0x8800 0x0 0x0 0x2 &ipic 21 0x8
0x8800 0x0 0x0 0x3 &ipic 22 0x8
0x8800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x12 */
0x9000 0x0 0x0 0x1 &ipic 22 0x8
0x9000 0x0 0x0 0x2 &ipic 23 0x8
0x9000 0x0 0x0 0x3 &ipic 20 0x8
0x9000 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x13 */
0x9800 0x0 0x0 0x1 &ipic 23 0x8
0x9800 0x0 0x0 0x2 &ipic 20 0x8
0x9800 0x0 0x0 0x3 &ipic 21 0x8
0x9800 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x15 */
0xa800 0x0 0x0 0x1 &ipic 20 0x8
0xa800 0x0 0x0 0x2 &ipic 21 0x8
0xa800 0x0 0x0 0x3 &ipic 22 0x8
0xa800 0x0 0x0 0x4 &ipic 23 0x8
/* IDSEL 0x16 */
0xb000 0x0 0x0 0x1 &ipic 23 0x8
0xb000 0x0 0x0 0x2 &ipic 20 0x8
0xb000 0x0 0x0 0x3 &ipic 21 0x8
0xb000 0x0 0x0 0x4 &ipic 22 0x8
/* IDSEL 0x17 */
0xb800 0x0 0x0 0x1 &ipic 22 0x8
0xb800 0x0 0x0 0x2 &ipic 23 0x8
0xb800 0x0 0x0 0x3 &ipic 20 0x8
0xb800 0x0 0x0 0x4 &ipic 21 0x8
/* IDSEL 0x18 */
0xc000 0x0 0x0 0x1 &ipic 21 0x8
0xc000 0x0 0x0 0x2 &ipic 22 0x8
0xc000 0x0 0x0 0x3 &ipic 23 0x8
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
interrupt-parent = <&ipic>;
interrupts = <66 0x8>;
bus-range = <0x0 0x0>;
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
sleep = <&pmc 0x00010000>;
clock-frequency = <0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008500 0x100 /* internal registers */
0xe0008300 0x8>; /* config space access registers */
compatible = "fsl,mpc8349-pci";
device_type = "pci";
};
};

503
arch/powerpc/boot/dts/mpc8610_hpcd.dts
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@ -1,503 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* MPC8610 HPCD Device Tree Source
*
* Copyright 2007-2008 Freescale Semiconductor Inc.
*/
/dts-v1/;
/ {
model = "MPC8610HPCD";
compatible = "fsl,MPC8610HPCD";
#address-cells = <1>;
#size-cells = <1>;
aliases {
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8610@0 {
device_type = "cpu";
reg = <0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <32768>; // L1
i-cache-size = <32768>; // L1
sleep = <&pmc 0x00008000 0 // core
&pmc 0x00004000 0>; // timebase
timebase-frequency = <0>; // From uboot
bus-frequency = <0>; // From uboot
clock-frequency = <0>; // From uboot
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; // 512M at 0x0
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
reg = <0xe0005000 0x1000>;
interrupts = <19 2>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xf8000000 0x08000000
1 0 0xf0000000 0x08000000
2 0 0xe8400000 0x00008000
4 0 0xe8440000 0x00008000
5 0 0xe8480000 0x00008000
6 0 0xe84c0000 0x00008000
3 0 0xe8000000 0x00000020>;
sleep = <&pmc 0x08000000 0>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
flash@1,0 {
compatible = "cfi-flash";
reg = <1 0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
flash@2,0 {
compatible = "fsl,mpc8610-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <2 0 0x8000>;
};
flash@4,0 {
compatible = "fsl,mpc8610-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <4 0 0x8000>;
};
flash@5,0 {
compatible = "fsl,mpc8610-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <5 0 0x8000>;
};
flash@6,0 {
compatible = "fsl,mpc8610-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <6 0 0x8000>;
};
board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,fpga-pixis";
reg = <3 0 0x20>;
ranges = <0 3 0 0x20>;
interrupt-parent = <&mpic>;
interrupts = <8 8>;
sdcsr_pio: gpio-controller@a {
#gpio-cells = <2>;
compatible = "fsl,fpga-pixis-gpio-bank";
reg = <0xa 1>;
gpio-controller;
};
};
};
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
compatible = "fsl,mpc8610-immr", "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
bus-frequency = <0>;
mcm-law@0 {
compatible = "fsl,mcm-law";
reg = <0x0 0x1000>;
fsl,num-laws = <10>;
};
mcm@1000 {
compatible = "fsl,mpc8610-mcm", "fsl,mcm";
reg = <0x1000 0x1000>;
interrupts = <17 2>;
interrupt-parent = <&mpic>;
};
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
dfsrr;
cs4270:codec@4f {
compatible = "cirrus,cs4270";
reg = <0x4f>;
/* MCLK source is a stand-alone oscillator */
clock-frequency = <12288000>;
};
};
i2c@3100 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
compatible = "fsl-i2c";
reg = <0x3100 0x100>;
interrupts = <43 2>;
interrupt-parent = <&mpic>;
sleep = <&pmc 0x00000004 0>;
dfsrr;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
sleep = <&pmc 0x00000002 0>;
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <0>;
interrupts = <42 2>;
interrupt-parent = <&mpic>;
sleep = <&pmc 0x00000008 0>;
};
spi@7000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc8610-spi", "fsl,spi";
reg = <0x7000 0x40>;
cell-index = <0>;
interrupts = <59 2>;
interrupt-parent = <&mpic>;
mode = "cpu";
cs-gpios = <&sdcsr_pio 7 0>;
sleep = <&pmc 0x00000800 0>;
mmc-slot@0 {
compatible = "fsl,mpc8610hpcd-mmc-slot",
"mmc-spi-slot";
reg = <0>;
gpios = <&sdcsr_pio 0 1 /* nCD */
&sdcsr_pio 1 0>; /* WP */
voltage-ranges = <3300 3300>;
spi-max-frequency = <50000000>;
};
};
display@2c000 {
compatible = "fsl,diu";
reg = <0x2c000 100>;
interrupts = <72 2>;
interrupt-parent = <&mpic>;
sleep = <&pmc 0x04000000 0>;
};
mpic: interrupt-controller@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x40000 0x40000>;
compatible = "chrp,open-pic";
device_type = "open-pic";
};
msi@41600 {
compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
reg = <0x41600 0x80>;
msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0
0xe4 0
0xe5 0
0xe6 0
0xe7 0>;
interrupt-parent = <&mpic>;
};
global-utilities@e0000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8610-guts";
reg = <0xe0000 0x1000>;
ranges = <0 0xe0000 0x1000>;
fsl,has-rstcr;
pmc: power@70 {
compatible = "fsl,mpc8610-pmc",
"fsl,mpc8641d-pmc";
reg = <0x70 0x20>;
};
};
wdt@e4000 {
compatible = "fsl,mpc8610-wdt";
reg = <0xe4000 0x100>;
};
ssi@16000 {
compatible = "fsl,mpc8610-ssi";
cell-index = <0>;
reg = <0x16000 0x100>;
interrupt-parent = <&mpic>;
interrupts = <62 2>;
fsl,mode = "i2s-slave";
codec-handle = <&cs4270>;
fsl,playback-dma = <&dma00>;
fsl,capture-dma = <&dma01>;
fsl,fifo-depth = <8>;
sleep = <&pmc 0 0x08000000>;
};
ssi@16100 {
compatible = "fsl,mpc8610-ssi";
status = "disabled";
cell-index = <1>;
reg = <0x16100 0x100>;
interrupt-parent = <&mpic>;
interrupts = <63 2>;
fsl,fifo-depth = <8>;
sleep = <&pmc 0 0x04000000>;
};
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
cell-index = <0>;
reg = <0x21300 0x4>; /* DMA general status register */
ranges = <0x0 0x21100 0x200>;
sleep = <&pmc 0x00000400 0>;
dma00: dma-channel@0 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,ssi-dma-channel";
cell-index = <0>;
reg = <0x0 0x80>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma01: dma-channel@1 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,ssi-dma-channel";
cell-index = <1>;
reg = <0x80 0x80>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@2 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <2>;
reg = <0x100 0x80>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@3 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <3>;
reg = <0x180 0x80>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
dma@c300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
cell-index = <1>;
reg = <0xc300 0x4>; /* DMA general status register */
ranges = <0x0 0xc100 0x200>;
sleep = <&pmc 0x00000200 0>;
dma-channel@0 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <0>;
reg = <0x0 0x80>;
interrupt-parent = <&mpic>;
interrupts = <76 2>;
};
dma-channel@1 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <1>;
reg = <0x80 0x80>;
interrupt-parent = <&mpic>;
interrupts = <77 2>;
};
dma-channel@2 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <2>;
reg = <0x100 0x80>;
interrupt-parent = <&mpic>;
interrupts = <78 2>;
};
dma-channel@3 {
compatible = "fsl,mpc8610-dma-channel",
"fsl,eloplus-dma-channel";
cell-index = <3>;
reg = <0x180 0x80>;
interrupt-parent = <&mpic>;
interrupts = <79 2>;
};
};
};
pci0: pci@e0008000 {
compatible = "fsl,mpc8610-pci";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe0008000 0x1000>;
bus-range = <0 0>;
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
sleep = <&pmc 0x80000000 0>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <24 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x11 */
0x8800 0 0 1 &mpic 4 1
0x8800 0 0 2 &mpic 5 1
0x8800 0 0 3 &mpic 6 1
0x8800 0 0 4 &mpic 7 1
/* IDSEL 0x12 */
0x9000 0 0 1 &mpic 5 1
0x9000 0 0 2 &mpic 6 1
0x9000 0 0 3 &mpic 7 1
0x9000 0 0 4 &mpic 4 1
>;
};
pci1: pcie@e000a000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
reg = <0xe000a000 0x1000>;
bus-range = <1 3>;
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
sleep = <&pmc 0x40000000 0>;
clock-frequency = <33333333>;
interrupt-parent = <&mpic>;
interrupts = <26 2>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <
/* IDSEL 0x1b */
0xd800 0 0 1 &mpic 2 1
/* IDSEL 0x1c*/
0xe000 0 0 1 &mpic 1 1
0xe000 0 0 2 &mpic 1 1
0xe000 0 0 3 &mpic 1 1
0xe000 0 0 4 &mpic 1 1
/* IDSEL 0x1f */
0xf800 0 0 1 &mpic 3 2
0xf800 0 0 2 &mpic 0 1
>;
pcie@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
ranges = <0x02000000 0x0 0xa0000000
0x02000000 0x0 0xa0000000
0x0 0x10000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00100000>;
uli1575@0 {
reg = <0 0 0 0 0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x02000000 0x0 0xa0000000
0x02000000 0x0 0xa0000000
0x0 0x10000000
0x01000000 0x0 0x00000000
0x01000000 0x0 0x00000000
0x0 0x00100000>;
isa@1e {
device_type = "isa";
#size-cells = <1>;
#address-cells = <2>;
reg = <0xf000 0 0 0 0>;
ranges = <1 0 0x01000000 0 0
0x00001000>;
rtc@70 {
compatible = "pnpPNP,b00";
reg = <1 0x70 2>;
};
};
};
};
};
pci2: pcie@e0009000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
compatible = "fsl,mpc8641-pcie";
reg = <0xe0009000 0x00001000>;
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
bus-range = <0 255>;
interrupt-map-mask = <0xf800 0 0 7>;
interrupt-map = <0x0000 0 0 1 &mpic 4 1
0x0000 0 0 2 &mpic 5 1
0x0000 0 0 3 &mpic 6 1
0x0000 0 0 4 &mpic 7 1>;
interrupt-parent = <&mpic>;
interrupts = <25 2>;
sleep = <&pmc 0x20000000 0>;
clock-frequency = <33333333>;
};
};

243
arch/powerpc/boot/dts/pq2fads.dts
View File

@ -1,243 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
*
* Copyright 2007,2008 Freescale Semiconductor Inc.
*/
/dts-v1/;
/ {
model = "pq2fads";
compatible = "fsl,pq2fads";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet0;
ethernet1 = &enet1;
serial0 = &serial0;
serial1 = &serial1;
pci0 = &pci0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>;
i-cache-line-size = <32>;
d-cache-size = <16384>;
i-cache-size = <16384>;
timebase-frequency = <0>;
clock-frequency = <0>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0>;
};
localbus@f0010100 {
compatible = "fsl,mpc8280-localbus",
"fsl,pq2-localbus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xf0010100 0x60>;
ranges = <0x0 0x0 0xff800000 0x800000
0x1 0x0 0xf4500000 0x8000
0x8 0x0 0xf8200000 0x8000>;
flash@0,0 {
compatible = "jedec-flash";
reg = <0x0 0x0 0x800000>;
bank-width = <4>;
device-width = <1>;
};
bcsr@1,0 {
reg = <0x1 0x0 0x20>;
compatible = "fsl,pq2fads-bcsr";
};
PCI_PIC: pic@8,0 {
#interrupt-cells = <1>;
interrupt-controller;
reg = <0x8 0x0 0x8>;
compatible = "fsl,pq2ads-pci-pic";
interrupt-parent = <&PIC>;
interrupts = <24 8>;
};
};
pci0: pci@f0010800 {
device_type = "pci";
reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
clock-frequency = <66000000>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
/* IDSEL 0x16 */
0xb000 0x0 0x0 0x1 &PCI_PIC 0
0xb000 0x0 0x0 0x2 &PCI_PIC 1
0xb000 0x0 0x0 0x3 &PCI_PIC 2
0xb000 0x0 0x0 0x4 &PCI_PIC 3
/* IDSEL 0x17 */
0xb800 0x0 0x0 0x1 &PCI_PIC 4
0xb800 0x0 0x0 0x2 &PCI_PIC 5
0xb800 0x0 0x0 0x3 &PCI_PIC 6
0xb800 0x0 0x0 0x4 &PCI_PIC 7
/* IDSEL 0x18 */
0xc000 0x0 0x0 0x1 &PCI_PIC 8
0xc000 0x0 0x0 0x2 &PCI_PIC 9
0xc000 0x0 0x0 0x3 &PCI_PIC 10
0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
interrupt-parent = <&PIC>;
interrupts = <18 8>;
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
};
soc@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8280", "fsl,pq2-soc";
ranges = <0x0 0xf0000000 0x53000>;
// Temporary -- will go away once kernel uses ranges for get_immrbase().
reg = <0xf0000000 0x53000>;
cpm@119c0 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
reg = <0x119c0 0x30>;
ranges;
muram@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x10000>;
data@0 {
compatible = "fsl,cpm-muram-data";
reg = <0x0 0x2000 0x9800 0x800>;
};
};
brg@119f0 {
compatible = "fsl,mpc8280-brg",
"fsl,cpm2-brg",
"fsl,cpm-brg";
reg = <0x119f0 0x10 0x115f0 0x10>;
};
serial0: serial@11a00 {
device_type = "serial";
compatible = "fsl,mpc8280-scc-uart",
"fsl,cpm2-scc-uart";
reg = <0x11a00 0x20 0x8000 0x100>;
interrupts = <40 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <1>;
fsl,cpm-command = <0x800000>;
};
serial1: serial@11a20 {
device_type = "serial";
compatible = "fsl,mpc8280-scc-uart",
"fsl,cpm2-scc-uart";
reg = <0x11a20 0x20 0x8100 0x100>;
interrupts = <41 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <2>;
fsl,cpm-command = <0x4a00000>;
};
enet0: ethernet@11320 {
device_type = "network";
compatible = "fsl,mpc8280-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
interrupts = <33 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY0>;
linux,network-index = <0>;
fsl,cpm-command = <0x16200300>;
};
enet1: ethernet@11340 {
device_type = "network";
compatible = "fsl,mpc8280-fcc-enet",
"fsl,cpm2-fcc-enet";
reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
interrupts = <34 8>;
interrupt-parent = <&PIC>;
phy-handle = <&PHY1>;
linux,network-index = <1>;
fsl,cpm-command = <0x1a400300>;
local-mac-address = [00 e0 0c 00 79 01];
};
mdio@10d40 {
compatible = "fsl,pq2fads-mdio-bitbang",
"fsl,mpc8280-mdio-bitbang",
"fsl,cpm2-mdio-bitbang";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10d40 0x14>;
fsl,mdio-pin = <9>;
fsl,mdc-pin = <10>;
PHY0: ethernet-phy@0 {
interrupt-parent = <&PIC>;
interrupts = <25 2>;
reg = <0x0>;
};
PHY1: ethernet-phy@1 {
interrupt-parent = <&PIC>;
interrupts = <25 2>;
reg = <0x3>;
};
};
usb@11b60 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc8280-usb",
"fsl,cpm2-usb";
reg = <0x11b60 0x18 0x8b00 0x100>;
interrupt-parent = <&PIC>;
interrupts = <11 8>;
fsl,cpm-command = <0x2e600000>;
};
};
PIC: interrupt-controller@10c00 {
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x10c00 0x80>;
compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
};
};
chosen {
stdout-path = "/soc/cpm/serial@11a00";
};
};

2
arch/powerpc/boot/dts/turris1x.dts
View File

@ -15,7 +15,7 @@
/ {
model = "Turris 1.x";
compatible = "cznic,turris1x", "fsl,P2020RDB-PC"; /* fsl,P2020RDB-PC is required for booting Linux */
compatible = "cznic,turris1x";
aliases {
ethernet0 = &enet0;

59
arch/powerpc/configs/83xx/mpc832x_mds_defconfig
View File

@ -1,59 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_MSDOS_PARTITION is not set
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_83xx=y
CONFIG_MPC832x_MDS=y
CONFIG_MATH_EMULATION=y
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
# CONFIG_IPV6 is not set
# CONFIG_FW_LOADER is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_SCSI=y
CONFIG_NETDEVICES=y
CONFIG_UCC_GETH=y
CONFIG_DAVICOM_PHY=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_WATCHDOG=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1374=y
CONFIG_QUICC_ENGINE=y
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m

58
arch/powerpc/configs/83xx/mpc834x_mds_defconfig
View File

@ -1,58 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_MSDOS_PARTITION is not set
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_83xx=y
CONFIG_MPC834x_MDS=y
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
# CONFIG_IPV6 is not set
# CONFIG_FW_LOADER is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_NETDEVICES=y
CONFIG_GIANFAR=y
CONFIG_E100=y
CONFIG_MARVELL_PHY=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_WATCHDOG=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1374=y
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m

64
arch/powerpc/configs/83xx/mpc836x_mds_defconfig
View File

@ -1,64 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_KALLSYMS is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_MSDOS_PARTITION is not set
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_83xx=y
CONFIG_MPC836x_MDS=y
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
# CONFIG_IPV6 is not set
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_SCSI=y
CONFIG_NETDEVICES=y
CONFIG_UCC_GETH=y
CONFIG_MARVELL_PHY=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_WATCHDOG=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1374=y
CONFIG_QUICC_ENGINE=y
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m

58
arch/powerpc/configs/83xx/mpc837x_mds_defconfig
View File

@ -1,58 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_83xx=y
CONFIG_MPC837x_MDS=y
CONFIG_GEN_RTC=y
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
# CONFIG_IPV6 is not set
# CONFIG_FW_LOADER is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=32768
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_ATA=y
CONFIG_SATA_FSL=y
CONFIG_NETDEVICES=y
CONFIG_GIANFAR=y
CONFIG_MARVELL_PHY=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MPC=y
CONFIG_WATCHDOG=y
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_CRC_T10DIF=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m

1
arch/powerpc/configs/corenet_base.config
View File

@ -1 +1,2 @@
CONFIG_CORENET_GENERIC=y
CONFIG_PPC_QEMU_E500=y

2
arch/powerpc/configs/guest.config
View File

@ -10,3 +10,5 @@ CONFIG_EPAPR_PARAVIRT=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VHOST_NET=y
CONFIG_VHOST=y
CONFIG_IBMVETH=y
CONFIG_IBMVNIC=y

1
arch/powerpc/configs/kvm_guest.config Symbolic link
View File

@ -0,0 +1 @@
../../../kernel/configs/kvm_guest.config

54
arch/powerpc/configs/mpc7448_hpc2_defconfig
View File

@ -1,54 +0,0 @@
CONFIG_ALTIVEC=y
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_EMBEDDED6xx=y
CONFIG_MPC7448HPC2=y
CONFIG_GEN_RTC=y
CONFIG_BINFMT_MISC=y
# CONFIG_SECCOMP is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
# CONFIG_IPV6 is not set
# CONFIG_FW_LOADER is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_SATA_MV=y
CONFIG_NETDEVICES=y
CONFIG_E100=y
CONFIG_8139TOO=y
# CONFIG_8139TOO_PIO is not set
CONFIG_TSI108_ETH=y
CONFIG_PHYLIB=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_CRC_T10DIF=y

79
arch/powerpc/configs/mpc8272_ads_defconfig
View File

@ -1,79 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_82xx=y
CONFIG_MPC8272_ADS=y
CONFIG_BINFMT_MISC=y
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
CONFIG_NETFILTER=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
# CONFIG_MTD_CFI_I1 is not set
# CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_CFI_I4=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_NETDEVICES=y
CONFIG_TUN=y
CONFIG_FS_ENET=y
# CONFIG_FS_ENET_HAS_SCC is not set
CONFIG_FS_ENET_MDIO_FCC=y
CONFIG_DAVICOM_PHY=y
CONFIG_PPP=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
CONFIG_INPUT_EVDEV=y
# CONFIG_VT is not set
CONFIG_SERIAL_CPM=y
CONFIG_SERIAL_CPM_CONSOLE=y
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_ROOT_NFS=y
CONFIG_NLS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_BDI_SWITCH=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_HW is not set

4
arch/powerpc/configs/mpc83xx_defconfig
View File

@ -11,13 +11,9 @@ CONFIG_PARTITION_ADVANCED=y
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_83xx=y
CONFIG_MPC831x_RDB=y
CONFIG_MPC832x_MDS=y
CONFIG_MPC832x_RDB=y
CONFIG_MPC834x_MDS=y
CONFIG_MPC834x_ITX=y
CONFIG_MPC836x_MDS=y
CONFIG_MPC836x_RDK=y
CONFIG_MPC837x_MDS=y
CONFIG_MPC837x_RDB=y
CONFIG_ASP834x=y
CONFIG_QE_GPIO=y

2
arch/powerpc/configs/mpc86xx_base.config
View File

@ -1,6 +1,4 @@
CONFIG_PPC_86xx=y
CONFIG_MPC8641_HPCN=y
CONFIG_MPC8610_HPCD=y
CONFIG_GEF_PPC9A=y
CONFIG_GEF_SBC310=y
CONFIG_GEF_SBC610=y

1
arch/powerpc/configs/powernv_defconfig
View File

@ -170,6 +170,7 @@ CONFIG_S2IO=m
CONFIG_E100=y
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_IGB=y
CONFIG_IXGBE=m
CONFIG_I40E=m
CONFIG_MLX4_EN=m

183
arch/powerpc/configs/ppc64_defconfig
View File

@ -1,35 +1,48 @@
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
CONFIG_AUDIT=y
CONFIG_NO_HZ_FULL=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_BPF_SYSCALL=y
CONFIG_BPF_JIT=y
CONFIG_BPF_LSM=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_PSI=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=13
CONFIG_NUMA_BALANCING=y
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_CGROUP_SCHED=y
CONFIG_BLK_CGROUP=y
CONFIG_CFS_BANDWIDTH=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CGROUP_HUGETLB=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_CGROUP_MISC=y
CONFIG_USER_NS=y
CONFIG_CHECKPOINT_RESTORE=y
CONFIG_SCHED_AUTOGROUP=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_BPF_SYSCALL=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
CONFIG_PPC64=y
CONFIG_NR_CPUS=2048
CONFIG_PPC_SPLPAR=y
CONFIG_DTL=y
CONFIG_PPC_SMLPAR=y
CONFIG_IBMEBUS=y
CONFIG_PAPR_SCM=m
CONFIG_PPC_SVM=y
CONFIG_PPC_MAPLE=y
CONFIG_PPC_PASEMI=y
@ -54,27 +67,32 @@ CONFIG_CRASH_DUMP=y
CONFIG_FA_DUMP=y
CONFIG_IRQ_ALL_CPUS=y
CONFIG_SCHED_SMT=y
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_RPA=m
CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
CONFIG_PCCARD=y
CONFIG_ELECTRA_CF=y
CONFIG_PPC_SECURE_BOOT=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM_BOOK3S_64=m
CONFIG_KVM_BOOK3S_64_HV=m
CONFIG_VHOST_NET=m
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_MODULE_SIG_SHA512=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BINFMT_MISC=m
CONFIG_ZSWAP=y
CONFIG_Z3FOLD=y
CONFIG_ZSMALLOC=y
# CONFIG_SLAB_MERGE_DEFAULT is not set
CONFIG_SLAB_FREELIST_RANDOM=y
CONFIG_SLAB_FREELIST_HARDENED=y
CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
# CONFIG_COMPAT_BRK is not set
CONFIG_MEMORY_HOTPLUG=y
CONFIG_MEMORY_HOTREMOVE=y
CONFIG_KSM=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_ZONE_DEVICE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@ -90,23 +108,29 @@ CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_IPV6=y
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_NET_SCHED=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_BPF=m
CONFIG_BPF_JIT=y
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_RPA=m
CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
CONFIG_PCCARD=y
CONFIG_ELECTRA_CF=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_BLK_DEV_FD=y
CONFIG_ZRAM=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_VIRTIO_BLK=m
CONFIG_BLK_DEV_NVME=m
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=m
CONFIG_BLK_DEV_SR=y
@ -143,18 +167,30 @@ CONFIG_BLK_DEV_MD=y
CONFIG_MD_LINEAR=y
CONFIG_MD_RAID0=y
CONFIG_MD_RAID1=y
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_BLK_DEV_DM=y
CONFIG_DM_UNSTRIPED=m
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_CACHE=m
CONFIG_DM_WRITECACHE=m
CONFIG_DM_EBS=m
CONFIG_DM_ERA=m
CONFIG_DM_CLONE=m
CONFIG_DM_MIRROR=m
CONFIG_DM_LOG_USERSPACE=m
CONFIG_DM_RAID=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
CONFIG_DM_MULTIPATH_HST=m
CONFIG_DM_MULTIPATH_IOA=m
CONFIG_DM_DELAY=m
CONFIG_DM_DUST=m
CONFIG_DM_INIT=y
CONFIG_DM_UEVENT=y
CONFIG_ADB_PMU=y
CONFIG_PMAC_SMU=y
@ -266,9 +302,9 @@ CONFIG_LEDS_POWERNV=m
CONFIG_INFINIBAND=m
CONFIG_INFINIBAND_USER_MAD=m
CONFIG_INFINIBAND_USER_ACCESS=m
CONFIG_INFINIBAND_MTHCA=m
CONFIG_INFINIBAND_CXGB4=m
CONFIG_MLX4_INFINIBAND=m
CONFIG_INFINIBAND_MTHCA=m
CONFIG_INFINIBAND_IPOIB=m
CONFIG_INFINIBAND_IPOIB_CM=y
CONFIG_INFINIBAND_SRP=m
@ -279,22 +315,12 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_BALLOON=m
CONFIG_LIBNVDIMM=y
CONFIG_VHOST_NET=m
CONFIG_RAS=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_LIBNVDIMM=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_REISERFS_FS=m
CONFIG_REISERFS_FS_XATTR=y
CONFIG_REISERFS_FS_POSIX_ACL=y
CONFIG_REISERFS_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
CONFIG_XFS_FS=y
CONFIG_XFS_POSIX_ACL=y
CONFIG_BTRFS_FS=m
@ -319,6 +345,7 @@ CONFIG_SQUASHFS=m
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_PSTORE=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
@ -334,42 +361,110 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_YAMA=y
CONFIG_SECURITY_LOCKDOWN_LSM=y
CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
CONFIG_SECURITY_LANDLOCK=y
CONFIG_INTEGRITY_SIGNATURE=y
CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
CONFIG_INTEGRITY_PLATFORM_KEYRING=y
CONFIG_IMA=y
CONFIG_IMA_KEXEC=y
CONFIG_IMA_DEFAULT_HASH_SHA256=y
CONFIG_IMA_WRITE_POLICY=y
CONFIG_IMA_APPRAISE=y
CONFIG_IMA_ARCH_POLICY=y
CONFIG_IMA_APPRAISE_MODSIG=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_CRC32C_VPMSUM=m
CONFIG_CRYPTO_MD5_PPC=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA1_PPC=m
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_LZO=m
CONFIG_CRYPTO_CRC32C_VPMSUM=m
CONFIG_CRYPTO_MD5_PPC=m
CONFIG_CRYPTO_SHA1_PPC=m
CONFIG_CRYPTO_DEV_NX=y
CONFIG_CRYPTO_DEV_NX_ENCRYPT=m
CONFIG_CRYPTO_DEV_VMX=y
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYSTEM_BLACKLIST_KEYRING=y
CONFIG_PRINTK_TIME=y
CONFIG_PRINTK_CALLER=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_PAGE_OWNER=y
CONFIG_PAGE_POISONING=y
CONFIG_DEBUG_RODATA_TEST=y
CONFIG_DEBUG_WX=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_VM=y
# CONFIG_DEBUG_VM_PGTABLE is not set
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_SCHEDSTATS=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_FUNCTION_TRACER=y
CONFIG_FTRACE_SYSCALLS=y
CONFIG_SCHED_TRACER=y
CONFIG_LOCK_TORTURE_TEST=m
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_STACK_TRACER=y
CONFIG_SCHED_TRACER=y
CONFIG_FTRACE_SYSCALLS=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_IO_STRICT_DEVMEM=y
CONFIG_PPC_EMULATED_STATS=y
CONFIG_CODE_PATCHING_SELFTEST=y
CONFIG_FTR_FIXUP_SELFTEST=y
CONFIG_MSI_BITMAP_SELFTEST=y
CONFIG_XMON=y
CONFIG_BOOTX_TEXT=y
CONFIG_KUNIT=m
CONFIG_KUNIT_ALL_TESTS=m
CONFIG_LKDTM=m
CONFIG_TEST_MIN_HEAP=m
CONFIG_TEST_DIV64=m
CONFIG_BACKTRACE_SELF_TEST=m
CONFIG_TEST_REF_TRACKER=m
CONFIG_RBTREE_TEST=m
CONFIG_REED_SOLOMON_TEST=m
CONFIG_INTERVAL_TREE_TEST=m
CONFIG_PERCPU_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
CONFIG_TEST_BITMAP=m
CONFIG_TEST_UUID=m
CONFIG_TEST_XARRAY=m
CONFIG_TEST_MAPLE_TREE=m
CONFIG_TEST_RHASHTABLE=m
CONFIG_TEST_IDA=m
CONFIG_TEST_BITOPS=m
CONFIG_TEST_VMALLOC=m
CONFIG_TEST_USER_COPY=m
CONFIG_TEST_BPF=m
CONFIG_TEST_BLACKHOLE_DEV=m
CONFIG_FIND_BIT_BENCHMARK=m
CONFIG_TEST_FIRMWARE=m
CONFIG_TEST_SYSCTL=m
CONFIG_LINEAR_RANGES_TEST=m
CONFIG_TEST_UDELAY=m
CONFIG_TEST_STATIC_KEYS=m
CONFIG_TEST_KMOD=m
CONFIG_TEST_MEMCAT_P=m
CONFIG_TEST_MEMINIT=m
CONFIG_TEST_FREE_PAGES=m
CONFIG_MEMTEST=y

8
arch/powerpc/configs/ppc6xx_defconfig
View File

@ -38,24 +38,16 @@ CONFIG_PPC_MPC52xx=y
CONFIG_PPC_EFIKA=y
CONFIG_PPC_MPC5200_BUGFIX=y
CONFIG_PPC_82xx=y
CONFIG_MPC8272_ADS=y
CONFIG_PQ2FADS=y
CONFIG_EP8248E=y
CONFIG_MGCOGE=y
CONFIG_PPC_83xx=y
CONFIG_MPC831x_RDB=y
CONFIG_MPC832x_MDS=y
CONFIG_MPC832x_RDB=y
CONFIG_MPC834x_MDS=y
CONFIG_MPC834x_ITX=y
CONFIG_MPC836x_MDS=y
CONFIG_MPC836x_RDK=y
CONFIG_MPC837x_MDS=y
CONFIG_MPC837x_RDB=y
CONFIG_ASP834x=y
CONFIG_PPC_86xx=y
CONFIG_MPC8641_HPCN=y
CONFIG_MPC8610_HPCD=y
CONFIG_GEF_SBC610=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_STAT=y

80
arch/powerpc/configs/pq2fads_defconfig
View File

@ -1,80 +0,0 @@
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_KALLSYMS_ALL=y
CONFIG_PARTITION_ADVANCED=y
# CONFIG_PPC_CHRP is not set
# CONFIG_PPC_PMAC is not set
CONFIG_PPC_82xx=y
CONFIG_PQ2FADS=y
CONFIG_BINFMT_MISC=y
CONFIG_PCI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_SYN_COOKIES=y
CONFIG_NETFILTER=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
# CONFIG_MTD_CFI_I1 is not set
# CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_CFI_I4=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_NETDEVICES=y
CONFIG_TUN=y
CONFIG_FS_ENET=y
# CONFIG_FS_ENET_HAS_SCC is not set
CONFIG_FS_ENET_MDIO_FCC=y
CONFIG_DAVICOM_PHY=y
CONFIG_PPP=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_SYNC_TTY=y
CONFIG_INPUT_EVDEV=y
# CONFIG_VT is not set
CONFIG_SERIAL_CPM=y
CONFIG_SERIAL_CPM_CONSOLE=y
# CONFIG_HWMON is not set
CONFIG_USB_GADGET=y
CONFIG_USB_ETH=y
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_SCHED_DEBUG is not set
CONFIG_BDI_SWITCH=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DES=y

322
arch/powerpc/configs/pseries_defconfig
View File

@ -1,322 +0,0 @@
CONFIG_PPC64=y
CONFIG_NR_CPUS=2048
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_AUDIT=y
# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=18
CONFIG_LOG_CPU_MAX_BUF_SHIFT=13
CONFIG_NUMA_BALANCING=y
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_CGROUP_SCHED=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_CGROUP_PERF=y
CONFIG_CGROUP_BPF=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_BPF_SYSCALL=y
# CONFIG_COMPAT_BRK is not set
CONFIG_PROFILING=y
CONFIG_KPROBES=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_PPC_SPLPAR=y
CONFIG_DTL=y
CONFIG_PPC_SMLPAR=y
CONFIG_IBMEBUS=y
CONFIG_LIBNVDIMM=m
CONFIG_PAPR_SCM=m
CONFIG_PPC_SVM=y
# CONFIG_PPC_PMAC is not set
CONFIG_RTAS_FLASH=m
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_HZ_100=y
CONFIG_BINFMT_MISC=m
CONFIG_PPC_TRANSACTIONAL_MEM=y
CONFIG_KEXEC=y
CONFIG_KEXEC_FILE=y
CONFIG_IRQ_ALL_CPUS=y
CONFIG_MEMORY_HOTPLUG=y
CONFIG_MEMORY_HOTREMOVE=y
CONFIG_KSM=y
CONFIG_TRANSPARENT_HUGEPAGE=y
CONFIG_SCHED_SMT=y
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_RPA=m
CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_NET_KEY=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_NET_IPIP=y
CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_NET_SCHED=y
CONFIG_NET_CLS_BPF=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_BPF=m
CONFIG_BPF_JIT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_PARPORT=m
CONFIG_PARPORT_PC=m
CONFIG_BLK_DEV_FD=m
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_VIRTIO_BLK=m
CONFIG_BLK_DEV_NVME=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=m
CONFIG_BLK_DEV_SR=y
CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_FC_ATTRS=y
CONFIG_SCSI_CXGB3_ISCSI=m
CONFIG_SCSI_CXGB4_ISCSI=m
CONFIG_SCSI_BNX2_ISCSI=m
CONFIG_BE2ISCSI=m
CONFIG_SCSI_MPT2SAS=m
CONFIG_SCSI_IBMVSCSI=y
CONFIG_SCSI_IBMVFC=m
CONFIG_SCSI_SYM53C8XX_2=m
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
CONFIG_SCSI_IPR=y
CONFIG_SCSI_QLA_FC=m
CONFIG_SCSI_QLA_ISCSI=m
CONFIG_SCSI_LPFC=m
CONFIG_SCSI_VIRTIO=m
CONFIG_SCSI_DH=y
CONFIG_SCSI_DH_RDAC=m
CONFIG_SCSI_DH_ALUA=m
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_PATA_AMD=y
CONFIG_ATA_GENERIC=y
CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_LINEAR=y
CONFIG_MD_RAID0=y
CONFIG_MD_RAID1=y
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_THIN_PROVISIONING=m
CONFIG_DM_MIRROR=m
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
CONFIG_DM_MULTIPATH_QL=m
CONFIG_DM_MULTIPATH_ST=m
CONFIG_DM_UEVENT=y
CONFIG_BONDING=m
CONFIG_DUMMY=m
CONFIG_MACVLAN=m
CONFIG_MACVTAP=m
CONFIG_VXLAN=m
CONFIG_NETCONSOLE=y
CONFIG_TUN=m
CONFIG_VETH=m
CONFIG_VIRTIO_NET=m
CONFIG_VORTEX=m
CONFIG_ACENIC=m
CONFIG_ACENIC_OMIT_TIGON_I=y
CONFIG_PCNET32=m
CONFIG_TIGON3=y
CONFIG_BNX2X=m
CONFIG_CHELSIO_T1=m
CONFIG_BE2NET=m
CONFIG_S2IO=m
CONFIG_IBMVETH=y
CONFIG_EHEA=y
CONFIG_IBMVNIC=y
CONFIG_E100=y
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_IXGBE=m
CONFIG_I40E=m
CONFIG_MLX4_EN=m
CONFIG_MYRI10GE=m
CONFIG_NETXEN_NIC=m
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPPOE=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_MISC=y
CONFIG_INPUT_PCSPKR=m
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_ICOM=m
CONFIG_SERIAL_JSM=m
CONFIG_HVC_CONSOLE=y
CONFIG_HVC_RTAS=y
CONFIG_HVCS=m
CONFIG_VIRTIO_CONSOLE=m
CONFIG_IBM_BSR=m
CONFIG_I2C_CHARDEV=y
CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_OF=y
CONFIG_FB_MATROX=y
CONFIG_FB_MATROX_MILLENIUM=y
CONFIG_FB_MATROX_MYSTIQUE=y
CONFIG_FB_MATROX_G=y
CONFIG_FB_RADEON=y
CONFIG_FB_IBM_GXT4500=y
CONFIG_LCD_PLATFORM=m
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_HID_GYRATION=y
CONFIG_HID_PANTHERLORD=y
CONFIG_HID_PETALYNX=y
CONFIG_HID_SAMSUNG=y
CONFIG_HID_SUNPLUS=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_MON=m
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_STORAGE=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_POWERNV=m
CONFIG_INFINIBAND=m
CONFIG_INFINIBAND_USER_MAD=m
CONFIG_INFINIBAND_USER_ACCESS=m
CONFIG_INFINIBAND_MTHCA=m
CONFIG_INFINIBAND_CXGB4=m
CONFIG_MLX4_INFINIBAND=m
CONFIG_INFINIBAND_IPOIB=m
CONFIG_INFINIBAND_IPOIB_CM=y
CONFIG_INFINIBAND_SRP=m
CONFIG_INFINIBAND_ISER=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_GENERIC=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_BALLOON=m
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_JFS_FS=m
CONFIG_JFS_POSIX_ACL=y
CONFIG_JFS_SECURITY=y
CONFIG_XFS_FS=m
CONFIG_XFS_POSIX_ACL=y
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
CONFIG_NILFS2_FS=m
CONFIG_FS_DAX=y
CONFIG_AUTOFS4_FS=m
CONFIG_FUSE_FS=m
CONFIG_OVERLAY_FS=m
CONFIG_ISO9660_FS=y
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=m
CONFIG_PROC_KCORE=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_HUGETLBFS=y
CONFIG_CRAMFS=m
CONFIG_SQUASHFS=m
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_PSTORE=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFSD=m
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_CIFS=m
CONFIG_CIFS_XATTR=y
CONFIG_CIFS_POSIX=y
CONFIG_NLS_DEFAULT="utf8"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_STACK_USAGE=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_HARDLOCKUP_DETECTOR=y
CONFIG_FUNCTION_TRACER=y
CONFIG_FTRACE_SYSCALLS=y
CONFIG_SCHED_TRACER=y
CONFIG_STACK_TRACER=y
CONFIG_BLK_DEV_IO_TRACE=y
CONFIG_CODE_PATCHING_SELFTEST=y
CONFIG_FTR_FIXUP_SELFTEST=y
CONFIG_MSI_BITMAP_SELFTEST=y
CONFIG_XMON=y
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_CRC32C_VPMSUM=m
CONFIG_CRYPTO_MD5_PPC=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA1_PPC=m
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_LZO=m
CONFIG_CRYPTO_DEV_NX=y
CONFIG_CRYPTO_DEV_NX_ENCRYPT=m
CONFIG_CRYPTO_DEV_VMX=y
CONFIG_VIRTUALIZATION=y
CONFIG_KVM_BOOK3S_64=m
CONFIG_KVM_BOOK3S_64_HV=m
CONFIG_VHOST_NET=m
CONFIG_PRINTK_TIME=y
CONFIG_PRINTK_CALLER=y

53
arch/powerpc/include/asm/atomic.h
View File

@ -27,14 +27,22 @@ static __inline__ int arch_atomic_read(const atomic_t *v)
{
int t;
__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
/* -mprefixed can generate offsets beyond range, fall back hack */
if (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED))
__asm__ __volatile__("lwz %0,0(%1)" : "=r"(t) : "b"(&v->counter));
else
__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
return t;
}
static __inline__ void arch_atomic_set(atomic_t *v, int i)
{
__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
/* -mprefixed can generate offsets beyond range, fall back hack */
if (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED))
__asm__ __volatile__("stw %1,0(%2)" : "=m"(v->counter) : "r"(i), "b"(&v->counter));
else
__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
}
#define ATOMIC_OP(op, asm_op, suffix, sign, ...) \
@ -130,35 +138,6 @@ ATOMIC_OPS(xor, xor, "", K)
#define arch_atomic_xchg_relaxed(v, new) \
arch_xchg_relaxed(&((v)->counter), (new))
/*
* Don't want to override the generic atomic_try_cmpxchg_acquire, because
* we add a lock hint to the lwarx, which may not be wanted for the
* _acquire case (and is not used by the other _acquire variants so it
* would be a surprise).
*/
static __always_inline bool
arch_atomic_try_cmpxchg_lock(atomic_t *v, int *old, int new)
{
int r, o = *old;
unsigned int eh = IS_ENABLED(CONFIG_PPC64);
__asm__ __volatile__ (
"1: lwarx %0,0,%2,%[eh] # atomic_try_cmpxchg_acquire \n"
" cmpw 0,%0,%3 \n"
" bne- 2f \n"
" stwcx. %4,0,%2 \n"
" bne- 1b \n"
"\t" PPC_ACQUIRE_BARRIER " \n"
"2: \n"
: "=&r" (r), "+m" (v->counter)
: "r" (&v->counter), "r" (o), "r" (new), [eh] "n" (eh)
: "cr0", "memory");
if (unlikely(r != o))
*old = r;
return likely(r == o);
}
/**
* atomic_fetch_add_unless - add unless the number is a given value
* @v: pointer of type atomic_t
@ -226,14 +205,22 @@ static __inline__ s64 arch_atomic64_read(const atomic64_t *v)
{
s64 t;
__asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
/* -mprefixed can generate offsets beyond range, fall back hack */
if (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED))
__asm__ __volatile__("ld %0,0(%1)" : "=r"(t) : "b"(&v->counter));
else
__asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
return t;
}
static __inline__ void arch_atomic64_set(atomic64_t *v, s64 i)
{
__asm__ __volatile__("std%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
/* -mprefixed can generate offsets beyond range, fall back hack */
if (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED))
__asm__ __volatile__("std %1,0(%2)" : "=m"(v->counter) : "r"(i), "b"(&v->counter));
else
__asm__ __volatile__("std%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
}
#define ATOMIC64_OP(op, asm_op) \

4
arch/powerpc/include/asm/firmware.h
View File

@ -56,6 +56,7 @@
#define FW_FEATURE_FORM2_AFFINITY ASM_CONST(0x0000020000000000)
#define FW_FEATURE_ENERGY_SCALE_INFO ASM_CONST(0x0000040000000000)
#define FW_FEATURE_WATCHDOG ASM_CONST(0x0000080000000000)
#define FW_FEATURE_PLPKS ASM_CONST(0x0000100000000000)
#ifndef __ASSEMBLY__
@ -77,7 +78,8 @@ enum {
FW_FEATURE_DRC_INFO | FW_FEATURE_BLOCK_REMOVE |
FW_FEATURE_PAPR_SCM | FW_FEATURE_ULTRAVISOR |
FW_FEATURE_RPT_INVALIDATE | FW_FEATURE_FORM2_AFFINITY |
FW_FEATURE_ENERGY_SCALE_INFO | FW_FEATURE_WATCHDOG,
FW_FEATURE_ENERGY_SCALE_INFO | FW_FEATURE_WATCHDOG |
FW_FEATURE_PLPKS,
FW_FEATURE_PSERIES_ALWAYS = 0,
FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_ULTRAVISOR,
FW_FEATURE_POWERNV_ALWAYS = 0,

12
arch/powerpc/include/asm/idle.h
View File

@ -9,17 +9,17 @@ DECLARE_PER_CPU(u64, idle_spurr_cycles);
DECLARE_PER_CPU(u64, idle_entry_purr_snap);
DECLARE_PER_CPU(u64, idle_entry_spurr_snap);
static inline void snapshot_purr_idle_entry(void)
static __always_inline void snapshot_purr_idle_entry(void)
{
*this_cpu_ptr(&idle_entry_purr_snap) = mfspr(SPRN_PURR);
}
static inline void snapshot_spurr_idle_entry(void)
static __always_inline void snapshot_spurr_idle_entry(void)
{
*this_cpu_ptr(&idle_entry_spurr_snap) = mfspr(SPRN_SPURR);
}
static inline void update_idle_purr_accounting(void)
static __always_inline void update_idle_purr_accounting(void)
{
u64 wait_cycles;
u64 in_purr = *this_cpu_ptr(&idle_entry_purr_snap);
@ -29,7 +29,7 @@ static inline void update_idle_purr_accounting(void)
get_lppaca()->wait_state_cycles = cpu_to_be64(wait_cycles);
}
static inline void update_idle_spurr_accounting(void)
static __always_inline void update_idle_spurr_accounting(void)
{
u64 *idle_spurr_cycles_ptr = this_cpu_ptr(&idle_spurr_cycles);
u64 in_spurr = *this_cpu_ptr(&idle_entry_spurr_snap);
@ -37,7 +37,7 @@ static inline void update_idle_spurr_accounting(void)
*idle_spurr_cycles_ptr += mfspr(SPRN_SPURR) - in_spurr;
}
static inline void pseries_idle_prolog(void)
static __always_inline void pseries_idle_prolog(void)
{
ppc64_runlatch_off();
snapshot_purr_idle_entry();
@ -49,7 +49,7 @@ static inline void pseries_idle_prolog(void)
get_lppaca()->idle = 1;
}
static inline void pseries_idle_epilog(void)
static __always_inline void pseries_idle_epilog(void)
{
update_idle_purr_accounting();
update_idle_spurr_accounting();

37
arch/powerpc/include/asm/io.h
View File

@ -97,6 +97,42 @@ extern bool isa_io_special;
*
*/
/* -mprefixed can generate offsets beyond range, fall back hack */
#ifdef CONFIG_PPC_KERNEL_PREFIXED
#define DEF_MMIO_IN_X(name, size, insn) \
static inline u##size name(const volatile u##size __iomem *addr) \
{ \
u##size ret; \
__asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
: "=r" (ret) : "r" (addr) : "memory"); \
return ret; \
}
#define DEF_MMIO_OUT_X(name, size, insn) \
static inline void name(volatile u##size __iomem *addr, u##size val) \
{ \
__asm__ __volatile__("sync;"#insn" %1,0,%0" \
: : "r" (addr), "r" (val) : "memory"); \
mmiowb_set_pending(); \
}
#define DEF_MMIO_IN_D(name, size, insn) \
static inline u##size name(const volatile u##size __iomem *addr) \
{ \
u##size ret; \
__asm__ __volatile__("sync;"#insn" %0,0(%1);twi 0,%0,0;isync"\
: "=r" (ret) : "b" (addr) : "memory"); \
return ret; \
}
#define DEF_MMIO_OUT_D(name, size, insn) \
static inline void name(volatile u##size __iomem *addr, u##size val) \
{ \
__asm__ __volatile__("sync;"#insn" %1,0(%0)" \
: : "b" (addr), "r" (val) : "memory"); \
mmiowb_set_pending(); \
}
#else
#define DEF_MMIO_IN_X(name, size, insn) \
static inline u##size name(const volatile u##size __iomem *addr) \
{ \
@ -130,6 +166,7 @@ static inline void name(volatile u##size __iomem *addr, u##size val) \
: "=m<>" (*addr) : "r" (val) : "memory"); \
mmiowb_set_pending(); \
}
#endif
DEF_MMIO_IN_D(in_8, 8, lbz);
DEF_MMIO_OUT_D(out_8, 8, stb);

6
arch/powerpc/include/asm/iommu.h
View File

@ -175,7 +175,7 @@ struct iommu_table_group_ops {
long (*unset_window)(struct iommu_table_group *table_group,
int num);
/* Switch ownership from platform code to external user (e.g. VFIO) */
void (*take_ownership)(struct iommu_table_group *table_group);
long (*take_ownership)(struct iommu_table_group *table_group);
/* Switch ownership from external user (e.g. VFIO) back to core */
void (*release_ownership)(struct iommu_table_group *table_group);
};
@ -215,6 +215,8 @@ extern long iommu_tce_xchg_no_kill(struct mm_struct *mm,
enum dma_data_direction *direction);
extern void iommu_tce_kill(struct iommu_table *tbl,
unsigned long entry, unsigned long pages);
extern struct iommu_table_group_ops spapr_tce_table_group_ops;
#else
static inline void iommu_register_group(struct iommu_table_group *table_group,
int pci_domain_number,
@ -303,8 +305,6 @@ extern int iommu_tce_check_gpa(unsigned long page_shift,
iommu_tce_check_gpa((tbl)->it_page_shift, (gpa)))
extern void iommu_flush_tce(struct iommu_table *tbl);
extern int iommu_take_ownership(struct iommu_table *tbl);
extern void iommu_release_ownership(struct iommu_table *tbl);
extern enum dma_data_direction iommu_tce_direction(unsigned long tce);
extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir);

4
arch/powerpc/include/asm/kvm_host.h
View File

@ -758,7 +758,7 @@ struct kvm_vcpu_arch {
u8 prodded;
u8 doorbell_request;
u8 irq_pending; /* Used by XIVE to signal pending guest irqs */
u32 last_inst;
unsigned long last_inst;
struct rcuwait wait;
struct rcuwait *waitp;
@ -818,7 +818,7 @@ struct kvm_vcpu_arch {
u64 busy_stolen;
u64 busy_preempt;
u32 emul_inst;
u64 emul_inst;
u32 online;

64
arch/powerpc/include/asm/kvm_ppc.h
View File

@ -28,6 +28,7 @@
#include <asm/xive.h>
#include <asm/cpu_has_feature.h>
#endif
#include <asm/inst.h>
/*
* KVMPPC_INST_SW_BREAKPOINT is debug Instruction
@ -84,7 +85,8 @@ extern int kvmppc_handle_vsx_store(struct kvm_vcpu *vcpu,
int is_default_endian);
extern int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
enum instruction_fetch_type type, u32 *inst);
enum instruction_fetch_type type,
unsigned long *inst);
extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr,
bool data);
@ -126,25 +128,34 @@ extern void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu);
extern int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu);
extern int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu);
extern void kvmppc_core_queue_machine_check(struct kvm_vcpu *vcpu, ulong flags);
extern void kvmppc_core_queue_machine_check(struct kvm_vcpu *vcpu,
ulong srr1_flags);
extern void kvmppc_core_queue_syscall(struct kvm_vcpu *vcpu);
extern void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong flags);
extern void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu);
extern void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu);
extern void kvmppc_core_queue_vsx_unavail(struct kvm_vcpu *vcpu);
extern void kvmppc_core_queue_program(struct kvm_vcpu *vcpu,
ulong srr1_flags);
extern void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu,
ulong srr1_flags);
extern void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu,
ulong srr1_flags);
extern void kvmppc_core_queue_vsx_unavail(struct kvm_vcpu *vcpu,
ulong srr1_flags);
extern void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu);
extern void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu);
extern void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
struct kvm_interrupt *irq);
extern void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu);
extern void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu, ulong dear_flags,
extern void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
ulong dear_flags,
ulong esr_flags);
extern void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
ulong dear_flags,
ulong esr_flags);
ulong srr1_flags,
ulong dar,
ulong dsisr);
extern void kvmppc_core_queue_itlb_miss(struct kvm_vcpu *vcpu);
extern void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu,
ulong esr_flags);
ulong srr1_flags);
extern void kvmppc_core_flush_tlb(struct kvm_vcpu *vcpu);
extern int kvmppc_core_check_requests(struct kvm_vcpu *vcpu);
@ -315,7 +326,7 @@ extern struct kvmppc_ops *kvmppc_hv_ops;
extern struct kvmppc_ops *kvmppc_pr_ops;
static inline int kvmppc_get_last_inst(struct kvm_vcpu *vcpu,
enum instruction_fetch_type type, u32 *inst)
enum instruction_fetch_type type, ppc_inst_t *inst)
{
int ret = EMULATE_DONE;
u32 fetched_inst;
@ -326,15 +337,30 @@ static inline int kvmppc_get_last_inst(struct kvm_vcpu *vcpu,
ret = kvmppc_load_last_inst(vcpu, type, &vcpu->arch.last_inst);
/* Write fetch_failed unswapped if the fetch failed */
if (ret == EMULATE_DONE)
fetched_inst = kvmppc_need_byteswap(vcpu) ?
swab32(vcpu->arch.last_inst) :
vcpu->arch.last_inst;
else
fetched_inst = vcpu->arch.last_inst;
if (ret != EMULATE_DONE) {
*inst = ppc_inst(KVM_INST_FETCH_FAILED);
return ret;
}
*inst = fetched_inst;
return ret;
#ifdef CONFIG_PPC64
/* Is this a prefixed instruction? */
if ((vcpu->arch.last_inst >> 32) != 0) {
u32 prefix = vcpu->arch.last_inst >> 32;
u32 suffix = vcpu->arch.last_inst;
if (kvmppc_need_byteswap(vcpu)) {
prefix = swab32(prefix);
suffix = swab32(suffix);
}
*inst = ppc_inst_prefix(prefix, suffix);
return EMULATE_DONE;
}
#endif
fetched_inst = kvmppc_need_byteswap(vcpu) ?
swab32(vcpu->arch.last_inst) :
vcpu->arch.last_inst;
*inst = ppc_inst(fetched_inst);
return EMULATE_DONE;
}
static inline bool is_kvmppc_hv_enabled(struct kvm *kvm)

3
arch/powerpc/include/asm/machdep.h
View File

@ -20,7 +20,8 @@ struct kimage;
struct pci_host_bridge;
struct machdep_calls {
char *name;
const char *name;
const char *compatible;
#ifdef CONFIG_PPC64
#ifdef CONFIG_PM
void (*iommu_restore)(void);

10
arch/powerpc/include/asm/module.h
View File

@ -27,8 +27,13 @@ struct ppc_plt_entry {
struct mod_arch_specific {
#ifdef __powerpc64__
unsigned int stubs_section; /* Index of stubs section in module */
#ifdef CONFIG_PPC_KERNEL_PCREL
unsigned int got_section; /* What section is the GOT? */
unsigned int pcpu_section; /* .data..percpu section */
#else
unsigned int toc_section; /* What section is the TOC? */
bool toc_fixed; /* Have we fixed up .TOC.? */
#endif
/* For module function descriptor dereference */
unsigned long start_opd;
@ -52,12 +57,15 @@ struct mod_arch_specific {
/*
* Select ELF headers.
* Make empty section for module_frob_arch_sections to expand.
* Make empty sections for module_frob_arch_sections to expand.
*/
#ifdef __powerpc64__
# ifdef MODULE
asm(".section .stubs,\"ax\",@nobits; .align 3; .previous");
# ifdef CONFIG_PPC_KERNEL_PCREL
asm(".section .mygot,\"a\",@nobits; .align 3; .previous");
# endif
# endif
#else
# ifdef MODULE

4
arch/powerpc/include/asm/mpc8260.h
View File

@ -13,10 +13,6 @@
#ifdef CONFIG_8260
#if defined(CONFIG_PQ2ADS) || defined (CONFIG_PQ2FADS)
#include <platforms/82xx/pq2ads.h>
#endif
#ifdef CONFIG_PCI_8260
#include <platforms/82xx/m82xx_pci.h>
#endif

2
arch/powerpc/include/asm/paca.h
View File

@ -88,7 +88,9 @@ struct paca_struct {
u16 lock_token; /* Constant 0x8000, used in locks */
#endif
#ifndef CONFIG_PPC_KERNEL_PCREL
u64 kernel_toc; /* Kernel TOC address */
#endif
u64 kernelbase; /* Base address of kernel */
u64 kernel_msr; /* MSR while running in kernel */
void *emergency_sp; /* pointer to emergency stack */

7
arch/powerpc/include/asm/pci-bridge.h
View File

@ -8,6 +8,7 @@
#include <linux/list.h>
#include <linux/ioport.h>
#include <linux/numa.h>
#include <linux/iommu.h>
struct device_node;
@ -44,6 +45,9 @@ struct pci_controller_ops {
#endif
void (*shutdown)(struct pci_controller *hose);
struct iommu_group *(*device_group)(struct pci_controller *hose,
struct pci_dev *pdev);
};
/*
@ -131,6 +135,9 @@ struct pci_controller {
struct irq_domain *dev_domain;
struct irq_domain *msi_domain;
struct fwnode_handle *fwnode;
/* iommu_ops support */
struct iommu_device iommu;
};
/* These are used for config access before all the PCI probing

8
arch/powerpc/include/asm/ppc-opcode.h
View File

@ -120,11 +120,18 @@
* 16-bit immediate helper macros: HA() is for use with sign-extending instrs
* (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
* top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
*
* XXX: should these mask out possible sign bits?
*/
#define IMM_H(i) ((uintptr_t)(i)>>16)
#define IMM_HA(i) (((uintptr_t)(i)>>16) + \
(((uintptr_t)(i) & 0x8000) >> 15))
/*
* 18-bit immediate helper for prefix 18-bit upper immediate si0 field.
*/
#define IMM_H18(i) (((uintptr_t)(i)>>16) & 0x3ffff)
/* opcode and xopcode for instructions */
#define OP_PREFIX 1
@ -306,6 +313,7 @@
#define PPC_PREFIX_8LS 0x04000000
/* Prefixed instructions */
#define PPC_INST_PADDI 0x38000000
#define PPC_INST_PLD 0xe4000000
#define PPC_INST_PSTD 0xf4000000

8
arch/powerpc/include/asm/ppc-pci.h
View File

@ -57,11 +57,19 @@ void eeh_sysfs_remove_device(struct pci_dev *pdev);
#endif /* CONFIG_EEH */
#ifdef CONFIG_FSL_ULI1575
void __init uli_init(void);
#endif /* CONFIG_FSL_ULI1575 */
#define PCI_BUSNO(bdfn) ((bdfn >> 8) & 0xff)
#else /* CONFIG_PCI */
static inline void init_pci_config_tokens(void) { }
#endif /* !CONFIG_PCI */
#if !defined(CONFIG_PCI) || !defined(CONFIG_FSL_ULI1575)
static inline void __init uli_init(void) {}
#endif /* !defined(CONFIG_PCI) || !defined(CONFIG_FSL_ULI1575) */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PPC_PCI_H */

32
arch/powerpc/include/asm/ppc_asm.h
View File

@ -180,6 +180,15 @@
#ifdef __KERNEL__
/*
* Used to name C functions called from asm
*/
#ifdef CONFIG_PPC_KERNEL_PCREL
#define CFUNC(name) name@notoc
#else
#define CFUNC(name) name
#endif
/*
* We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
* version below in the else case of the ifdef.
@ -207,6 +216,9 @@
.globl name; \
name:
#ifdef CONFIG_PPC_KERNEL_PCREL
#define _GLOBAL_TOC _GLOBAL
#else
#define _GLOBAL_TOC(name) \
.align 2 ; \
.type name,@function; \
@ -215,6 +227,7 @@ name: \
0: addis r2,r12,(.TOC.-0b)@ha; \
addi r2,r2,(.TOC.-0b)@l; \
.localentry name,.-name
#endif
#define DOTSYM(a) a
@ -346,8 +359,13 @@ GLUE(.,name):
#ifdef __powerpc64__
#ifdef CONFIG_PPC_KERNEL_PCREL
#define __LOAD_PACA_TOC(reg) \
li reg,-1
#else
#define __LOAD_PACA_TOC(reg) \
ld reg,PACATOC(r13)
#endif
#define LOAD_PACA_TOC() \
__LOAD_PACA_TOC(r2)
@ -361,9 +379,15 @@ GLUE(.,name):
ori reg, reg, (expr)@l; \
rldimi reg, tmp, 32, 0
#ifdef CONFIG_PPC_KERNEL_PCREL
#define LOAD_REG_ADDR(reg,name) \
pla reg,name@pcrel
#else
#define LOAD_REG_ADDR(reg,name) \
addis reg,r2,name@toc@ha; \
addi reg,reg,name@toc@l
#endif
#ifdef CONFIG_PPC_BOOK3E_64
/*
@ -837,4 +861,12 @@ END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
#define BTB_FLUSH(reg)
#endif /* CONFIG_PPC_E500 */
#if defined(CONFIG_PPC64_ELF_ABI_V1)
#define STACK_FRAME_PARAMS 48
#elif defined(CONFIG_PPC64_ELF_ABI_V2)
#define STACK_FRAME_PARAMS 32
#elif defined(CONFIG_PPC32)
#define STACK_FRAME_PARAMS 8
#endif
#endif /* _ASM_POWERPC_PPC_ASM_H */

8
arch/powerpc/include/asm/reg.h
View File

@ -382,8 +382,6 @@
#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
#define SPRN_RMOR 0x138 /* Real mode offset register */
#define SPRN_HRMOR 0x139 /* Real mode offset register */
#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
#define SPRN_ASDR 0x330 /* Access segment descriptor register */
#define SPRN_IC 0x350 /* Virtual Instruction Count */
#define SPRN_VTB 0x351 /* Virtual Time Base */
@ -417,6 +415,7 @@
#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
#define FSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */
#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
#define HFSCR_TAR __MASK(FSCR_TAR_LG)
#define HFSCR_EBB __MASK(FSCR_EBB_LG)
@ -1310,6 +1309,11 @@
#define PVR_VER_E500MC 0x8023
#define PVR_VER_E5500 0x8024
#define PVR_VER_E6500 0x8040
#define PVR_VER_7450 0x8000
#define PVR_VER_7455 0x8001
#define PVR_VER_7447 0x8002
#define PVR_VER_7447A 0x8003
#define PVR_VER_7448 0x8004
/*
* For the 8xx processors, all of them report the same PVR family for

4
arch/powerpc/include/asm/rtas-types.h
View File

@ -2,7 +2,7 @@
#ifndef _ASM_POWERPC_RTAS_TYPES_H
#define _ASM_POWERPC_RTAS_TYPES_H
#include <linux/spinlock_types.h>
#include <linux/compiler_attributes.h>
typedef __be32 rtas_arg_t;
@ -12,7 +12,7 @@ struct rtas_args {
__be32 nret;
rtas_arg_t args[16];
rtas_arg_t *rets; /* Pointer to return values in args[]. */
};
} __aligned(8);
struct rtas_t {
unsigned long entry; /* physical address pointer */

5
arch/powerpc/include/asm/sections.h
View File

@ -46,10 +46,15 @@ extern char end_virt_trampolines[];
*/
static inline unsigned long kernel_toc_addr(void)
{
#ifdef CONFIG_PPC_KERNEL_PCREL
BUILD_BUG();
return -1UL;
#else
unsigned long toc_ptr;
asm volatile("mr %0, 2" : "=r" (toc_ptr));
return toc_ptr;
#endif
}
static inline int overlaps_interrupt_vector_text(unsigned long start,

40
arch/powerpc/include/asm/thread_info.h
View File

@ -45,6 +45,7 @@
#include <linux/cache.h>
#include <asm/processor.h>
#include <asm/accounting.h>
#include <asm/ppc_asm.h>
#define SLB_PRELOAD_NR 16U
/*
@ -175,9 +176,11 @@ static inline bool test_thread_local_flags(unsigned int flags)
#ifdef CONFIG_COMPAT
#define is_32bit_task() (test_thread_flag(TIF_32BIT))
#define is_tsk_32bit_task(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT))
#define clear_tsk_compat_task(tsk) (clear_tsk_thread_flag(p, TIF_32BIT))
#else
#define is_32bit_task() (IS_ENABLED(CONFIG_PPC32))
#define is_tsk_32bit_task(tsk) (IS_ENABLED(CONFIG_PPC32))
#define clear_tsk_compat_task(tsk) do { } while (0)
#endif
#if defined(CONFIG_PPC64)
@ -186,6 +189,43 @@ static inline bool test_thread_local_flags(unsigned int flags)
#define is_elf2_task() (0)
#endif
/*
* Walks up the stack frames to make sure that the specified object is
* entirely contained by a single stack frame.
*
* Returns:
* GOOD_FRAME if within a frame
* BAD_STACK if placed across a frame boundary (or outside stack)
*/
static inline int arch_within_stack_frames(const void * const stack,
const void * const stackend,
const void *obj, unsigned long len)
{
const void *params;
const void *frame;
params = *(const void * const *)current_stack_pointer + STACK_FRAME_PARAMS;
frame = **(const void * const * const *)current_stack_pointer;
/*
* low -----------------------------------------------------------> high
* [backchain][metadata][params][local vars][saved registers][backchain]
* ^------------------------------------^
* | allows copies only in this region |
* | |
* params frame
* The metadata region contains the saved LR, CR etc.
*/
while (stack <= frame && frame < stackend) {
if (obj + len <= frame)
return obj >= params ? GOOD_FRAME : BAD_STACK;
params = frame + STACK_FRAME_PARAMS;
frame = *(const void * const *)frame;
}
return BAD_STACK;
}
#endif /* !__ASSEMBLY__ */
#endif /* __KERNEL__ */

30
arch/powerpc/include/asm/uaccess.h
View File

@ -71,14 +71,26 @@ __pu_failed: \
* because we do not write to any memory gcc knows about, so there
* are no aliasing issues.
*/
/* -mprefixed can generate offsets beyond range, fall back hack */
#ifdef CONFIG_PPC_KERNEL_PREFIXED
#define __put_user_asm_goto(x, addr, label, op) \
asm_volatile_goto( \
"1: " op " %0,0(%1) # put_user\n" \
EX_TABLE(1b, %l2) \
: \
: "r" (x), "b" (addr) \
: \
: label)
#else
#define __put_user_asm_goto(x, addr, label, op) \
asm_volatile_goto( \
"1: " op "%U1%X1 %0,%1 # put_user\n" \
EX_TABLE(1b, %l2) \
: \
: "r" (x), "m<>" (*addr) \
: "r" (x), "m<>" (*addr) \
: \
: label)
#endif
#ifdef __powerpc64__
#define __put_user_asm2_goto(x, ptr, label) \
@ -131,14 +143,26 @@ do { \
#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
/* -mprefixed can generate offsets beyond range, fall back hack */
#ifdef CONFIG_PPC_KERNEL_PREFIXED
#define __get_user_asm_goto(x, addr, label, op) \
asm_volatile_goto( \
"1: "op" %0,0(%1) # get_user\n" \
EX_TABLE(1b, %l2) \
: "=r" (x) \
: "b" (addr) \
: \
: label)
#else
#define __get_user_asm_goto(x, addr, label, op) \
asm_volatile_goto( \
"1: "op"%U1%X1 %0, %1 # get_user\n" \
EX_TABLE(1b, %l2) \
: "=r" (x) \
: "m<>" (*addr) \
: "m<>" (*addr) \
: \
: label)
#endif
#ifdef __powerpc64__
#define __get_user_asm2_goto(x, addr, label) \
@ -361,8 +385,6 @@ copy_mc_to_user(void __user *to, const void *from, unsigned long n)
extern long __copy_from_user_flushcache(void *dst, const void __user *src,
unsigned size);
extern void memcpy_page_flushcache(char *to, struct page *page, size_t offset,
size_t len);
static __must_check inline bool user_access_begin(const void __user *ptr, size_t len)
{

4
arch/powerpc/include/uapi/asm/elf.h
View File

@ -279,8 +279,12 @@ typedef elf_fpreg_t elf_vsrreghalf_t32[ELF_NVSRHALFREG];
#define R_PPC64_TLSLD 108
#define R_PPC64_TOCSAVE 109
#define R_PPC64_REL24_NOTOC 116
#define R_PPC64_ENTRY 118
#define R_PPC64_PCREL34 132
#define R_PPC64_GOT_PCREL34 133
#define R_PPC64_REL16 249
#define R_PPC64_REL16_LO 250
#define R_PPC64_REL16_HI 251

2
arch/powerpc/kernel/asm-offsets.c
View File

@ -185,7 +185,9 @@ int main(void)
offsetof(struct task_struct, thread_info));
OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
OFFSET(PACAR1, paca_struct, saved_r1);
#ifndef CONFIG_PPC_KERNEL_PCREL
OFFSET(PACATOC, paca_struct, kernel_toc);
#endif
OFFSET(PACAKBASE, paca_struct, kernelbase);
OFFSET(PACAKMSR, paca_struct, kernel_msr);
#ifdef CONFIG_PPC_BOOK3S_64

2
arch/powerpc/kernel/btext.c
View File

@ -235,7 +235,7 @@ int __init btext_find_display(int allow_nonstdout)
return rc;
for_each_node_by_type(np, "display") {
if (of_get_property(np, "linux,opened", NULL)) {
if (of_property_read_bool(np, "linux,opened")) {
printk("trying %pOF ...\n", np);
rc = btext_initialize(np);
printk("result: %d\n", rc);

23
arch/powerpc/kernel/entry_32.S
View File

@ -183,12 +183,11 @@ syscall_exit_finish:
ret_from_fork:
REST_NVGPRS(r1)
bl schedule_tail
li r3,0
li r3,0 /* fork() return value */
b ret_from_syscall
.globl ret_from_kernel_thread
ret_from_kernel_thread:
REST_NVGPRS(r1)
.globl ret_from_kernel_user_thread
ret_from_kernel_user_thread:
bl schedule_tail
mtctr r14
mr r3,r15
@ -197,6 +196,22 @@ ret_from_kernel_thread:
li r3,0
b ret_from_syscall
.globl start_kernel_thread
start_kernel_thread:
bl schedule_tail
mtctr r14
mr r3,r15
PPC440EP_ERR42
bctrl
/*
* This must not return. We actually want to BUG here, not WARN,
* because BUG will exit the process which is what the kernel thread
* should have done, which may give some hope of continuing.
*/
100: trap
EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
/*
* This routine switches between two different tasks. The process
* state of one is saved on its kernel stack. Then the state

112
arch/powerpc/kernel/exceptions-64s.S
View File

@ -1075,7 +1075,7 @@ EXC_COMMON_BEGIN(system_reset_common)
__GEN_COMMON_BODY system_reset
addi r3,r1,STACK_INT_FRAME_REGS
bl system_reset_exception
bl CFUNC(system_reset_exception)
/* Clear MSR_RI before setting SRR0 and SRR1. */
li r9,0
@ -1223,9 +1223,9 @@ BEGIN_FTR_SECTION
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
addi r3,r1,STACK_INT_FRAME_REGS
BEGIN_FTR_SECTION
bl machine_check_early_boot
bl CFUNC(machine_check_early_boot)
END_FTR_SECTION(0, 1) // nop out after boot
bl machine_check_early
bl CFUNC(machine_check_early)
std r3,RESULT(r1) /* Save result */
ld r12,_MSR(r1)
@ -1286,7 +1286,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
* Queue up the MCE event so that we can log it later, while
* returning from kernel or opal call.
*/
bl machine_check_queue_event
bl CFUNC(machine_check_queue_event)
MACHINE_CHECK_HANDLER_WINDUP
RFI_TO_KERNEL
@ -1312,7 +1312,7 @@ EXC_COMMON_BEGIN(machine_check_common)
*/
GEN_COMMON machine_check
addi r3,r1,STACK_INT_FRAME_REGS
bl machine_check_exception_async
bl CFUNC(machine_check_exception_async)
b interrupt_return_srr
@ -1322,7 +1322,7 @@ EXC_COMMON_BEGIN(machine_check_common)
* done. Queue the event then call the idle code to do the wake up.
*/
EXC_COMMON_BEGIN(machine_check_idle_common)
bl machine_check_queue_event
bl CFUNC(machine_check_queue_event)
/*
* GPR-loss wakeups are relatively straightforward, because the
@ -1361,7 +1361,7 @@ EXC_COMMON_BEGIN(unrecoverable_mce)
BEGIN_FTR_SECTION
li r10,0 /* clear MSR_RI */
mtmsrd r10,1
bl disable_machine_check
bl CFUNC(disable_machine_check)
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
ld r10,PACAKMSR(r13)
li r3,MSR_ME
@ -1378,14 +1378,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
* the early handler which is a true NMI.
*/
addi r3,r1,STACK_INT_FRAME_REGS
bl machine_check_exception
bl CFUNC(machine_check_exception)
/*
* We will not reach here. Even if we did, there is no way out.
* Call unrecoverable_exception and die.
*/
addi r3,r1,STACK_INT_FRAME_REGS
bl unrecoverable_exception
bl CFUNC(unrecoverable_exception)
b .
@ -1440,16 +1440,16 @@ EXC_COMMON_BEGIN(data_access_common)
bne- 1f
#ifdef CONFIG_PPC_64S_HASH_MMU
BEGIN_MMU_FTR_SECTION
bl do_hash_fault
bl CFUNC(do_hash_fault)
MMU_FTR_SECTION_ELSE
bl do_page_fault
bl CFUNC(do_page_fault)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
#else
bl do_page_fault
bl CFUNC(do_page_fault)
#endif
b interrupt_return_srr
1: bl do_break
1: bl CFUNC(do_break)
/*
* do_break() may have changed the NV GPRS while handling a breakpoint.
* If so, we need to restore them with their updated values.
@ -1493,7 +1493,7 @@ EXC_COMMON_BEGIN(data_access_slb_common)
BEGIN_MMU_FTR_SECTION
/* HPT case, do SLB fault */
addi r3,r1,STACK_INT_FRAME_REGS
bl do_slb_fault
bl CFUNC(do_slb_fault)
cmpdi r3,0
bne- 1f
b fast_interrupt_return_srr
@ -1507,7 +1507,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
#endif
std r3,RESULT(r1)
addi r3,r1,STACK_INT_FRAME_REGS
bl do_bad_segment_interrupt
bl CFUNC(do_bad_segment_interrupt)
b interrupt_return_srr
@ -1541,12 +1541,12 @@ EXC_COMMON_BEGIN(instruction_access_common)
addi r3,r1,STACK_INT_FRAME_REGS
#ifdef CONFIG_PPC_64S_HASH_MMU
BEGIN_MMU_FTR_SECTION
bl do_hash_fault
bl CFUNC(do_hash_fault)
MMU_FTR_SECTION_ELSE
bl do_page_fault
bl CFUNC(do_page_fault)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
#else
bl do_page_fault
bl CFUNC(do_page_fault)
#endif
b interrupt_return_srr
@ -1581,7 +1581,7 @@ EXC_COMMON_BEGIN(instruction_access_slb_common)
BEGIN_MMU_FTR_SECTION
/* HPT case, do SLB fault */
addi r3,r1,STACK_INT_FRAME_REGS
bl do_slb_fault
bl CFUNC(do_slb_fault)
cmpdi r3,0
bne- 1f
b fast_interrupt_return_srr
@ -1595,7 +1595,7 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
#endif
std r3,RESULT(r1)
addi r3,r1,STACK_INT_FRAME_REGS
bl do_bad_segment_interrupt
bl CFUNC(do_bad_segment_interrupt)
b interrupt_return_srr
@ -1649,7 +1649,7 @@ EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
EXC_COMMON_BEGIN(hardware_interrupt_common)
GEN_COMMON hardware_interrupt
addi r3,r1,STACK_INT_FRAME_REGS
bl do_IRQ
bl CFUNC(do_IRQ)
BEGIN_FTR_SECTION
b interrupt_return_hsrr
FTR_SECTION_ELSE
@ -1679,7 +1679,7 @@ EXC_VIRT_END(alignment, 0x4600, 0x100)
EXC_COMMON_BEGIN(alignment_common)
GEN_COMMON alignment
addi r3,r1,STACK_INT_FRAME_REGS
bl alignment_exception
bl CFUNC(alignment_exception)
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
b interrupt_return_srr
@ -1745,7 +1745,7 @@ EXC_COMMON_BEGIN(program_check_common)
.Ldo_program_check:
addi r3,r1,STACK_INT_FRAME_REGS
bl program_check_exception
bl CFUNC(program_check_exception)
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
b interrupt_return_srr
@ -1777,7 +1777,7 @@ EXC_COMMON_BEGIN(fp_unavailable_common)
GEN_COMMON fp_unavailable
bne 1f /* if from user, just load it up */
addi r3,r1,STACK_INT_FRAME_REGS
bl kernel_fp_unavailable_exception
bl CFUNC(kernel_fp_unavailable_exception)
0: trap
EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1:
@ -1790,12 +1790,12 @@ BEGIN_FTR_SECTION
bne- 2f
END_FTR_SECTION_IFSET(CPU_FTR_TM)
#endif
bl load_up_fpu
bl CFUNC(load_up_fpu)
b fast_interrupt_return_srr
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2: /* User process was in a transaction */
addi r3,r1,STACK_INT_FRAME_REGS
bl fp_unavailable_tm
bl CFUNC(fp_unavailable_tm)
b interrupt_return_srr
#endif
@ -1839,7 +1839,7 @@ EXC_VIRT_END(decrementer, 0x4900, 0x80)
EXC_COMMON_BEGIN(decrementer_common)
GEN_COMMON decrementer
addi r3,r1,STACK_INT_FRAME_REGS
bl timer_interrupt
bl CFUNC(timer_interrupt)
b interrupt_return_srr
@ -1925,9 +1925,9 @@ EXC_COMMON_BEGIN(doorbell_super_common)
GEN_COMMON doorbell_super
addi r3,r1,STACK_INT_FRAME_REGS
#ifdef CONFIG_PPC_DOORBELL
bl doorbell_exception
bl CFUNC(doorbell_exception)
#else
bl unknown_async_exception
bl CFUNC(unknown_async_exception)
#endif
b interrupt_return_srr
@ -2091,7 +2091,7 @@ EXC_VIRT_END(single_step, 0x4d00, 0x100)
EXC_COMMON_BEGIN(single_step_common)
GEN_COMMON single_step
addi r3,r1,STACK_INT_FRAME_REGS
bl single_step_exception
bl CFUNC(single_step_exception)
b interrupt_return_srr
@ -2126,9 +2126,9 @@ EXC_COMMON_BEGIN(h_data_storage_common)
GEN_COMMON h_data_storage
addi r3,r1,STACK_INT_FRAME_REGS
BEGIN_MMU_FTR_SECTION
bl do_bad_page_fault_segv
bl CFUNC(do_bad_page_fault_segv)
MMU_FTR_SECTION_ELSE
bl unknown_exception
bl CFUNC(unknown_exception)
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
b interrupt_return_hsrr
@ -2154,7 +2154,7 @@ EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
EXC_COMMON_BEGIN(h_instr_storage_common)
GEN_COMMON h_instr_storage
addi r3,r1,STACK_INT_FRAME_REGS
bl unknown_exception
bl CFUNC(unknown_exception)
b interrupt_return_hsrr
@ -2177,7 +2177,7 @@ EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
EXC_COMMON_BEGIN(emulation_assist_common)
GEN_COMMON emulation_assist
addi r3,r1,STACK_INT_FRAME_REGS
bl emulation_assist_interrupt
bl CFUNC(emulation_assist_interrupt)
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
b interrupt_return_hsrr
@ -2237,7 +2237,7 @@ EXC_COMMON_BEGIN(hmi_exception_early_common)
__GEN_COMMON_BODY hmi_exception_early
addi r3,r1,STACK_INT_FRAME_REGS
bl hmi_exception_realmode
bl CFUNC(hmi_exception_realmode)
cmpdi cr0,r3,0
bne 1f
@ -2255,7 +2255,7 @@ EXC_COMMON_BEGIN(hmi_exception_early_common)
EXC_COMMON_BEGIN(hmi_exception_common)
GEN_COMMON hmi_exception
addi r3,r1,STACK_INT_FRAME_REGS
bl handle_hmi_exception
bl CFUNC(handle_hmi_exception)
b interrupt_return_hsrr
@ -2290,9 +2290,9 @@ EXC_COMMON_BEGIN(h_doorbell_common)
GEN_COMMON h_doorbell
addi r3,r1,STACK_INT_FRAME_REGS
#ifdef CONFIG_PPC_DOORBELL
bl doorbell_exception
bl CFUNC(doorbell_exception)
#else
bl unknown_async_exception
bl CFUNC(unknown_async_exception)
#endif
b interrupt_return_hsrr
@ -2325,7 +2325,7 @@ EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
EXC_COMMON_BEGIN(h_virt_irq_common)
GEN_COMMON h_virt_irq
addi r3,r1,STACK_INT_FRAME_REGS
bl do_IRQ
bl CFUNC(do_IRQ)
b interrupt_return_hsrr
@ -2374,10 +2374,10 @@ EXC_COMMON_BEGIN(performance_monitor_common)
lbz r4,PACAIRQSOFTMASK(r13)
cmpdi r4,IRQS_ENABLED
bne 1f
bl performance_monitor_exception_async
bl CFUNC(performance_monitor_exception_async)
b interrupt_return_srr
1:
bl performance_monitor_exception_nmi
bl CFUNC(performance_monitor_exception_nmi)
/* Clear MSR_RI before setting SRR0 and SRR1. */
li r9,0
mtmsrd r9,1
@ -2421,19 +2421,19 @@ BEGIN_FTR_SECTION
bne- 2f
END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
#endif
bl load_up_altivec
bl CFUNC(load_up_altivec)
b fast_interrupt_return_srr
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2: /* User process was in a transaction */
addi r3,r1,STACK_INT_FRAME_REGS
bl altivec_unavailable_tm
bl CFUNC(altivec_unavailable_tm)
b interrupt_return_srr
#endif
1:
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
#endif
addi r3,r1,STACK_INT_FRAME_REGS
bl altivec_unavailable_exception
bl CFUNC(altivec_unavailable_exception)
b interrupt_return_srr
@ -2475,14 +2475,14 @@ BEGIN_FTR_SECTION
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2: /* User process was in a transaction */
addi r3,r1,STACK_INT_FRAME_REGS
bl vsx_unavailable_tm
bl CFUNC(vsx_unavailable_tm)
b interrupt_return_srr
#endif
1:
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
#endif
addi r3,r1,STACK_INT_FRAME_REGS
bl vsx_unavailable_exception
bl CFUNC(vsx_unavailable_exception)
b interrupt_return_srr
@ -2509,7 +2509,7 @@ EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
EXC_COMMON_BEGIN(facility_unavailable_common)
GEN_COMMON facility_unavailable
addi r3,r1,STACK_INT_FRAME_REGS
bl facility_unavailable_exception
bl CFUNC(facility_unavailable_exception)
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
b interrupt_return_srr
@ -2537,7 +2537,7 @@ EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
EXC_COMMON_BEGIN(h_facility_unavailable_common)
GEN_COMMON h_facility_unavailable
addi r3,r1,STACK_INT_FRAME_REGS
bl facility_unavailable_exception
bl CFUNC(facility_unavailable_exception)
/* XXX Shouldn't be necessary in practice */
HANDLER_RESTORE_NVGPRS()
b interrupt_return_hsrr
@ -2568,7 +2568,7 @@ EXC_VIRT_NONE(0x5200, 0x100)
EXC_COMMON_BEGIN(cbe_system_error_common)
GEN_COMMON cbe_system_error
addi r3,r1,STACK_INT_FRAME_REGS
bl cbe_system_error_exception
bl CFUNC(cbe_system_error_exception)
b interrupt_return_hsrr
#else /* CONFIG_CBE_RAS */
@ -2599,7 +2599,7 @@ EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
EXC_COMMON_BEGIN(instruction_breakpoint_common)
GEN_COMMON instruction_breakpoint
addi r3,r1,STACK_INT_FRAME_REGS
bl instruction_breakpoint_exception
bl CFUNC(instruction_breakpoint_exception)
b interrupt_return_srr
@ -2721,7 +2721,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
EXC_COMMON_BEGIN(denorm_exception_common)
GEN_COMMON denorm_exception
addi r3,r1,STACK_INT_FRAME_REGS
bl unknown_exception
bl CFUNC(unknown_exception)
b interrupt_return_hsrr
@ -2738,7 +2738,7 @@ EXC_VIRT_NONE(0x5600, 0x100)
EXC_COMMON_BEGIN(cbe_maintenance_common)
GEN_COMMON cbe_maintenance
addi r3,r1,STACK_INT_FRAME_REGS
bl cbe_maintenance_exception
bl CFUNC(cbe_maintenance_exception)
b interrupt_return_hsrr
#else /* CONFIG_CBE_RAS */
@ -2764,10 +2764,10 @@ EXC_COMMON_BEGIN(altivec_assist_common)
GEN_COMMON altivec_assist
addi r3,r1,STACK_INT_FRAME_REGS
#ifdef CONFIG_ALTIVEC
bl altivec_assist_exception
bl CFUNC(altivec_assist_exception)
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
#else
bl unknown_exception
bl CFUNC(unknown_exception)
#endif
b interrupt_return_srr
@ -2785,7 +2785,7 @@ EXC_VIRT_NONE(0x5800, 0x100)
EXC_COMMON_BEGIN(cbe_thermal_common)
GEN_COMMON cbe_thermal
addi r3,r1,STACK_INT_FRAME_REGS
bl cbe_thermal_exception
bl CFUNC(cbe_thermal_exception)
b interrupt_return_hsrr
#else /* CONFIG_CBE_RAS */
@ -2818,7 +2818,7 @@ EXC_COMMON_BEGIN(soft_nmi_common)
__GEN_COMMON_BODY soft_nmi
addi r3,r1,STACK_INT_FRAME_REGS
bl soft_nmi_interrupt
bl CFUNC(soft_nmi_interrupt)
/* Clear MSR_RI before setting SRR0 and SRR1. */
li r9,0

133
arch/powerpc/kernel/head_64.S
View File

@ -76,6 +76,13 @@
* 2. The kernel is entered at __start
*/
/*
* boot_from_prom and prom_init run at the physical address. Everything
* after prom and kexec entry run at the virtual address (PAGE_OFFSET).
* Secondaries run at the virtual address from generic_secondary_common_init
* onward.
*/
OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
USE_FIXED_SECTION(first_256B)
/*
@ -303,13 +310,11 @@ _GLOBAL(fsl_secondary_thread_init)
/* turn on 64-bit mode */
bl enable_64b_mode
/* get a valid TOC pointer, wherever we're mapped at */
bl relative_toc
tovirt(r2,r2)
/* Book3E initialization */
mr r3,r24
bl book3e_secondary_thread_init
bl relative_toc
b generic_secondary_common_init
#endif /* CONFIG_PPC_BOOK3E_64 */
@ -325,22 +330,24 @@ _GLOBAL(fsl_secondary_thread_init)
*/
_GLOBAL(generic_secondary_smp_init)
FIXUP_ENDIAN
li r13,0
/* Poison TOC */
li r2,-1
mr r24,r3
mr r25,r4
/* turn on 64-bit mode */
bl enable_64b_mode
/* get a valid TOC pointer, wherever we're mapped at */
bl relative_toc
tovirt(r2,r2)
#ifdef CONFIG_PPC_BOOK3E_64
/* Book3E initialization */
mr r3,r24
mr r4,r25
bl book3e_secondary_core_init
/* Now NIA and r2 are relocated to PAGE_OFFSET if not already */
/*
* After common core init has finished, check if the current thread is the
* one we wanted to boot. If not, start the specified thread and stop the
@ -378,6 +385,16 @@ _GLOBAL(generic_secondary_smp_init)
10:
b 10b
20:
#else
/* Now the MMU is off, can branch to our PAGE_OFFSET address */
bcl 20,31,$+4
1: mflr r11
addi r11,r11,(2f - 1b)
tovirt(r11, r11)
mtctr r11
bctr
2:
bl relative_toc
#endif
generic_secondary_common_init:
@ -492,6 +509,8 @@ SYM_FUNC_START_LOCAL(start_initialization_book3s)
/* Switch off MMU if not already off */
bl __mmu_off
/* Now the MMU is off, can return to our PAGE_OFFSET address */
tovirt(r25,r25)
mtlr r25
blr
SYM_FUNC_END(start_initialization_book3s)
@ -515,14 +534,8 @@ __start_initialization_multiplatform:
/* Zero r13 (paca) so early program check / mce don't use it */
li r13,0
/* Get TOC pointer (current runtime address) */
bl relative_toc
/* find out where we are now */
bcl 20,31,$+4
0: mflr r26 /* r26 = runtime addr here */
addis r26,r26,(_stext - 0b)@ha
addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
/* Poison TOC */
li r2,-1
/*
* Are we booted from a PROM Of-type client-interface ?
@ -540,16 +553,41 @@ __start_initialization_multiplatform:
mr r29,r9
#endif
/* Get TOC pointer (current runtime address) */
bl relative_toc
/* These functions return to the virtual (PAGE_OFFSET) address */
#ifdef CONFIG_PPC_BOOK3E_64
bl start_initialization_book3e
#else
bl start_initialization_book3s
#endif /* CONFIG_PPC_BOOK3E_64 */
/* Get TOC pointer, virtual */
bl relative_toc
/* find out where we are now */
/* OPAL doesn't pass base address in r4, have to derive it. */
bcl 20,31,$+4
0: mflr r26 /* r26 = runtime addr here */
addis r26,r26,(_stext - 0b)@ha
addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
b __after_prom_start
__REF
__boot_from_prom:
#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
/* Get TOC pointer, non-virtual */
bl relative_toc
/* find out where we are now */
bcl 20,31,$+4
0: mflr r26 /* r26 = runtime addr here */
addis r26,r26,(_stext - 0b)@ha
addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
/* Save parameters */
mr r31,r3
mr r30,r4
@ -579,7 +617,7 @@ __boot_from_prom:
/* Do all of the interaction with OF client interface */
mr r8,r26
bl prom_init
bl CFUNC(prom_init)
#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
/* We never return. We also hit that trap if trying to boot
@ -590,18 +628,11 @@ __boot_from_prom:
__after_prom_start:
#ifdef CONFIG_RELOCATABLE
/* process relocations for the final address of the kernel */
lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
sldi r25,r25,32
#if defined(CONFIG_PPC_BOOK3E_64)
tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
#endif
lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
#if defined(CONFIG_PPC_BOOK3E_64)
tophys(r26,r26)
#endif
cmplwi cr0,r7,1 /* flagged to stay where we are ? */
bne 1f
add r25,r25,r26
mr r25,r26 /* then use current kernel base */
beq 1f
LOAD_REG_IMMEDIATE(r25, PAGE_OFFSET) /* else use static kernel base */
1: mr r3,r25
bl relocate
#if defined(CONFIG_PPC_BOOK3E_64)
@ -617,14 +648,8 @@ __after_prom_start:
*
* Note: This process overwrites the OF exception vectors.
*/
li r3,0 /* target addr */
#ifdef CONFIG_PPC_BOOK3E_64
tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
#endif
LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET)
mr. r4,r26 /* In some cases the loader may */
#if defined(CONFIG_PPC_BOOK3E_64)
tovirt(r4,r4)
#endif
beq 9f /* have already put us at zero */
li r6,0x100 /* Start offset, the first 0x100 */
/* bytes were copied earlier. */
@ -635,9 +660,6 @@ __after_prom_start:
* variable __run_at_load, if it is set the kernel is treated as relocatable
* kernel, otherwise it will be moved to PHYSICAL_START
*/
#if defined(CONFIG_PPC_BOOK3E_64)
tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
#endif
lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
cmplwi cr0,r7,1
bne 3f
@ -756,9 +778,15 @@ _GLOBAL(pmac_secondary_start)
sync
slbia
/* get TOC pointer (real address) */
/* Branch to our PAGE_OFFSET address */
bcl 20,31,$+4
1: mflr r11
addi r11,r11,(2f - 1b)
tovirt(r11, r11)
mtctr r11
bctr
2:
bl relative_toc
tovirt(r2,r2)
/* Copy some CPU settings from CPU 0 */
bl __restore_cpu_ppc970
@ -817,7 +845,7 @@ __secondary_start:
* can turn it on below. This is a call to C, which is OK, we're still
* running on the emergency stack.
*/
bl early_setup_secondary
bl CFUNC(early_setup_secondary)
/*
* The primary has initialized our kernel stack for us in the paca, grab
@ -856,7 +884,7 @@ start_secondary_prolog:
LOAD_PACA_TOC()
li r3,0
std r3,0(r1) /* Zero the stack frame pointer */
bl start_secondary
bl CFUNC(start_secondary)
b .
/*
* Reset stack pointer and call start_secondary
@ -867,7 +895,7 @@ _GLOBAL(start_secondary_resume)
ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
li r3,0
std r3,0(r1) /* Zero the stack frame pointer */
bl start_secondary
bl CFUNC(start_secondary)
b .
#endif
@ -897,10 +925,15 @@ SYM_FUNC_END(enable_64b_mode)
* TOC in -mcmodel=medium mode. After we relocate to 0 but before
* the MMU is on we need our TOC to be a virtual address otherwise
* these pointers will be real addresses which may get stored and
* accessed later with the MMU on. We use tovirt() at the call
* sites to handle this.
* accessed later with the MMU on. We branch to the virtual address
* while still in real mode then call relative_toc again to handle
* this.
*/
_GLOBAL(relative_toc)
#ifdef CONFIG_PPC_KERNEL_PCREL
tdnei r2,-1
blr
#else
mflr r0
bcl 20,31,$+4
0: mflr r11
@ -911,15 +944,15 @@ _GLOBAL(relative_toc)
.balign 8
p_toc: .8byte .TOC. - 0b
#endif
/*
* This is where the main kernel code starts.
*/
__REF
start_here_multiplatform:
/* set up the TOC */
bl relative_toc
tovirt(r2,r2)
/* Adjust TOC for moved kernel. Could adjust when moving it instead. */
bl relative_toc
/* Clear out the BSS. It may have been done in prom_init,
* already but that's irrelevant since prom_init will soon
@ -972,7 +1005,7 @@ start_here_multiplatform:
*/
#ifdef CONFIG_KASAN
bl kasan_early_init
bl CFUNC(kasan_early_init)
#endif
/* Restore parameters passed from prom_init/kexec */
mr r3,r31
@ -1005,7 +1038,7 @@ start_here_common:
stb r0,PACAIRQHAPPENED(r13)
/* Generic kernel entry */
bl start_kernel
bl CFUNC(start_kernel)
/* Not reached */
0: trap

1
arch/powerpc/kernel/head_booke.h
View File

@ -5,6 +5,7 @@
#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
#include <asm/kvm_asm.h>
#include <asm/kvm_booke_hv_asm.h>
#include <asm/thread_info.h> /* for THREAD_SHIFT */
#ifdef __ASSEMBLY__

10
arch/powerpc/kernel/idle.c
View File

@ -107,19 +107,11 @@ static struct ctl_table powersave_nap_ctl_table[] = {
},
{}
};
static struct ctl_table powersave_nap_sysctl_root[] = {
{
.procname = "kernel",
.mode = 0555,
.child = powersave_nap_ctl_table,
},
{}
};
static int __init
register_powersave_nap_sysctl(void)
{
register_sysctl_table(powersave_nap_sysctl_root);
register_sysctl("kernel", powersave_nap_ctl_table);
return 0;
}

2
arch/powerpc/kernel/interrupt.c
View File

@ -95,7 +95,7 @@ static notrace void booke_load_dbcr0(void)
#endif
}
static void check_return_regs_valid(struct pt_regs *regs)
static notrace void check_return_regs_valid(struct pt_regs *regs)
{
#ifdef CONFIG_PPC_BOOK3S_64
unsigned long trap, srr0, srr1;

56
arch/powerpc/kernel/interrupt_64.S
View File

@ -101,12 +101,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
* state of kernel code.
*/
SANITIZE_SYSCALL_GPRS()
bl system_call_exception
bl CFUNC(system_call_exception)
.Lsyscall_vectored_\name\()_exit:
addi r4,r1,STACK_INT_FRAME_REGS
li r5,1 /* scv */
bl syscall_exit_prepare
bl CFUNC(syscall_exit_prepare)
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
.Lsyscall_vectored_\name\()_rst_start:
lbz r11,PACAIRQHAPPENED(r13)
@ -185,7 +185,7 @@ _ASM_NOKPROBE_SYMBOL(syscall_vectored_\name\()_restart)
addi r4,r1,STACK_INT_FRAME_REGS
li r11,IRQS_ALL_DISABLED
stb r11,PACAIRQSOFTMASK(r13)
bl syscall_exit_restart
bl CFUNC(syscall_exit_restart)
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
b .Lsyscall_vectored_\name\()_rst_start
1:
@ -286,12 +286,12 @@ END_BTB_FLUSH_SECTION
* state of kernel code.
*/
SANITIZE_SYSCALL_GPRS()
bl system_call_exception
bl CFUNC(system_call_exception)
.Lsyscall_exit:
addi r4,r1,STACK_INT_FRAME_REGS
li r5,0 /* !scv */
bl syscall_exit_prepare
bl CFUNC(syscall_exit_prepare)
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
#ifdef CONFIG_PPC_BOOK3S
.Lsyscall_rst_start:
@ -372,7 +372,7 @@ _ASM_NOKPROBE_SYMBOL(syscall_restart)
addi r4,r1,STACK_INT_FRAME_REGS
li r11,IRQS_ALL_DISABLED
stb r11,PACAIRQSOFTMASK(r13)
bl syscall_exit_restart
bl CFUNC(syscall_exit_restart)
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
b .Lsyscall_rst_start
1:
@ -401,7 +401,7 @@ _ASM_NOKPROBE_SYMBOL(fast_interrupt_return_srr)
li r3,0 /* 0 return value, no EMULATE_STACK_STORE */
bne+ .Lfast_kernel_interrupt_return_srr
addi r3,r1,STACK_INT_FRAME_REGS
bl unrecoverable_exception
bl CFUNC(unrecoverable_exception)
b . /* should not get here */
#else
bne .Lfast_user_interrupt_return_srr
@ -419,7 +419,7 @@ _ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\())
interrupt_return_\srr\()_user: /* make backtraces match the _kernel variant */
_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_user)
addi r3,r1,STACK_INT_FRAME_REGS
bl interrupt_exit_user_prepare
bl CFUNC(interrupt_exit_user_prepare)
#ifndef CONFIG_INTERRUPT_SANITIZE_REGISTERS
cmpdi r3,0
bne- .Lrestore_nvgprs_\srr
@ -523,7 +523,7 @@ _ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_user_restart)
addi r3,r1,STACK_INT_FRAME_REGS
li r11,IRQS_ALL_DISABLED
stb r11,PACAIRQSOFTMASK(r13)
bl interrupt_exit_user_restart
bl CFUNC(interrupt_exit_user_restart)
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
b .Linterrupt_return_\srr\()_user_rst_start
1:
@ -536,7 +536,7 @@ RESTART_TABLE(.Linterrupt_return_\srr\()_user_rst_start, .Linterrupt_return_\srr
interrupt_return_\srr\()_kernel:
_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_kernel)
addi r3,r1,STACK_INT_FRAME_REGS
bl interrupt_exit_kernel_prepare
bl CFUNC(interrupt_exit_kernel_prepare)
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
.Linterrupt_return_\srr\()_kernel_rst_start:
@ -705,7 +705,7 @@ _ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_kernel_restart)
addi r3,r1,STACK_INT_FRAME_REGS
li r11,IRQS_ALL_DISABLED
stb r11,PACAIRQSOFTMASK(r13)
bl interrupt_exit_kernel_restart
bl CFUNC(interrupt_exit_kernel_restart)
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
b .Linterrupt_return_\srr\()_kernel_rst_start
1:
@ -727,21 +727,20 @@ DEFINE_FIXED_SYMBOL(__end_soft_masked, text)
#ifdef CONFIG_PPC_BOOK3S
_GLOBAL(ret_from_fork_scv)
bl schedule_tail
REST_NVGPRS(r1)
bl CFUNC(schedule_tail)
HANDLER_RESTORE_NVGPRS()
li r3,0 /* fork() return value */
b .Lsyscall_vectored_common_exit
#endif
_GLOBAL(ret_from_fork)
bl schedule_tail
REST_NVGPRS(r1)
bl CFUNC(schedule_tail)
HANDLER_RESTORE_NVGPRS()
li r3,0 /* fork() return value */
b .Lsyscall_exit
_GLOBAL(ret_from_kernel_thread)
bl schedule_tail
REST_NVGPRS(r1)
_GLOBAL(ret_from_kernel_user_thread)
bl CFUNC(schedule_tail)
mtctr r14
mr r3,r15
#ifdef CONFIG_PPC64_ELF_ABI_V2
@ -749,4 +748,25 @@ _GLOBAL(ret_from_kernel_thread)
#endif
bctrl
li r3,0
/*
* It does not matter whether this returns via the scv or sc path
* because it returns as execve() and therefore has no calling ABI
* (i.e., it sets registers according to the exec()ed entry point).
*/
b .Lsyscall_exit
_GLOBAL(start_kernel_thread)
bl CFUNC(schedule_tail)
mtctr r14
mr r3,r15
#ifdef CONFIG_PPC64_ELF_ABI_V2
mr r12,r14
#endif
bctrl
/*
* This must not return. We actually want to BUG here, not WARN,
* because BUG will exit the process which is what the kernel thread
* should have done, which may give some hope of continuing.
*/
100: trap
EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0

246
arch/powerpc/kernel/iommu.c
View File

@ -35,6 +35,7 @@
#include <asm/vio.h>
#include <asm/tce.h>
#include <asm/mmu_context.h>
#include <asm/ppc-pci.h>
#define DBG(...)
@ -1086,7 +1087,7 @@ void iommu_tce_kill(struct iommu_table *tbl,
}
EXPORT_SYMBOL_GPL(iommu_tce_kill);
int iommu_take_ownership(struct iommu_table *tbl)
static int iommu_take_ownership(struct iommu_table *tbl)
{
unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
int ret = 0;
@ -1118,9 +1119,8 @@ int iommu_take_ownership(struct iommu_table *tbl)
return ret;
}
EXPORT_SYMBOL_GPL(iommu_take_ownership);
void iommu_release_ownership(struct iommu_table *tbl)
static void iommu_release_ownership(struct iommu_table *tbl)
{
unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
@ -1137,7 +1137,6 @@ void iommu_release_ownership(struct iommu_table *tbl)
spin_unlock(&tbl->pools[i].lock);
spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
}
EXPORT_SYMBOL_GPL(iommu_release_ownership);
int iommu_add_device(struct iommu_table_group *table_group, struct device *dev)
{
@ -1158,8 +1157,14 @@ int iommu_add_device(struct iommu_table_group *table_group, struct device *dev)
pr_debug("%s: Adding %s to iommu group %d\n",
__func__, dev_name(dev), iommu_group_id(table_group->group));
return iommu_group_add_device(table_group->group, dev);
/*
* This is still not adding devices via the IOMMU bus notifier because
* of pcibios_init() from arch/powerpc/kernel/pci_64.c which calls
* pcibios_scan_phb() first (and this guy adds devices and triggers
* the notifier) and only then it calls pci_bus_add_devices() which
* configures DMA for buses which also creates PEs and IOMMU groups.
*/
return iommu_probe_device(dev);
}
EXPORT_SYMBOL_GPL(iommu_add_device);
@ -1179,4 +1184,233 @@ void iommu_del_device(struct device *dev)
iommu_group_remove_device(dev);
}
EXPORT_SYMBOL_GPL(iommu_del_device);
/*
* A simple iommu_table_group_ops which only allows reusing the existing
* iommu_table. This handles VFIO for POWER7 or the nested KVM.
* The ops does not allow creating windows and only allows reusing the existing
* one if it matches table_group->tce32_start/tce32_size/page_shift.
*/
static unsigned long spapr_tce_get_table_size(__u32 page_shift,
__u64 window_size, __u32 levels)
{
unsigned long size;
if (levels > 1)
return ~0U;
size = window_size >> (page_shift - 3);
return size;
}
static long spapr_tce_create_table(struct iommu_table_group *table_group, int num,
__u32 page_shift, __u64 window_size, __u32 levels,
struct iommu_table **ptbl)
{
struct iommu_table *tbl = table_group->tables[0];
if (num > 0)
return -EPERM;
if (tbl->it_page_shift != page_shift ||
tbl->it_size != (window_size >> page_shift) ||
tbl->it_indirect_levels != levels - 1)
return -EINVAL;
*ptbl = iommu_tce_table_get(tbl);
return 0;
}
static long spapr_tce_set_window(struct iommu_table_group *table_group,
int num, struct iommu_table *tbl)
{
return tbl == table_group->tables[num] ? 0 : -EPERM;
}
static long spapr_tce_unset_window(struct iommu_table_group *table_group, int num)
{
return 0;
}
static long spapr_tce_take_ownership(struct iommu_table_group *table_group)
{
int i, j, rc = 0;
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
struct iommu_table *tbl = table_group->tables[i];
if (!tbl || !tbl->it_map)
continue;
rc = iommu_take_ownership(tbl);
if (!rc)
continue;
for (j = 0; j < i; ++j)
iommu_release_ownership(table_group->tables[j]);
return rc;
}
return 0;
}
static void spapr_tce_release_ownership(struct iommu_table_group *table_group)
{
int i;
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
struct iommu_table *tbl = table_group->tables[i];
if (!tbl)
continue;
iommu_table_clear(tbl);
if (tbl->it_map)
iommu_release_ownership(tbl);
}
}
struct iommu_table_group_ops spapr_tce_table_group_ops = {
.get_table_size = spapr_tce_get_table_size,
.create_table = spapr_tce_create_table,
.set_window = spapr_tce_set_window,
.unset_window = spapr_tce_unset_window,
.take_ownership = spapr_tce_take_ownership,
.release_ownership = spapr_tce_release_ownership,
};
/*
* A simple iommu_ops to allow less cruft in generic VFIO code.
*/
static int spapr_tce_blocking_iommu_attach_dev(struct iommu_domain *dom,
struct device *dev)
{
struct iommu_group *grp = iommu_group_get(dev);
struct iommu_table_group *table_group;
int ret = -EINVAL;
if (!grp)
return -ENODEV;
table_group = iommu_group_get_iommudata(grp);
ret = table_group->ops->take_ownership(table_group);
iommu_group_put(grp);
return ret;
}
static void spapr_tce_blocking_iommu_set_platform_dma(struct device *dev)
{
struct iommu_group *grp = iommu_group_get(dev);
struct iommu_table_group *table_group;
table_group = iommu_group_get_iommudata(grp);
table_group->ops->release_ownership(table_group);
}
static const struct iommu_domain_ops spapr_tce_blocking_domain_ops = {
.attach_dev = spapr_tce_blocking_iommu_attach_dev,
};
static bool spapr_tce_iommu_capable(struct device *dev, enum iommu_cap cap)
{
switch (cap) {
case IOMMU_CAP_CACHE_COHERENCY:
return true;
default:
break;
}
return false;
}
static struct iommu_domain *spapr_tce_iommu_domain_alloc(unsigned int type)
{
struct iommu_domain *dom;
if (type != IOMMU_DOMAIN_BLOCKED)
return NULL;
dom = kzalloc(sizeof(*dom), GFP_KERNEL);
if (!dom)
return NULL;
dom->ops = &spapr_tce_blocking_domain_ops;
return dom;
}
static struct iommu_device *spapr_tce_iommu_probe_device(struct device *dev)
{
struct pci_dev *pdev;
struct pci_controller *hose;
if (!dev_is_pci(dev))
return ERR_PTR(-EPERM);
pdev = to_pci_dev(dev);
hose = pdev->bus->sysdata;
return &hose->iommu;
}
static void spapr_tce_iommu_release_device(struct device *dev)
{
}
static struct iommu_group *spapr_tce_iommu_device_group(struct device *dev)
{
struct pci_controller *hose;
struct pci_dev *pdev;
pdev = to_pci_dev(dev);
hose = pdev->bus->sysdata;
if (!hose->controller_ops.device_group)
return ERR_PTR(-ENOENT);
return hose->controller_ops.device_group(hose, pdev);
}
static const struct iommu_ops spapr_tce_iommu_ops = {
.capable = spapr_tce_iommu_capable,
.domain_alloc = spapr_tce_iommu_domain_alloc,
.probe_device = spapr_tce_iommu_probe_device,
.release_device = spapr_tce_iommu_release_device,
.device_group = spapr_tce_iommu_device_group,
.set_platform_dma_ops = spapr_tce_blocking_iommu_set_platform_dma,
};
static struct attribute *spapr_tce_iommu_attrs[] = {
NULL,
};
static struct attribute_group spapr_tce_iommu_group = {
.name = "spapr-tce-iommu",
.attrs = spapr_tce_iommu_attrs,
};
static const struct attribute_group *spapr_tce_iommu_groups[] = {
&spapr_tce_iommu_group,
NULL,
};
/*
* This registers IOMMU devices of PHBs. This needs to happen
* after core_initcall(iommu_init) + postcore_initcall(pci_driver_init) and
* before subsys_initcall(iommu_subsys_init).
*/
static int __init spapr_tce_setup_phb_iommus_initcall(void)
{
struct pci_controller *hose;
list_for_each_entry(hose, &hose_list, list_node) {
iommu_device_sysfs_add(&hose->iommu, hose->parent,
spapr_tce_iommu_groups, "iommu-phb%04x",
hose->global_number);
iommu_device_register(&hose->iommu, &spapr_tce_iommu_ops,
hose->parent);
}
return 0;
}
postcore_initcall_sync(spapr_tce_setup_phb_iommus_initcall);
#endif /* CONFIG_IOMMU_API */

8
arch/powerpc/kernel/irq.c
View File

@ -206,7 +206,11 @@ static __always_inline void call_do_softirq(const void *sp)
asm volatile (
PPC_STLU " %%r1, %[offset](%[sp]) ;"
"mr %%r1, %[sp] ;"
#ifdef CONFIG_PPC_KERNEL_PCREL
"bl %[callee]@notoc ;"
#else
"bl %[callee] ;"
#endif
PPC_LL " %%r1, 0(%%r1) ;"
: // Outputs
: // Inputs
@ -259,7 +263,11 @@ static __always_inline void call_do_irq(struct pt_regs *regs, void *sp)
PPC_STLU " %%r1, %[offset](%[sp]) ;"
"mr %%r4, %%r1 ;"
"mr %%r1, %[sp] ;"
#ifdef CONFIG_PPC_KERNEL_PCREL
"bl %[callee]@notoc ;"
#else
"bl %[callee] ;"
#endif
PPC_LL " %%r1, 0(%%r1) ;"
: // Outputs
"+r" (r3)

10
arch/powerpc/kernel/irq_64.c
View File

@ -348,13 +348,12 @@ EXPORT_SYMBOL(arch_local_irq_restore);
* already the case when ppc_md.power_save is called). The function
* will return whether to enter power save or just return.
*
* In the former case, it will have notified lockdep of interrupts
* being re-enabled and generally sanitized the lazy irq state,
* and in the latter case it will leave with interrupts hard
* In the former case, it will have generally sanitized the lazy irq
* state, and in the latter case it will leave with interrupts hard
* disabled and marked as such, so the local_irq_enable() call
* in arch_cpu_idle() will properly re-enable everything.
*/
bool prep_irq_for_idle(void)
__cpuidle bool prep_irq_for_idle(void)
{
/*
* First we need to hard disable to ensure no interrupt
@ -370,9 +369,6 @@ bool prep_irq_for_idle(void)
if (lazy_irq_pending())
return false;
/* Tell lockdep we are about to re-enable */
trace_hardirqs_on();
/*
* Mark interrupts as soft-enabled and clear the
* PACA_IRQ_HARD_DIS from the pending mask since we

172
arch/powerpc/kernel/isa-bridge.c
View File

@ -55,80 +55,49 @@ static void remap_isa_base(phys_addr_t pa, unsigned long size)
}
}
static void pci_process_ISA_OF_ranges(struct device_node *isa_node,
unsigned long phb_io_base_phys)
static int process_ISA_OF_ranges(struct device_node *isa_node,
unsigned long phb_io_base_phys)
{
/* We should get some saner parsing here and remove these structs */
struct pci_address {
u32 a_hi;
u32 a_mid;
u32 a_lo;
};
struct isa_address {
u32 a_hi;
u32 a_lo;
};
struct isa_range {
struct isa_address isa_addr;
struct pci_address pci_addr;
unsigned int size;
};
const struct isa_range *range;
unsigned long pci_addr;
unsigned int isa_addr;
unsigned int size;
int rlen = 0;
struct of_range_parser parser;
struct of_range range;
range = of_get_property(isa_node, "ranges", &rlen);
if (range == NULL || (rlen < sizeof(struct isa_range)))
if (of_range_parser_init(&parser, isa_node))
goto inval_range;
/* From "ISA Binding to 1275"
* The ranges property is laid out as an array of elements,
* each of which comprises:
* cells 0 - 1: an ISA address
* cells 2 - 4: a PCI address
* (size depending on dev->n_addr_cells)
* cell 5: the size of the range
*/
if ((range->isa_addr.a_hi & ISA_SPACE_MASK) != ISA_SPACE_IO) {
range++;
rlen -= sizeof(struct isa_range);
if (rlen < sizeof(struct isa_range))
goto inval_range;
for_each_of_range(&parser, &range) {
if ((range.flags & ISA_SPACE_MASK) != ISA_SPACE_IO)
continue;
if (range.cpu_addr == OF_BAD_ADDR) {
pr_err("ISA: Bad CPU mapping: %s\n", __func__);
return -EINVAL;
}
/* We need page alignment */
if ((range.bus_addr & ~PAGE_MASK) || (range.cpu_addr & ~PAGE_MASK)) {
pr_warn("ISA: bridge %pOF has non aligned IO range\n", isa_node);
return -EINVAL;
}
/* Align size and make sure it's cropped to 64K */
size = PAGE_ALIGN(range.size);
if (size > 0x10000)
size = 0x10000;
if (!phb_io_base_phys)
phb_io_base_phys = range.cpu_addr;
remap_isa_base(phb_io_base_phys, size);
return 0;
}
if ((range->isa_addr.a_hi & ISA_SPACE_MASK) != ISA_SPACE_IO)
goto inval_range;
isa_addr = range->isa_addr.a_lo;
pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
range->pci_addr.a_lo;
/* Assume these are both zero. Note: We could fix that and
* do a proper parsing instead ... oh well, that will do for
* now as nobody uses fancy mappings for ISA bridges
*/
if ((pci_addr != 0) || (isa_addr != 0)) {
printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
__func__);
return;
}
/* Align size and make sure it's cropped to 64K */
size = PAGE_ALIGN(range->size);
if (size > 0x10000)
size = 0x10000;
remap_isa_base(phb_io_base_phys, size);
return;
inval_range:
printk(KERN_ERR "no ISA IO ranges or unexpected isa range, "
"mapping 64k\n");
remap_isa_base(phb_io_base_phys, 0x10000);
if (!phb_io_base_phys) {
pr_err("no ISA IO ranges or unexpected isa range, mapping 64k\n");
remap_isa_base(phb_io_base_phys, 0x10000);
}
return 0;
}
@ -170,7 +139,7 @@ void __init isa_bridge_find_early(struct pci_controller *hose)
isa_bridge_devnode = np;
/* Now parse the "ranges" property and setup the ISA mapping */
pci_process_ISA_OF_ranges(np, hose->io_base_phys);
process_ISA_OF_ranges(np, hose->io_base_phys);
/* Set the global ISA io base to indicate we have an ISA bridge */
isa_io_base = ISA_IO_BASE;
@ -186,75 +155,15 @@ void __init isa_bridge_find_early(struct pci_controller *hose)
*/
void __init isa_bridge_init_non_pci(struct device_node *np)
{
const __be32 *ranges, *pbasep = NULL;
int rlen, i, rs;
u32 na, ns, pna;
u64 cbase, pbase, size = 0;
int ret;
/* If we already have an ISA bridge, bail off */
if (isa_bridge_devnode != NULL)
return;
pna = of_n_addr_cells(np);
if (of_property_read_u32(np, "#address-cells", &na) ||
of_property_read_u32(np, "#size-cells", &ns)) {
pr_warn("ISA: Non-PCI bridge %pOF is missing address format\n",
np);
ret = process_ISA_OF_ranges(np, 0);
if (ret)
return;
}
/* Check it's a supported address format */
if (na != 2 || ns != 1) {
pr_warn("ISA: Non-PCI bridge %pOF has unsupported address format\n",
np);
return;
}
rs = na + ns + pna;
/* Grab the ranges property */
ranges = of_get_property(np, "ranges", &rlen);
if (ranges == NULL || rlen < rs) {
pr_warn("ISA: Non-PCI bridge %pOF has absent or invalid ranges\n",
np);
return;
}
/* Parse it. We are only looking for IO space */
for (i = 0; (i + rs - 1) < rlen; i += rs) {
if (be32_to_cpup(ranges + i) != 1)
continue;
cbase = be32_to_cpup(ranges + i + 1);
size = of_read_number(ranges + i + na + pna, ns);
pbasep = ranges + i + na;
break;
}
/* Got something ? */
if (!size || !pbasep) {
pr_warn("ISA: Non-PCI bridge %pOF has no usable IO range\n",
np);
return;
}
/* Align size and make sure it's cropped to 64K */
size = PAGE_ALIGN(size);
if (size > 0x10000)
size = 0x10000;
/* Map pbase */
pbase = of_translate_address(np, pbasep);
if (pbase == OF_BAD_ADDR) {
pr_warn("ISA: Non-PCI bridge %pOF failed to translate IO base\n",
np);
return;
}
/* We need page alignment */
if ((cbase & ~PAGE_MASK) || (pbase & ~PAGE_MASK)) {
pr_warn("ISA: Non-PCI bridge %pOF has non aligned IO range\n",
np);
return;
}
/* Got it */
isa_bridge_devnode = np;
@ -263,7 +172,6 @@ void __init isa_bridge_init_non_pci(struct device_node *np)
* and map it
*/
isa_io_base = ISA_IO_BASE;
remap_isa_base(pbase, size);
pr_debug("ISA: Non-PCI bridge is %pOF\n", np);
}
@ -282,7 +190,7 @@ static void isa_bridge_find_late(struct pci_dev *pdev,
isa_bridge_pcidev = pdev;
/* Now parse the "ranges" property and setup the ISA mapping */
pci_process_ISA_OF_ranges(devnode, hose->io_base_phys);
process_ISA_OF_ranges(devnode, hose->io_base_phys);
/* Set the global ISA io base to indicate we have an ISA bridge */
isa_io_base = ISA_IO_BASE;

10
arch/powerpc/kernel/legacy_serial.c
View File

@ -171,15 +171,15 @@ static int __init add_legacy_soc_port(struct device_node *np,
/* We only support ports that have a clock frequency properly
* encoded in the device-tree.
*/
if (of_get_property(np, "clock-frequency", NULL) == NULL)
if (!of_property_present(np, "clock-frequency"))
return -1;
/* if reg-offset don't try to use it */
if ((of_get_property(np, "reg-offset", NULL) != NULL))
if (of_property_present(np, "reg-offset"))
return -1;
/* if rtas uses this device, don't try to use it as well */
if (of_get_property(np, "used-by-rtas", NULL) != NULL)
if (of_property_read_bool(np, "used-by-rtas"))
return -1;
/* Get the address */
@ -237,7 +237,7 @@ static int __init add_legacy_isa_port(struct device_node *np,
* Note: Don't even try on P8 lpc, we know it's not directly mapped
*/
if (!of_device_is_compatible(isa_brg, "ibm,power8-lpc") ||
of_get_property(isa_brg, "ranges", NULL)) {
of_property_present(isa_brg, "ranges")) {
taddr = of_translate_address(np, reg);
if (taddr == OF_BAD_ADDR)
taddr = 0;
@ -268,7 +268,7 @@ static int __init add_legacy_pci_port(struct device_node *np,
* compatible UARTs on PCI need all sort of quirks (port offsets
* etc...) that this code doesn't know about
*/
if (of_get_property(np, "clock-frequency", NULL) == NULL)
if (!of_property_present(np, "clock-frequency"))
return -1;
/* Get the PCI address. Assume BAR 0 */

2
arch/powerpc/kernel/misc_64.S
View File

@ -432,7 +432,7 @@ _GLOBAL(kexec_sequence)
1:
/* copy dest pages, flush whole dest image */
mr r3,r29
bl kexec_copy_flush /* (image) */
bl CFUNC(kexec_copy_flush) /* (image) */
/* turn off mmu now if not done earlier */
cmpdi r26,0

379
arch/powerpc/kernel/module_64.c
View File

@ -101,32 +101,45 @@ static unsigned long stub_func_addr(func_desc_t func)
/* Like PPC32, we need little trampolines to do > 24-bit jumps (into
the kernel itself). But on PPC64, these need to be used for every
jump, actually, to reset r2 (TOC+0x8000). */
struct ppc64_stub_entry
{
/* 28 byte jump instruction sequence (7 instructions). We only
* need 6 instructions on ABIv2 but we always allocate 7 so
* so we don't have to modify the trampoline load instruction. */
struct ppc64_stub_entry {
/*
* 28 byte jump instruction sequence (7 instructions) that can
* hold ppc64_stub_insns or stub_insns. Must be 8-byte aligned
* with PCREL kernels that use prefix instructions in the stub.
*/
u32 jump[7];
/* Used by ftrace to identify stubs */
u32 magic;
/* Data for the above code */
func_desc_t funcdata;
} __aligned(8);
struct ppc64_got_entry {
u64 addr;
};
/*
* PPC64 uses 24 bit jumps, but we need to jump into other modules or
* the kernel which may be further. So we jump to a stub.
*
* For ELFv1 we need to use this to set up the new r2 value (aka TOC
* pointer). For ELFv2 it's the callee's responsibility to set up the
* new r2, but for both we need to save the old r2.
* Target address and TOC are loaded from function descriptor in the
* ppc64_stub_entry.
*
* We could simply patch the new r2 value and function pointer into
* the stub, but it's significantly shorter to put these values at the
* end of the stub code, and patch the stub address (32-bits relative
* to the TOC ptr, r2) into the stub.
* r12 is used to generate the target address, which is required for the
* ELFv2 global entry point calling convention.
*
* TOC handling:
* - PCREL does not have a TOC.
* - ELFv2 non-PCREL just has to save r2, the callee is responsible for
* setting its own TOC pointer at the global entry address.
* - ELFv1 must load the new TOC pointer from the function descriptor.
*/
static u32 ppc64_stub_insns[] = {
#ifdef CONFIG_PPC_KERNEL_PCREL
/* pld r12,addr */
PPC_PREFIX_8LS | __PPC_PRFX_R(1),
PPC_INST_PLD | ___PPC_RT(_R12),
#else
PPC_RAW_ADDIS(_R11, _R2, 0),
PPC_RAW_ADDI(_R11, _R11, 0),
/* Save current r2 value in magic place on the stack. */
@ -135,14 +148,18 @@ static u32 ppc64_stub_insns[] = {
#ifdef CONFIG_PPC64_ELF_ABI_V1
/* Set up new r2 from function descriptor */
PPC_RAW_LD(_R2, _R11, 40),
#endif
#endif
PPC_RAW_MTCTR(_R12),
PPC_RAW_BCTR(),
};
/* Count how many different 24-bit relocations (different symbol,
different addend) */
static unsigned int count_relocs(const Elf64_Rela *rela, unsigned int num)
/*
* Count how many different r_type relocations (different symbol,
* different addend).
*/
static unsigned int count_relocs(const Elf64_Rela *rela, unsigned int num,
unsigned long r_type)
{
unsigned int i, r_info, r_addend, _count_relocs;
@ -151,8 +168,8 @@ static unsigned int count_relocs(const Elf64_Rela *rela, unsigned int num)
r_info = 0;
r_addend = 0;
for (i = 0; i < num; i++)
/* Only count 24-bit relocs, others don't need stubs */
if (ELF64_R_TYPE(rela[i].r_info) == R_PPC_REL24 &&
/* Only count r_type relocs, others don't need stubs */
if (ELF64_R_TYPE(rela[i].r_info) == r_type &&
(r_info != ELF64_R_SYM(rela[i].r_info) ||
r_addend != rela[i].r_addend)) {
_count_relocs++;
@ -213,7 +230,14 @@ static unsigned long get_stubs_size(const Elf64_Ehdr *hdr,
relocs += count_relocs((void *)sechdrs[i].sh_addr,
sechdrs[i].sh_size
/ sizeof(Elf64_Rela));
/ sizeof(Elf64_Rela),
R_PPC_REL24);
#ifdef CONFIG_PPC_KERNEL_PCREL
relocs += count_relocs((void *)sechdrs[i].sh_addr,
sechdrs[i].sh_size
/ sizeof(Elf64_Rela),
R_PPC64_REL24_NOTOC);
#endif
}
}
@ -230,6 +254,95 @@ static unsigned long get_stubs_size(const Elf64_Ehdr *hdr,
return relocs * sizeof(struct ppc64_stub_entry);
}
#ifdef CONFIG_PPC_KERNEL_PCREL
static int count_pcpu_relocs(const Elf64_Shdr *sechdrs,
const Elf64_Rela *rela, unsigned int num,
unsigned int symindex, unsigned int pcpu)
{
unsigned int i, r_info, r_addend, _count_relocs;
_count_relocs = 0;
r_info = 0;
r_addend = 0;
for (i = 0; i < num; i++) {
Elf64_Sym *sym;
/* This is the symbol it is referring to */
sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
+ ELF64_R_SYM(rela[i].r_info);
if (sym->st_shndx == pcpu &&
(r_info != ELF64_R_SYM(rela[i].r_info) ||
r_addend != rela[i].r_addend)) {
_count_relocs++;
r_info = ELF64_R_SYM(rela[i].r_info);
r_addend = rela[i].r_addend;
}
}
return _count_relocs;
}
/* Get size of potential GOT required. */
static unsigned long get_got_size(const Elf64_Ehdr *hdr,
const Elf64_Shdr *sechdrs,
struct module *me)
{
/* One extra reloc so it's always 0-addr terminated */
unsigned long relocs = 1;
unsigned int i, symindex = 0;
for (i = 1; i < hdr->e_shnum; i++) {
if (sechdrs[i].sh_type == SHT_SYMTAB) {
symindex = i;
break;
}
}
WARN_ON_ONCE(!symindex);
/* Every relocated section... */
for (i = 1; i < hdr->e_shnum; i++) {
if (sechdrs[i].sh_type == SHT_RELA) {
pr_debug("Found relocations in section %u\n", i);
pr_debug("Ptr: %p. Number: %llu\n", (void *)sechdrs[i].sh_addr,
sechdrs[i].sh_size / sizeof(Elf64_Rela));
/*
* Sort the relocation information based on a symbol and
* addend key. This is a stable O(n*log n) complexity
* algorithm but it will reduce the complexity of
* count_relocs() to linear complexity O(n)
*/
sort((void *)sechdrs[i].sh_addr,
sechdrs[i].sh_size / sizeof(Elf64_Rela),
sizeof(Elf64_Rela), relacmp, NULL);
relocs += count_relocs((void *)sechdrs[i].sh_addr,
sechdrs[i].sh_size
/ sizeof(Elf64_Rela),
R_PPC64_GOT_PCREL34);
/*
* Percpu data access typically gets linked with
* REL34 relocations, but the percpu section gets
* moved at load time and requires that to be
* converted to GOT linkage.
*/
if (IS_ENABLED(CONFIG_SMP) && symindex)
relocs += count_pcpu_relocs(sechdrs,
(void *)sechdrs[i].sh_addr,
sechdrs[i].sh_size
/ sizeof(Elf64_Rela),
symindex, me->arch.pcpu_section);
}
}
pr_debug("Looks like a total of %lu GOT entries, max\n", relocs);
return relocs * sizeof(struct ppc64_got_entry);
}
#else /* CONFIG_PPC_KERNEL_PCREL */
/* Still needed for ELFv2, for .TOC. */
static void dedotify_versions(struct modversion_info *vers,
unsigned long size)
@ -279,6 +392,7 @@ static Elf64_Sym *find_dot_toc(Elf64_Shdr *sechdrs,
}
return NULL;
}
#endif /* CONFIG_PPC_KERNEL_PCREL */
bool module_init_section(const char *name)
{
@ -297,6 +411,15 @@ int module_frob_arch_sections(Elf64_Ehdr *hdr,
for (i = 1; i < hdr->e_shnum; i++) {
if (strcmp(secstrings + sechdrs[i].sh_name, ".stubs") == 0)
me->arch.stubs_section = i;
#ifdef CONFIG_PPC_KERNEL_PCREL
else if (strcmp(secstrings + sechdrs[i].sh_name, ".data..percpu") == 0)
me->arch.pcpu_section = i;
else if (strcmp(secstrings + sechdrs[i].sh_name, ".mygot") == 0) {
me->arch.got_section = i;
if (sechdrs[i].sh_addralign < 8)
sechdrs[i].sh_addralign = 8;
}
#else
else if (strcmp(secstrings + sechdrs[i].sh_name, ".toc") == 0) {
me->arch.toc_section = i;
if (sechdrs[i].sh_addralign < 8)
@ -311,6 +434,7 @@ int module_frob_arch_sections(Elf64_Ehdr *hdr,
sechdrs[i].sh_size / sizeof(Elf64_Sym),
(void *)hdr
+ sechdrs[sechdrs[i].sh_link].sh_offset);
#endif
}
if (!me->arch.stubs_section) {
@ -318,26 +442,47 @@ int module_frob_arch_sections(Elf64_Ehdr *hdr,
return -ENOEXEC;
}
#ifdef CONFIG_PPC_KERNEL_PCREL
if (!me->arch.got_section) {
pr_err("%s: doesn't contain .mygot.\n", me->name);
return -ENOEXEC;
}
/* Override the got size */
sechdrs[me->arch.got_section].sh_size = get_got_size(hdr, sechdrs, me);
#else
/* If we don't have a .toc, just use .stubs. We need to set r2
to some reasonable value in case the module calls out to
other functions via a stub, or if a function pointer escapes
the module by some means. */
if (!me->arch.toc_section)
me->arch.toc_section = me->arch.stubs_section;
#endif
/* Override the stubs size */
sechdrs[me->arch.stubs_section].sh_size = get_stubs_size(hdr, sechdrs);
return 0;
}
#ifdef CONFIG_MPROFILE_KERNEL
static u32 stub_insns[] = {
#ifdef CONFIG_PPC_KERNEL_PCREL
PPC_RAW_LD(_R12, _R13, offsetof(struct paca_struct, kernelbase)),
PPC_RAW_NOP(), /* align the prefix insn */
/* paddi r12,r12,addr */
PPC_PREFIX_MLS | __PPC_PRFX_R(0),
PPC_INST_PADDI | ___PPC_RT(_R12) | ___PPC_RA(_R12),
PPC_RAW_MTCTR(_R12),
PPC_RAW_BCTR(),
#else
PPC_RAW_LD(_R12, _R13, offsetof(struct paca_struct, kernel_toc)),
PPC_RAW_ADDIS(_R12, _R12, 0),
PPC_RAW_ADDI(_R12, _R12, 0),
PPC_RAW_MTCTR(_R12),
PPC_RAW_BCTR(),
#endif
};
/*
@ -358,18 +503,37 @@ static inline int create_ftrace_stub(struct ppc64_stub_entry *entry,
{
long reladdr;
memcpy(entry->jump, stub_insns, sizeof(stub_insns));
/* Stub uses address relative to kernel toc (from the paca) */
reladdr = addr - kernel_toc_addr();
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
pr_err("%s: Address of %ps out of range of kernel_toc.\n",
me->name, (void *)addr);
if ((unsigned long)entry->jump % 8 != 0) {
pr_err("%s: Address of stub entry is not 8-byte aligned\n", me->name);
return 0;
}
entry->jump[1] |= PPC_HA(reladdr);
entry->jump[2] |= PPC_LO(reladdr);
BUILD_BUG_ON(sizeof(stub_insns) > sizeof(entry->jump));
memcpy(entry->jump, stub_insns, sizeof(stub_insns));
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL)) {
/* Stub uses address relative to kernel base (from the paca) */
reladdr = addr - local_paca->kernelbase;
if (reladdr > 0x1FFFFFFFFL || reladdr < -0x200000000L) {
pr_err("%s: Address of %ps out of range of 34-bit relative address.\n",
me->name, (void *)addr);
return 0;
}
entry->jump[2] |= IMM_H18(reladdr);
entry->jump[3] |= IMM_L(reladdr);
} else {
/* Stub uses address relative to kernel toc (from the paca) */
reladdr = addr - kernel_toc_addr();
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
pr_err("%s: Address of %ps out of range of kernel_toc.\n",
me->name, (void *)addr);
return 0;
}
entry->jump[1] |= PPC_HA(reladdr);
entry->jump[2] |= PPC_LO(reladdr);
}
/* Even though we don't use funcdata in the stub, it's needed elsewhere. */
entry->funcdata = func_desc(addr);
@ -415,7 +579,11 @@ static bool is_mprofile_ftrace_call(const char *name)
*/
static inline unsigned long my_r2(const Elf64_Shdr *sechdrs, struct module *me)
{
#ifndef CONFIG_PPC_KERNEL_PCREL
return (sechdrs[me->arch.toc_section].sh_addr & ~0xfful) + 0x8000;
#else
return -1;
#endif
}
/* Patch stub to reference function and correct r2 value. */
@ -432,28 +600,53 @@ static inline int create_stub(const Elf64_Shdr *sechdrs,
if (is_mprofile_ftrace_call(name))
return create_ftrace_stub(entry, addr, me);
if ((unsigned long)entry->jump % 8 != 0) {
pr_err("%s: Address of stub entry is not 8-byte aligned\n", me->name);
return 0;
}
BUILD_BUG_ON(sizeof(ppc64_stub_insns) > sizeof(entry->jump));
for (i = 0; i < ARRAY_SIZE(ppc64_stub_insns); i++) {
if (patch_instruction(&entry->jump[i],
ppc_inst(ppc64_stub_insns[i])))
return 0;
}
/* Stub uses address relative to r2. */
reladdr = (unsigned long)entry - my_r2(sechdrs, me);
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
pr_err("%s: Address %p of stub out of range of %p.\n",
me->name, (void *)reladdr, (void *)my_r2);
return 0;
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL)) {
/* Stub uses address relative to itself! */
reladdr = 0 + offsetof(struct ppc64_stub_entry, funcdata);
BUILD_BUG_ON(reladdr != 32);
if (reladdr > 0x1FFFFFFFFL || reladdr < -0x200000000L) {
pr_err("%s: Address of %p out of range of 34-bit relative address.\n",
me->name, (void *)reladdr);
return 0;
}
pr_debug("Stub %p get data from reladdr %li\n", entry, reladdr);
/* May not even need this if we're relative to 0 */
if (patch_instruction(&entry->jump[0],
ppc_inst_prefix(entry->jump[0] | IMM_H18(reladdr),
entry->jump[1] | IMM_L(reladdr))))
return 0;
} else {
/* Stub uses address relative to r2. */
reladdr = (unsigned long)entry - my_r2(sechdrs, me);
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
pr_err("%s: Address %p of stub out of range of %p.\n",
me->name, (void *)reladdr, (void *)my_r2);
return 0;
}
pr_debug("Stub %p get data from reladdr %li\n", entry, reladdr);
if (patch_instruction(&entry->jump[0],
ppc_inst(entry->jump[0] | PPC_HA(reladdr))))
return 0;
if (patch_instruction(&entry->jump[1],
ppc_inst(entry->jump[1] | PPC_LO(reladdr))))
return 0;
}
pr_debug("Stub %p get data from reladdr %li\n", entry, reladdr);
if (patch_instruction(&entry->jump[0],
ppc_inst(entry->jump[0] | PPC_HA(reladdr))))
return 0;
if (patch_instruction(&entry->jump[1],
ppc_inst(entry->jump[1] | PPC_LO(reladdr))))
return 0;
// func_desc_t is 8 bytes if ABIv2, else 16 bytes
desc = func_desc(addr);
@ -497,6 +690,37 @@ static unsigned long stub_for_addr(const Elf64_Shdr *sechdrs,
return (unsigned long)&stubs[i];
}
#ifdef CONFIG_PPC_KERNEL_PCREL
/* Create GOT to load the location described in this ptr */
static unsigned long got_for_addr(const Elf64_Shdr *sechdrs,
unsigned long addr,
struct module *me,
const char *name)
{
struct ppc64_got_entry *got;
unsigned int i, num_got;
if (!IS_ENABLED(CONFIG_PPC_KERNEL_PCREL))
return addr;
num_got = sechdrs[me->arch.got_section].sh_size / sizeof(*got);
/* Find this stub, or if that fails, the next avail. entry */
got = (void *)sechdrs[me->arch.got_section].sh_addr;
for (i = 0; got[i].addr; i++) {
if (WARN_ON(i >= num_got))
return 0;
if (got[i].addr == addr)
return (unsigned long)&got[i];
}
got[i].addr = addr;
return (unsigned long)&got[i];
}
#endif
/* We expect a noop next: if it is, replace it with instruction to
restore r2. */
static int restore_r2(const char *name, u32 *instruction, struct module *me)
@ -504,6 +728,9 @@ static int restore_r2(const char *name, u32 *instruction, struct module *me)
u32 *prev_insn = instruction - 1;
u32 insn_val = *instruction;
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL))
return 0;
if (is_mprofile_ftrace_call(name))
return 0;
@ -549,6 +776,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
pr_debug("Applying ADD relocate section %u to %u\n", relsec,
sechdrs[relsec].sh_info);
#ifndef CONFIG_PPC_KERNEL_PCREL
/* First time we're called, we can fix up .TOC. */
if (!me->arch.toc_fixed) {
sym = find_dot_toc(sechdrs, strtab, symindex);
@ -558,7 +786,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
sym->st_value = my_r2(sechdrs, me);
me->arch.toc_fixed = true;
}
#endif
for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rela); i++) {
/* This is where to make the change */
location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
@ -586,6 +814,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
*(unsigned long *)location = value;
break;
#ifndef CONFIG_PPC_KERNEL_PCREL
case R_PPC64_TOC:
*(unsigned long *)location = my_r2(sechdrs, me);
break;
@ -645,8 +874,13 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
= (*((uint16_t *) location) & ~0xffff)
| (value & 0xffff);
break;
#endif
case R_PPC_REL24:
#ifdef CONFIG_PPC_KERNEL_PCREL
/* PCREL still generates REL24 for mcount */
case R_PPC64_REL24_NOTOC:
#endif
/* FIXME: Handle weak symbols here --RR */
if (sym->st_shndx == SHN_UNDEF ||
sym->st_shndx == SHN_LIVEPATCH) {
@ -694,6 +928,47 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
*(u32 *)location = value;
break;
#ifdef CONFIG_PPC_KERNEL_PCREL
case R_PPC64_PCREL34: {
unsigned long absvalue = value;
/* Convert value to relative */
value -= (unsigned long)location;
if (value + 0x200000000 > 0x3ffffffff) {
if (sym->st_shndx != me->arch.pcpu_section) {
pr_err("%s: REL34 %li out of range!\n",
me->name, (long)value);
return -ENOEXEC;
}
/*
* per-cpu section is special cased because
* it is moved during loading, so has to be
* converted to use GOT.
*/
value = got_for_addr(sechdrs, absvalue, me,
strtab + sym->st_name);
if (!value)
return -ENOENT;
value -= (unsigned long)location;
/* Turn pla into pld */
if (patch_instruction((u32 *)location,
ppc_inst_prefix((*(u32 *)location & ~0x02000000),
(*((u32 *)location + 1) & ~0xf8000000) | 0xe4000000)))
return -EFAULT;
}
if (patch_instruction((u32 *)location,
ppc_inst_prefix((*(u32 *)location & ~0x3ffff) | IMM_H18(value),
(*((u32 *)location + 1) & ~0xffff) | IMM_L(value))))
return -EFAULT;
break;
}
#else
case R_PPC64_TOCSAVE:
/*
* Marker reloc indicates we don't have to save r2.
@ -701,8 +976,12 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
* it.
*/
break;
#endif
case R_PPC64_ENTRY:
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL))
break;
/*
* Optimize ELFv2 large code model entry point if
* the TOC is within 2GB range of current location.
@ -745,6 +1024,20 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
| (value & 0xffff);
break;
#ifdef CONFIG_PPC_KERNEL_PCREL
case R_PPC64_GOT_PCREL34:
value = got_for_addr(sechdrs, value, me,
strtab + sym->st_name);
if (!value)
return -ENOENT;
value -= (unsigned long)location;
((uint32_t *)location)[0] = (((uint32_t *)location)[0] & ~0x3ffff) |
((value >> 16) & 0x3ffff);
((uint32_t *)location)[1] = (((uint32_t *)location)[1] & ~0xffff) |
(value & 0xffff);
break;
#endif
default:
pr_err("%s: Unknown ADD relocation: %lu\n",
me->name,

2
arch/powerpc/kernel/paca.c
View File

@ -191,7 +191,9 @@ void __init initialise_paca(struct paca_struct *new_paca, int cpu)
#endif
new_paca->lock_token = 0x8000;
new_paca->paca_index = cpu;
#ifndef CONFIG_PPC_KERNEL_PCREL
new_paca->kernel_toc = kernel_toc_addr();
#endif
new_paca->kernelbase = (unsigned long) _stext;
/* Only set MSR:IR/DR when MMU is initialized */
new_paca->kernel_msr = MSR_KERNEL & ~(MSR_IR | MSR_DR);

2
arch/powerpc/kernel/pci_64.c
View File

@ -73,7 +73,7 @@ static int __init pcibios_init(void)
return 0;
}
subsys_initcall(pcibios_init);
subsys_initcall_sync(pcibios_init);
int pcibios_unmap_io_space(struct pci_bus *bus)
{

126
arch/powerpc/kernel/process.c
View File

@ -1630,7 +1630,7 @@ void arch_setup_new_exec(void)
}
#ifdef CONFIG_PPC64
/**
/*
* Assign a TIDR (thread ID) for task @t and set it in the thread
* structure. For now, we only support setting TIDR for 'current' task.
*
@ -1738,68 +1738,83 @@ static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
*/
int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
{
unsigned long clone_flags = args->flags;
unsigned long usp = args->stack;
unsigned long tls = args->tls;
struct pt_regs *childregs, *kregs;
struct pt_regs *kregs; /* Switch frame regs */
extern void ret_from_fork(void);
extern void ret_from_fork_scv(void);
extern void ret_from_kernel_thread(void);
extern void ret_from_kernel_user_thread(void);
extern void start_kernel_thread(void);
void (*f)(void);
unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
struct thread_info *ti = task_thread_info(p);
#ifdef CONFIG_HAVE_HW_BREAKPOINT
int i;
#endif
klp_init_thread_info(p);
/* Create initial stack frame. */
sp -= STACK_USER_INT_FRAME_SIZE;
*(unsigned long *)(sp + STACK_INT_FRAME_MARKER) = STACK_FRAME_REGS_MARKER;
/* Copy registers */
childregs = (struct pt_regs *)(sp + STACK_INT_FRAME_REGS);
if (unlikely(args->fn)) {
if (unlikely(p->flags & PF_KTHREAD)) {
/* kernel thread */
/* Create initial minimum stack frame. */
sp -= STACK_FRAME_MIN_SIZE;
((unsigned long *)sp)[0] = 0;
memset(childregs, 0, sizeof(struct pt_regs));
childregs->gpr[1] = sp + STACK_USER_INT_FRAME_SIZE;
/* function */
if (args->fn)
childregs->gpr[14] = ppc_function_entry((void *)args->fn);
#ifdef CONFIG_PPC64
clear_tsk_thread_flag(p, TIF_32BIT);
childregs->softe = IRQS_ENABLED;
#endif
childregs->gpr[15] = (unsigned long)args->fn_arg;
f = start_kernel_thread;
p->thread.regs = NULL; /* no user register state */
ti->flags |= _TIF_RESTOREALL;
f = ret_from_kernel_thread;
clear_tsk_compat_task(p);
} else {
/* user thread */
struct pt_regs *regs = current_pt_regs();
*childregs = *regs;
if (usp)
childregs->gpr[1] = usp;
((unsigned long *)sp)[0] = childregs->gpr[1];
p->thread.regs = childregs;
/* 64s sets this in ret_from_fork */
if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64))
childregs->gpr[3] = 0; /* Result from fork() */
if (clone_flags & CLONE_SETTLS) {
if (!is_32bit_task())
childregs->gpr[13] = tls;
struct pt_regs *childregs;
/* Create initial user return stack frame. */
sp -= STACK_USER_INT_FRAME_SIZE;
*(unsigned long *)(sp + STACK_INT_FRAME_MARKER) = STACK_FRAME_REGS_MARKER;
childregs = (struct pt_regs *)(sp + STACK_INT_FRAME_REGS);
if (unlikely(args->fn)) {
/*
* A user space thread, but it first runs a kernel
* thread, and then returns as though it had called
* execve rather than fork, so user regs will be
* filled in (e.g., by kernel_execve()).
*/
((unsigned long *)sp)[0] = 0;
memset(childregs, 0, sizeof(struct pt_regs));
#ifdef CONFIG_PPC64
childregs->softe = IRQS_ENABLED;
#endif
f = ret_from_kernel_user_thread;
} else {
struct pt_regs *regs = current_pt_regs();
unsigned long clone_flags = args->flags;
unsigned long usp = args->stack;
/* Copy registers */
*childregs = *regs;
if (usp)
childregs->gpr[1] = usp;
((unsigned long *)sp)[0] = childregs->gpr[1];
#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
WARN_ON_ONCE(childregs->softe != IRQS_ENABLED);
#endif
if (clone_flags & CLONE_SETTLS) {
unsigned long tls = args->tls;
if (!is_32bit_task())
childregs->gpr[13] = tls;
else
childregs->gpr[2] = tls;
}
if (trap_is_scv(regs))
f = ret_from_fork_scv;
else
childregs->gpr[2] = tls;
f = ret_from_fork;
}
if (trap_is_scv(regs))
f = ret_from_fork_scv;
else
f = ret_from_fork;
childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
p->thread.regs = childregs;
}
childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
/*
* The way this works is that at some point in the future
@ -1813,6 +1828,16 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
sp -= STACK_SWITCH_FRAME_SIZE;
((unsigned long *)sp)[0] = sp + STACK_SWITCH_FRAME_SIZE;
kregs = (struct pt_regs *)(sp + STACK_SWITCH_FRAME_REGS);
kregs->nip = ppc_function_entry(f);
if (unlikely(args->fn)) {
/*
* Put kthread fn, arg parameters in non-volatile GPRs in the
* switch frame so they are loaded by _switch before it returns
* to ret_from_kernel_thread.
*/
kregs->gpr[14] = ppc_function_entry((void *)args->fn);
kregs->gpr[15] = (unsigned long)args->fn_arg;
}
p->thread.ksp = sp;
#ifdef CONFIG_HAVE_HW_BREAKPOINT
@ -1840,22 +1865,9 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
p->thread.dscr_inherit = current->thread.dscr_inherit;
p->thread.dscr = mfspr(SPRN_DSCR);
}
if (cpu_has_feature(CPU_FTR_HAS_PPR))
childregs->ppr = DEFAULT_PPR;
p->thread.tidr = 0;
#endif
/*
* Run with the current AMR value of the kernel
*/
#ifdef CONFIG_PPC_PKEY
if (mmu_has_feature(MMU_FTR_BOOK3S_KUAP))
kregs->amr = AMR_KUAP_BLOCKED;
if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP))
kregs->iamr = AMR_KUEP_BLOCKED;
#endif
kregs->nip = ppc_function_entry(f);
return 0;
}

54
arch/powerpc/kernel/rtas.c
View File

@ -16,6 +16,7 @@
#include <linux/init.h>
#include <linux/kconfig.h>
#include <linux/kernel.h>
#include <linux/lockdep.h>
#include <linux/memblock.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
@ -68,7 +69,7 @@ struct rtas_filter {
* functions are believed to have no users on
* ppc64le, and we want to keep it that way. It does
* not make sense for this to be set when @filter
* is false.
* is NULL.
*/
struct rtas_function {
s32 token;
@ -453,6 +454,16 @@ static struct rtas_function rtas_function_table[] __ro_after_init = {
},
};
/*
* Nearly all RTAS calls need to be serialized. All uses of the
* default rtas_args block must hold rtas_lock.
*
* Exceptions to the RTAS serialization requirement (e.g. stop-self)
* must use a separate rtas_args structure.
*/
static DEFINE_RAW_SPINLOCK(rtas_lock);
static struct rtas_args rtas_args;
/**
* rtas_function_token() - RTAS function token lookup.
* @handle: Function handle, e.g. RTAS_FN_EVENT_SCAN.
@ -560,6 +571,9 @@ static void __do_enter_rtas(struct rtas_args *args)
static void __do_enter_rtas_trace(struct rtas_args *args)
{
const char *name = NULL;
if (args == &rtas_args)
lockdep_assert_held(&rtas_lock);
/*
* If the tracepoints that consume the function name aren't
* active, avoid the lookup.
@ -619,16 +633,6 @@ static void do_enter_rtas(struct rtas_args *args)
struct rtas_t rtas;
/*
* Nearly all RTAS calls need to be serialized. All uses of the
* default rtas_args block must hold rtas_lock.
*
* Exceptions to the RTAS serialization requirement (e.g. stop-self)
* must use a separate rtas_args structure.
*/
static DEFINE_RAW_SPINLOCK(rtas_lock);
static struct rtas_args rtas_args;
DEFINE_SPINLOCK(rtas_data_buf_lock);
EXPORT_SYMBOL_GPL(rtas_data_buf_lock);
@ -951,6 +955,8 @@ static char *__fetch_rtas_last_error(char *altbuf)
u32 bufsz;
char *buf = NULL;
lockdep_assert_held(&rtas_lock);
if (token == -1)
return NULL;
@ -981,7 +987,7 @@ static char *__fetch_rtas_last_error(char *altbuf)
buf = kmalloc(RTAS_ERROR_LOG_MAX, GFP_ATOMIC);
}
if (buf)
memcpy(buf, rtas_err_buf, RTAS_ERROR_LOG_MAX);
memmove(buf, rtas_err_buf, RTAS_ERROR_LOG_MAX);
}
return buf;
@ -1016,6 +1022,23 @@ va_rtas_call_unlocked(struct rtas_args *args, int token, int nargs, int nret,
do_enter_rtas(args);
}
/**
* rtas_call_unlocked() - Invoke an RTAS firmware function without synchronization.
* @args: RTAS parameter block to be used for the call, must obey RTAS addressing
* constraints.
* @token: Identifies the function being invoked.
* @nargs: Number of input parameters. Does not include token.
* @nret: Number of output parameters, including the call status.
* @....: List of @nargs input parameters.
*
* Invokes the RTAS function indicated by @token, which the caller
* should obtain via rtas_function_token().
*
* This function is similar to rtas_call(), but must be used with a
* limited set of RTAS calls specifically exempted from the general
* requirement that only one RTAS call may be in progress at any
* time. Examples include stop-self and ibm,nmi-interlock.
*/
void rtas_call_unlocked(struct rtas_args *args, int token, int nargs, int nret, ...)
{
va_list list;
@ -1091,6 +1114,7 @@ static bool token_is_restricted_errinjct(s32 token)
*/
int rtas_call(int token, int nargs, int nret, int *outputs, ...)
{
struct pin_cookie cookie;
va_list list;
int i;
unsigned long flags;
@ -1117,6 +1141,8 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...)
}
raw_spin_lock_irqsave(&rtas_lock, flags);
cookie = lockdep_pin_lock(&rtas_lock);
/* We use the global rtas args buffer */
args = &rtas_args;
@ -1134,6 +1160,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...)
outputs[i] = be32_to_cpu(args->rets[i + 1]);
ret = (nret > 0) ? be32_to_cpu(args->rets[0]) : 0;
lockdep_unpin_lock(&rtas_lock, cookie);
raw_spin_unlock_irqrestore(&rtas_lock, flags);
if (buff_copy) {
@ -1765,6 +1792,7 @@ static bool block_rtas_call(int token, int nargs,
/* We assume to be passed big endian arguments */
SYSCALL_DEFINE1(rtas, struct rtas_args __user *, uargs)
{
struct pin_cookie cookie;
struct rtas_args args;
unsigned long flags;
char *buff_copy, *errbuf = NULL;
@ -1833,6 +1861,7 @@ SYSCALL_DEFINE1(rtas, struct rtas_args __user *, uargs)
buff_copy = get_errorlog_buffer();
raw_spin_lock_irqsave(&rtas_lock, flags);
cookie = lockdep_pin_lock(&rtas_lock);
rtas_args = args;
do_enter_rtas(&rtas_args);
@ -1843,6 +1872,7 @@ SYSCALL_DEFINE1(rtas, struct rtas_args __user *, uargs)
if (be32_to_cpu(args.rets[0]) == -1)
errbuf = __fetch_rtas_last_error(buff_copy);
lockdep_unpin_lock(&rtas_lock, cookie);
raw_spin_unlock_irqrestore(&rtas_lock, flags);
if (buff_copy) {

13
arch/powerpc/kernel/setup-common.c
View File

@ -630,13 +630,14 @@ static __init void probe_machine(void)
for (machine_id = &__machine_desc_start;
machine_id < &__machine_desc_end;
machine_id++) {
DBG(" %s ...", machine_id->name);
DBG(" %s ...\n", machine_id->name);
if (machine_id->compatible && !of_machine_is_compatible(machine_id->compatible))
continue;
memcpy(&ppc_md, machine_id, sizeof(struct machdep_calls));
if (ppc_md.probe()) {
DBG(" match !\n");
break;
}
DBG("\n");
if (ppc_md.probe && !ppc_md.probe())
continue;
DBG(" %s match !\n", machine_id->name);
break;
}
/* What can we do if we didn't find ? */
if (machine_id >= &__machine_desc_end) {

6
arch/powerpc/kernel/time.c
View File

@ -887,7 +887,11 @@ void __init time_init(void)
unsigned shift;
/* Normal PowerPC with timebase register */
ppc_md.calibrate_decr();
if (ppc_md.calibrate_decr)
ppc_md.calibrate_decr();
else
generic_calibrate_decr();
printk(KERN_DEBUG "time_init: decrementer frequency = %lu.%.6lu MHz\n",
ppc_tb_freq / 1000000, ppc_tb_freq % 1000000);
printk(KERN_DEBUG "time_init: processor frequency = %lu.%.6lu MHz\n",

50
arch/powerpc/kernel/trace/ftrace.c
View File

@ -194,6 +194,8 @@ __ftrace_make_nop(struct module *mod,
* get corrupted.
*
* Use a b +8 to jump over the load.
* XXX: could make PCREL depend on MPROFILE_KERNEL
* XXX: check PCREL && MPROFILE_KERNEL calling sequence
*/
if (IS_ENABLED(CONFIG_MPROFILE_KERNEL) || IS_ENABLED(CONFIG_PPC32))
pop = ppc_inst(PPC_RAW_NOP());
@ -725,6 +727,15 @@ int __init ftrace_dyn_arch_init(void)
{
int i;
unsigned int *tramp[] = { ftrace_tramp_text, ftrace_tramp_init };
#ifdef CONFIG_PPC_KERNEL_PCREL
u32 stub_insns[] = {
/* pla r12,addr */
PPC_PREFIX_MLS | __PPC_PRFX_R(1),
PPC_INST_PADDI | ___PPC_RT(_R12),
PPC_RAW_MTCTR(_R12),
PPC_RAW_BCTR()
};
#else
u32 stub_insns[] = {
PPC_RAW_LD(_R12, _R13, PACATOC),
PPC_RAW_ADDIS(_R12, _R12, 0),
@ -732,6 +743,8 @@ int __init ftrace_dyn_arch_init(void)
PPC_RAW_MTCTR(_R12),
PPC_RAW_BCTR()
};
#endif
unsigned long addr;
long reladdr;
@ -740,19 +753,36 @@ int __init ftrace_dyn_arch_init(void)
else
addr = ppc_global_function_entry((void *)ftrace_caller);
reladdr = addr - kernel_toc_addr();
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL)) {
for (i = 0; i < 2; i++) {
reladdr = addr - (unsigned long)tramp[i];
if (reladdr >= SZ_2G || reladdr < -(long)SZ_2G) {
pr_err("Address of %ps out of range of kernel_toc.\n",
if (reladdr >= (long)SZ_8G || reladdr < -(long)SZ_8G) {
pr_err("Address of %ps out of range of pcrel address.\n",
(void *)addr);
return -1;
}
memcpy(tramp[i], stub_insns, sizeof(stub_insns));
tramp[i][0] |= IMM_H18(reladdr);
tramp[i][1] |= IMM_L(reladdr);
add_ftrace_tramp((unsigned long)tramp[i]);
}
} else {
reladdr = addr - kernel_toc_addr();
if (reladdr >= (long)SZ_2G || reladdr < -(long)SZ_2G) {
pr_err("Address of %ps out of range of kernel_toc.\n",
(void *)addr);
return -1;
}
return -1;
}
for (i = 0; i < 2; i++) {
memcpy(tramp[i], stub_insns, sizeof(stub_insns));
tramp[i][1] |= PPC_HA(reladdr);
tramp[i][2] |= PPC_LO(reladdr);
add_ftrace_tramp((unsigned long)tramp[i]);
for (i = 0; i < 2; i++) {
memcpy(tramp[i], stub_insns, sizeof(stub_insns));
tramp[i][1] |= PPC_HA(reladdr);
tramp[i][2] |= PPC_LO(reladdr);
add_ftrace_tramp((unsigned long)tramp[i]);
}
}
return 0;

6
arch/powerpc/kernel/vdso/gettimeofday.S
View File

@ -38,7 +38,11 @@
.else
addi r4, r5, VDSO_DATA_OFFSET
.endif
bl DOTSYM(\funct)
#ifdef __powerpc64__
bl CFUNC(DOTSYM(\funct))
#else
bl \funct
#endif
PPC_LL r0, PPC_MIN_STKFRM + PPC_LR_STKOFF(r1)
#ifdef __powerpc64__
PPC_LL r2, PPC_MIN_STKFRM + STK_GOT(r1)

6
arch/powerpc/kernel/vector.S
View File

@ -177,9 +177,15 @@ fpone:
fphalf:
.quad 0x3fe0000000000000 /* 0.5 */
#ifdef CONFIG_PPC_KERNEL_PCREL
#define LDCONST(fr, name) \
pla r11,name@pcrel; \
lfd fr,0(r11)
#else
#define LDCONST(fr, name) \
addis r11,r2,name@toc@ha; \
lfd fr,name@toc@l(r11)
#endif
#endif
.text
/*

6
arch/powerpc/kernel/vmlinux.lds.S
View File

@ -169,12 +169,18 @@ SECTIONS
}
#else /* CONFIG_PPC32 */
#ifndef CONFIG_PPC_KERNEL_PCREL
.toc1 : AT(ADDR(.toc1) - LOAD_OFFSET) {
*(.toc1)
}
#endif
.got : AT(ADDR(.got) - LOAD_OFFSET) ALIGN(256) {
#ifdef CONFIG_PPC_KERNEL_PCREL
*(.got)
#else
*(.got .toc)
#endif
}
SOFT_MASK_TABLE(8)

64
arch/powerpc/kvm/book3s.c
View File

@ -188,10 +188,10 @@ void kvmppc_book3s_queue_irqprio(struct kvm_vcpu *vcpu, unsigned int vec)
}
EXPORT_SYMBOL_GPL(kvmppc_book3s_queue_irqprio);
void kvmppc_core_queue_machine_check(struct kvm_vcpu *vcpu, ulong flags)
void kvmppc_core_queue_machine_check(struct kvm_vcpu *vcpu, ulong srr1_flags)
{
/* might as well deliver this straight away */
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_MACHINE_CHECK, flags);
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_MACHINE_CHECK, srr1_flags);
}
EXPORT_SYMBOL_GPL(kvmppc_core_queue_machine_check);
@ -201,29 +201,29 @@ void kvmppc_core_queue_syscall(struct kvm_vcpu *vcpu)
}
EXPORT_SYMBOL(kvmppc_core_queue_syscall);
void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong flags)
void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong srr1_flags)
{
/* might as well deliver this straight away */
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_PROGRAM, flags);
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_PROGRAM, srr1_flags);
}
EXPORT_SYMBOL_GPL(kvmppc_core_queue_program);
void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu)
void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
{
/* might as well deliver this straight away */
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, 0);
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, srr1_flags);
}
void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu)
void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
{
/* might as well deliver this straight away */
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_ALTIVEC, 0);
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_ALTIVEC, srr1_flags);
}
void kvmppc_core_queue_vsx_unavail(struct kvm_vcpu *vcpu)
void kvmppc_core_queue_vsx_unavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
{
/* might as well deliver this straight away */
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_VSX, 0);
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_VSX, srr1_flags);
}
void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
@ -278,18 +278,18 @@ void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu)
kvmppc_book3s_dequeue_irqprio(vcpu, BOOK3S_INTERRUPT_EXTERNAL);
}
void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, ulong dar,
ulong flags)
void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, ulong srr1_flags,
ulong dar, ulong dsisr)
{
kvmppc_set_dar(vcpu, dar);
kvmppc_set_dsisr(vcpu, flags);
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE, 0);
kvmppc_set_dsisr(vcpu, dsisr);
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE, srr1_flags);
}
EXPORT_SYMBOL_GPL(kvmppc_core_queue_data_storage);
void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong flags)
void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong srr1_flags)
{
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_INST_STORAGE, flags);
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_INST_STORAGE, srr1_flags);
}
EXPORT_SYMBOL_GPL(kvmppc_core_queue_inst_storage);
@ -481,20 +481,42 @@ int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr, enum xlate_instdata xlid,
return r;
}
/*
* Returns prefixed instructions with the prefix in the high 32 bits
* of *inst and suffix in the low 32 bits. This is the same convention
* as used in HEIR, vcpu->arch.last_inst and vcpu->arch.emul_inst.
* Like vcpu->arch.last_inst but unlike vcpu->arch.emul_inst, each
* half of the value needs byte-swapping if the guest endianness is
* different from the host endianness.
*/
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
enum instruction_fetch_type type, u32 *inst)
enum instruction_fetch_type type, unsigned long *inst)
{
ulong pc = kvmppc_get_pc(vcpu);
int r;
u32 iw;
if (type == INST_SC)
pc -= 4;
r = kvmppc_ld(vcpu, &pc, sizeof(u32), inst, false);
if (r == EMULATE_DONE)
return r;
else
r = kvmppc_ld(vcpu, &pc, sizeof(u32), &iw, false);
if (r != EMULATE_DONE)
return EMULATE_AGAIN;
/*
* If [H]SRR1 indicates that the instruction that caused the
* current interrupt is a prefixed instruction, get the suffix.
*/
if (kvmppc_get_msr(vcpu) & SRR1_PREFIXED) {
u32 suffix;
pc += 4;
r = kvmppc_ld(vcpu, &pc, sizeof(u32), &suffix, false);
if (r != EMULATE_DONE)
return EMULATE_AGAIN;
*inst = ((u64)iw << 32) | suffix;
} else {
*inst = iw;
}
return r;
}
EXPORT_SYMBOL_GPL(kvmppc_load_last_inst);

26
arch/powerpc/kvm/book3s_64_mmu_hv.c
View File

@ -415,20 +415,25 @@ static int kvmppc_mmu_book3s_64_hv_xlate(struct kvm_vcpu *vcpu, gva_t eaddr,
* embodied here.) If the instruction isn't a load or store, then
* this doesn't return anything useful.
*/
static int instruction_is_store(unsigned int instr)
static int instruction_is_store(ppc_inst_t instr)
{
unsigned int mask;
unsigned int suffix;
mask = 0x10000000;
if ((instr & 0xfc000000) == 0x7c000000)
suffix = ppc_inst_val(instr);
if (ppc_inst_prefixed(instr))
suffix = ppc_inst_suffix(instr);
else if ((suffix & 0xfc000000) == 0x7c000000)
mask = 0x100; /* major opcode 31 */
return (instr & mask) != 0;
return (suffix & mask) != 0;
}
int kvmppc_hv_emulate_mmio(struct kvm_vcpu *vcpu,
unsigned long gpa, gva_t ea, int is_store)
{
u32 last_inst;
ppc_inst_t last_inst;
bool is_prefixed = !!(kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
/*
* Fast path - check if the guest physical address corresponds to a
@ -443,7 +448,7 @@ int kvmppc_hv_emulate_mmio(struct kvm_vcpu *vcpu,
NULL);
srcu_read_unlock(&vcpu->kvm->srcu, idx);
if (!ret) {
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + (is_prefixed ? 8 : 4));
return RESUME_GUEST;
}
}
@ -458,7 +463,16 @@ int kvmppc_hv_emulate_mmio(struct kvm_vcpu *vcpu,
/*
* WARNING: We do not know for sure whether the instruction we just
* read from memory is the same that caused the fault in the first
* place. If the instruction we read is neither an load or a store,
* place.
*
* If the fault is prefixed but the instruction is not or vice
* versa, try again so that we don't advance pc the wrong amount.
*/
if (ppc_inst_prefixed(last_inst) != is_prefixed)
return RESUME_GUEST;
/*
* If the instruction we read is neither an load or a store,
* then it can't access memory, so we don't need to worry about
* enforcing access permissions. So, assuming it is a load or
* store, we just check that its direction (load or store) is

13
arch/powerpc/kvm/book3s_64_mmu_radix.c
View File

@ -954,7 +954,9 @@ int kvmppc_book3s_radix_page_fault(struct kvm_vcpu *vcpu,
if (dsisr & DSISR_BADACCESS) {
/* Reflect to the guest as DSI */
pr_err("KVM: Got radix HV page fault with DSISR=%lx\n", dsisr);
kvmppc_core_queue_data_storage(vcpu, ea, dsisr);
kvmppc_core_queue_data_storage(vcpu,
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
ea, dsisr);
return RESUME_GUEST;
}
@ -979,7 +981,9 @@ int kvmppc_book3s_radix_page_fault(struct kvm_vcpu *vcpu,
* Bad address in guest page table tree, or other
* unusual error - reflect it to the guest as DSI.
*/
kvmppc_core_queue_data_storage(vcpu, ea, dsisr);
kvmppc_core_queue_data_storage(vcpu,
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
ea, dsisr);
return RESUME_GUEST;
}
return kvmppc_hv_emulate_mmio(vcpu, gpa, ea, writing);
@ -988,8 +992,9 @@ int kvmppc_book3s_radix_page_fault(struct kvm_vcpu *vcpu,
if (memslot->flags & KVM_MEM_READONLY) {
if (writing) {
/* give the guest a DSI */
kvmppc_core_queue_data_storage(vcpu, ea, DSISR_ISSTORE |
DSISR_PROTFAULT);
kvmppc_core_queue_data_storage(vcpu,
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
ea, DSISR_ISSTORE | DSISR_PROTFAULT);
return RESUME_GUEST;
}
kvm_ro = true;

47
arch/powerpc/kvm/book3s_hv.c
View File

@ -477,7 +477,7 @@ static void kvmppc_dump_regs(struct kvm_vcpu *vcpu)
for (r = 0; r < vcpu->arch.slb_max; ++r)
pr_err(" ESID = %.16llx VSID = %.16llx\n",
vcpu->arch.slb[r].orige, vcpu->arch.slb[r].origv);
pr_err("lpcr = %.16lx sdr1 = %.16lx last_inst = %.8x\n",
pr_err("lpcr = %.16lx sdr1 = %.16lx last_inst = %.16lx\n",
vcpu->arch.vcore->lpcr, vcpu->kvm->arch.sdr1,
vcpu->arch.last_inst);
}
@ -1415,7 +1415,7 @@ static int kvmppc_hcall_impl_hv(unsigned long cmd)
static int kvmppc_emulate_debug_inst(struct kvm_vcpu *vcpu)
{
u32 last_inst;
ppc_inst_t last_inst;
if (kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst) !=
EMULATE_DONE) {
@ -1426,12 +1426,13 @@ static int kvmppc_emulate_debug_inst(struct kvm_vcpu *vcpu)
return RESUME_GUEST;
}
if (last_inst == KVMPPC_INST_SW_BREAKPOINT) {
if (ppc_inst_val(last_inst) == KVMPPC_INST_SW_BREAKPOINT) {
vcpu->run->exit_reason = KVM_EXIT_DEBUG;
vcpu->run->debug.arch.address = kvmppc_get_pc(vcpu);
return RESUME_HOST;
} else {
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
kvmppc_core_queue_program(vcpu, SRR1_PROGILL |
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
return RESUME_GUEST;
}
}
@ -1479,9 +1480,11 @@ static int kvmppc_emulate_doorbell_instr(struct kvm_vcpu *vcpu)
unsigned long arg;
struct kvm *kvm = vcpu->kvm;
struct kvm_vcpu *tvcpu;
ppc_inst_t pinst;
if (kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst) != EMULATE_DONE)
if (kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst) != EMULATE_DONE)
return RESUME_GUEST;
inst = ppc_inst_val(pinst);
if (get_op(inst) != 31)
return EMULATE_FAIL;
rb = get_rb(inst);
@ -1633,7 +1636,8 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
* so that it knows that the machine check occurred.
*/
if (!vcpu->kvm->arch.fwnmi_enabled) {
ulong flags = vcpu->arch.shregs.msr & 0x083c0000;
ulong flags = (vcpu->arch.shregs.msr & 0x083c0000) |
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
kvmppc_core_queue_machine_check(vcpu, flags);
r = RESUME_GUEST;
break;
@ -1662,7 +1666,8 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
* as a result of a hypervisor emulation interrupt
* (e40) getting turned into a 700 by BML RTAS.
*/
flags = vcpu->arch.shregs.msr & 0x1f0000ull;
flags = (vcpu->arch.shregs.msr & 0x1f0000ull) |
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
kvmppc_core_queue_program(vcpu, flags);
r = RESUME_GUEST;
break;
@ -1743,6 +1748,7 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
if (!(vcpu->arch.fault_dsisr & (DSISR_NOHPTE | DSISR_PROTFAULT))) {
kvmppc_core_queue_data_storage(vcpu,
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
vcpu->arch.fault_dar, vcpu->arch.fault_dsisr);
r = RESUME_GUEST;
break;
@ -1761,6 +1767,7 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
r = RESUME_PAGE_FAULT;
} else {
kvmppc_core_queue_data_storage(vcpu,
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
vcpu->arch.fault_dar, err);
r = RESUME_GUEST;
}
@ -1788,7 +1795,8 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
if (!(vcpu->arch.fault_dsisr & SRR1_ISI_NOPT)) {
kvmppc_core_queue_inst_storage(vcpu,
vcpu->arch.fault_dsisr);
vcpu->arch.fault_dsisr |
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
r = RESUME_GUEST;
break;
}
@ -1805,7 +1813,8 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
} else if (err == -1) {
r = RESUME_PAGE_FAULT;
} else {
kvmppc_core_queue_inst_storage(vcpu, err);
kvmppc_core_queue_inst_storage(vcpu,
err | (kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
r = RESUME_GUEST;
}
break;
@ -1826,7 +1835,8 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) {
r = kvmppc_emulate_debug_inst(vcpu);
} else {
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
kvmppc_core_queue_program(vcpu, SRR1_PROGILL |
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
r = RESUME_GUEST;
}
break;
@ -1867,7 +1877,8 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
r = kvmppc_tm_unavailable(vcpu);
}
if (r == EMULATE_FAIL) {
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
kvmppc_core_queue_program(vcpu, SRR1_PROGILL |
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
r = RESUME_GUEST;
}
break;
@ -1997,14 +2008,15 @@ static int kvmppc_handle_nested_exit(struct kvm_vcpu *vcpu)
*/
if (!(vcpu->arch.hfscr_permitted & (1UL << cause)) ||
(vcpu->arch.nested_hfscr & (1UL << cause))) {
ppc_inst_t pinst;
vcpu->arch.trap = BOOK3S_INTERRUPT_H_EMUL_ASSIST;
/*
* If the fetch failed, return to guest and
* try executing it again.
*/
r = kvmppc_get_last_inst(vcpu, INST_GENERIC,
&vcpu->arch.emul_inst);
r = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
vcpu->arch.emul_inst = ppc_inst_val(pinst);
if (r != EMULATE_DONE)
r = RESUME_GUEST;
else
@ -2921,13 +2933,18 @@ static int kvmppc_core_vcpu_create_hv(struct kvm_vcpu *vcpu)
/*
* Set the default HFSCR for the guest from the host value.
* This value is only used on POWER9.
* On POWER9, we want to virtualize the doorbell facility, so we
* This value is only used on POWER9 and later.
* On >= POWER9, we want to virtualize the doorbell facility, so we
* don't set the HFSCR_MSGP bit, and that causes those instructions
* to trap and then we emulate them.
*/
vcpu->arch.hfscr = HFSCR_TAR | HFSCR_EBB | HFSCR_PM | HFSCR_BHRB |
HFSCR_DSCR | HFSCR_VECVSX | HFSCR_FP;
/* On POWER10 and later, allow prefixed instructions */
if (cpu_has_feature(CPU_FTR_ARCH_31))
vcpu->arch.hfscr |= HFSCR_PREFIX;
if (cpu_has_feature(CPU_FTR_HVMODE)) {
vcpu->arch.hfscr &= mfspr(SPRN_HFSCR);
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

9
arch/powerpc/kvm/book3s_hv_nested.c
View File

@ -1560,7 +1560,9 @@ static long int __kvmhv_nested_page_fault(struct kvm_vcpu *vcpu,
if (!memslot || (memslot->flags & KVM_MEMSLOT_INVALID)) {
if (dsisr & (DSISR_PRTABLE_FAULT | DSISR_BADACCESS)) {
/* unusual error -> reflect to the guest as a DSI */
kvmppc_core_queue_data_storage(vcpu, ea, dsisr);
kvmppc_core_queue_data_storage(vcpu,
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
ea, dsisr);
return RESUME_GUEST;
}
@ -1570,8 +1572,9 @@ static long int __kvmhv_nested_page_fault(struct kvm_vcpu *vcpu,
if (memslot->flags & KVM_MEM_READONLY) {
if (writing) {
/* Give the guest a DSI */
kvmppc_core_queue_data_storage(vcpu, ea,
DSISR_ISSTORE | DSISR_PROTFAULT);
kvmppc_core_queue_data_storage(vcpu,
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
ea, DSISR_ISSTORE | DSISR_PROTFAULT);
return RESUME_GUEST;
}
kvm_ro = true;

26
arch/powerpc/kvm/book3s_hv_rmhandlers.S
View File

@ -381,7 +381,7 @@ kvm_secondary_got_guest:
bne kvm_no_guest
li r3,0 /* NULL argument */
bl hmi_exception_realmode
bl CFUNC(hmi_exception_realmode)
/*
* At this point we have finished executing in the guest.
* We need to wait for hwthread_req to become zero, since
@ -458,7 +458,7 @@ kvm_unsplit_nap:
cmpwi r12, BOOK3S_INTERRUPT_HMI
bne 55f
li r3, 0 /* NULL argument */
bl hmi_exception_realmode
bl CFUNC(hmi_exception_realmode)
55:
/*
* Ensure that secondary doesn't nap when it has
@ -502,8 +502,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
* *
*****************************************************************************/
.global kvmppc_hv_entry
kvmppc_hv_entry:
SYM_CODE_START_LOCAL(kvmppc_hv_entry)
/* Required state:
*
@ -859,7 +858,7 @@ deliver_guest_interrupt: /* r4 = vcpu, r13 = paca */
cmpdi r0, 0
beq 71f
mr r3, r4
bl kvmppc_guest_entry_inject_int
bl CFUNC(kvmppc_guest_entry_inject_int)
ld r4, HSTATE_KVM_VCPU(r13)
71:
ld r6, VCPU_SRR0(r4)
@ -940,6 +939,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
ld r4, VCPU_GPR(R4)(r4)
HRFI_TO_GUEST
b .
SYM_CODE_END(kvmppc_hv_entry)
secondary_too_late:
li r12, 0
@ -1071,11 +1071,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
/* Save HEIR (HV emulation assist reg) in emul_inst
if this is an HEI (HV emulation interrupt, e40) */
li r3,KVM_INST_FETCH_FAILED
stw r3,VCPU_LAST_INST(r9)
std r3,VCPU_LAST_INST(r9)
cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
bne 11f
mfspr r3,SPRN_HEIR
11: stw r3,VCPU_HEIR(r9)
11: std r3,VCPU_HEIR(r9)
/* these are volatile across C function calls */
mfctr r3
@ -1544,7 +1544,7 @@ kvmppc_guest_external:
/* External interrupt, first check for host_ipi. If this is
* set, we know the host wants us out so let's do it now
*/
bl kvmppc_read_intr
bl CFUNC(kvmppc_read_intr)
/*
* Restore the active volatile registers after returning from
@ -1626,7 +1626,7 @@ kvmppc_hdsi:
/* Search the hash table. */
mr r3, r9 /* vcpu pointer */
li r7, 1 /* data fault */
bl kvmppc_hpte_hv_fault
bl CFUNC(kvmppc_hpte_hv_fault)
ld r9, HSTATE_KVM_VCPU(r13)
ld r10, VCPU_PC(r9)
ld r11, VCPU_MSR(r9)
@ -1676,7 +1676,7 @@ fast_interrupt_c_return:
mtmsrd r3
/* Store the result */
stw r8, VCPU_LAST_INST(r9)
std r8, VCPU_LAST_INST(r9)
/* Unset guest mode. */
li r0, KVM_GUEST_MODE_HOST_HV
@ -1702,7 +1702,7 @@ kvmppc_hisi:
mr r4, r10
mr r6, r11
li r7, 0 /* instruction fault */
bl kvmppc_hpte_hv_fault
bl CFUNC(kvmppc_hpte_hv_fault)
ld r9, HSTATE_KVM_VCPU(r13)
ld r10, VCPU_PC(r9)
ld r11, VCPU_MSR(r9)
@ -2342,7 +2342,7 @@ hmi_realmode:
lbz r0, HSTATE_PTID(r13)
cmpwi r0, 0
bne guest_exit_cont
bl kvmppc_realmode_hmi_handler
bl CFUNC(kvmppc_realmode_hmi_handler)
ld r9, HSTATE_KVM_VCPU(r13)
li r12, BOOK3S_INTERRUPT_HMI
b guest_exit_cont
@ -2413,7 +2413,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
7: mflr r0
std r0, PPC_LR_STKOFF(r1)
stdu r1, -PPC_MIN_STKFRM(r1)
bl kvmppc_read_intr
bl CFUNC(kvmppc_read_intr)
nop
li r12, BOOK3S_INTERRUPT_EXTERNAL
cmpdi r3, 1

4
arch/powerpc/kvm/book3s_paired_singles.c
View File

@ -621,6 +621,7 @@ static int kvmppc_ps_one_in(struct kvm_vcpu *vcpu, bool rc,
int kvmppc_emulate_paired_single(struct kvm_vcpu *vcpu)
{
u32 inst;
ppc_inst_t pinst;
enum emulation_result emulated = EMULATE_DONE;
int ax_rd, ax_ra, ax_rb, ax_rc;
short full_d;
@ -632,7 +633,8 @@ int kvmppc_emulate_paired_single(struct kvm_vcpu *vcpu)
int i;
#endif
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst);
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
inst = ppc_inst_val(pinst);
if (emulated != EMULATE_DONE)
return emulated;

26
arch/powerpc/kvm/book3s_pr.c
View File

@ -759,7 +759,7 @@ static int kvmppc_handle_pagefault(struct kvm_vcpu *vcpu,
flags = DSISR_NOHPTE;
if (data) {
flags |= vcpu->arch.fault_dsisr & DSISR_ISSTORE;
kvmppc_core_queue_data_storage(vcpu, eaddr, flags);
kvmppc_core_queue_data_storage(vcpu, 0, eaddr, flags);
} else {
kvmppc_core_queue_inst_storage(vcpu, flags);
}
@ -1044,6 +1044,8 @@ void kvmppc_set_fscr(struct kvm_vcpu *vcpu, u64 fscr)
{
if (fscr & FSCR_SCV)
fscr &= ~FSCR_SCV; /* SCV must not be enabled */
/* Prohibit prefixed instructions for now */
fscr &= ~FSCR_PREFIX;
if ((vcpu->arch.fscr & FSCR_TAR) && !(fscr & FSCR_TAR)) {
/* TAR got dropped, drop it in shadow too */
kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
@ -1079,7 +1081,7 @@ static int kvmppc_exit_pr_progint(struct kvm_vcpu *vcpu, unsigned int exit_nr)
{
enum emulation_result er;
ulong flags;
u32 last_inst;
ppc_inst_t last_inst;
int emul, r;
/*
@ -1100,9 +1102,9 @@ static int kvmppc_exit_pr_progint(struct kvm_vcpu *vcpu, unsigned int exit_nr)
if (kvmppc_get_msr(vcpu) & MSR_PR) {
#ifdef EXIT_DEBUG
pr_info("Userspace triggered 0x700 exception at\n 0x%lx (0x%x)\n",
kvmppc_get_pc(vcpu), last_inst);
kvmppc_get_pc(vcpu), ppc_inst_val(last_inst));
#endif
if ((last_inst & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) {
if ((ppc_inst_val(last_inst) & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) {
kvmppc_core_queue_program(vcpu, flags);
return RESUME_GUEST;
}
@ -1119,7 +1121,7 @@ static int kvmppc_exit_pr_progint(struct kvm_vcpu *vcpu, unsigned int exit_nr)
break;
case EMULATE_FAIL:
pr_crit("%s: emulation at %lx failed (%08x)\n",
__func__, kvmppc_get_pc(vcpu), last_inst);
__func__, kvmppc_get_pc(vcpu), ppc_inst_val(last_inst));
kvmppc_core_queue_program(vcpu, flags);
r = RESUME_GUEST;
break;
@ -1236,7 +1238,7 @@ int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsigned int exit_nr)
r = kvmppc_handle_pagefault(vcpu, dar, exit_nr);
srcu_read_unlock(&vcpu->kvm->srcu, idx);
} else {
kvmppc_core_queue_data_storage(vcpu, dar, fault_dsisr);
kvmppc_core_queue_data_storage(vcpu, 0, dar, fault_dsisr);
r = RESUME_GUEST;
}
break;
@ -1281,7 +1283,7 @@ int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsigned int exit_nr)
break;
case BOOK3S_INTERRUPT_SYSCALL:
{
u32 last_sc;
ppc_inst_t last_sc;
int emul;
/* Get last sc for papr */
@ -1296,7 +1298,7 @@ int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsigned int exit_nr)
}
if (vcpu->arch.papr_enabled &&
(last_sc == 0x44000022) &&
(ppc_inst_val(last_sc) == 0x44000022) &&
!(kvmppc_get_msr(vcpu) & MSR_PR)) {
/* SC 1 papr hypercalls */
ulong cmd = kvmppc_get_gpr(vcpu, 3);
@ -1348,7 +1350,7 @@ int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsigned int exit_nr)
{
int ext_msr = 0;
int emul;
u32 last_inst;
ppc_inst_t last_inst;
if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) {
/* Do paired single instruction emulation */
@ -1382,15 +1384,15 @@ int kvmppc_handle_exit_pr(struct kvm_vcpu *vcpu, unsigned int exit_nr)
}
case BOOK3S_INTERRUPT_ALIGNMENT:
{
u32 last_inst;
ppc_inst_t last_inst;
int emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
if (emul == EMULATE_DONE) {
u32 dsisr;
u64 dar;
dsisr = kvmppc_alignment_dsisr(vcpu, last_inst);
dar = kvmppc_alignment_dar(vcpu, last_inst);
dsisr = kvmppc_alignment_dsisr(vcpu, ppc_inst_val(last_inst));
dar = kvmppc_alignment_dar(vcpu, ppc_inst_val(last_inst));
kvmppc_set_dsisr(vcpu, dsisr);
kvmppc_set_dar(vcpu, dar);

1
arch/powerpc/kvm/book3s_rmhandlers.S
View File

@ -123,6 +123,7 @@ INTERRUPT_TRAMPOLINE BOOK3S_INTERRUPT_ALTIVEC
kvmppc_handler_skip_ins:
/* Patch the IP to the next instruction */
/* Note that prefixed instructions are disabled in PR KVM for now */
mfsrr0 r12
addi r12, r12, 4
mtsrr0 r12

30
arch/powerpc/kvm/booke.c
View File

@ -283,9 +283,10 @@ void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
}
void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, ulong srr1_flags,
ulong dear_flags, ulong esr_flags)
{
WARN_ON_ONCE(srr1_flags);
vcpu->arch.queued_dear = dear_flags;
vcpu->arch.queued_esr = esr_flags;
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE);
@ -316,14 +317,16 @@ void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong esr_flags)
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM);
}
void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu)
void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
{
WARN_ON_ONCE(srr1_flags);
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
}
#ifdef CONFIG_ALTIVEC
void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu)
void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
{
WARN_ON_ONCE(srr1_flags);
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL);
}
#endif
@ -623,7 +626,7 @@ static void arm_next_watchdog(struct kvm_vcpu *vcpu)
spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags);
}
void kvmppc_watchdog_func(struct timer_list *t)
static void kvmppc_watchdog_func(struct timer_list *t)
{
struct kvm_vcpu *vcpu = from_timer(vcpu, t, arch.wdt_timer);
u32 tsr, new_tsr;
@ -841,7 +844,7 @@ static int emulation_exit(struct kvm_vcpu *vcpu)
return RESUME_GUEST;
case EMULATE_FAIL:
printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
printk(KERN_CRIT "%s: emulation at %lx failed (%08lx)\n",
__func__, vcpu->arch.regs.nip, vcpu->arch.last_inst);
/* For debugging, encode the failing instruction and
* report it to userspace. */
@ -1000,7 +1003,7 @@ static int kvmppc_resume_inst_load(struct kvm_vcpu *vcpu,
}
}
/**
/*
* kvmppc_handle_exit
*
* Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
@ -1012,6 +1015,7 @@ int kvmppc_handle_exit(struct kvm_vcpu *vcpu, unsigned int exit_nr)
int s;
int idx;
u32 last_inst = KVM_INST_FETCH_FAILED;
ppc_inst_t pinst;
enum emulation_result emulated = EMULATE_DONE;
/* Fix irq state (pairs with kvmppc_fix_ee_before_entry()) */
@ -1031,12 +1035,15 @@ int kvmppc_handle_exit(struct kvm_vcpu *vcpu, unsigned int exit_nr)
case BOOKE_INTERRUPT_DATA_STORAGE:
case BOOKE_INTERRUPT_DTLB_MISS:
case BOOKE_INTERRUPT_HV_PRIV:
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
last_inst = ppc_inst_val(pinst);
break;
case BOOKE_INTERRUPT_PROGRAM:
/* SW breakpoints arrive as illegal instructions on HV */
if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) {
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
last_inst = ppc_inst_val(pinst);
}
break;
default:
break;
@ -1225,7 +1232,7 @@ int kvmppc_handle_exit(struct kvm_vcpu *vcpu, unsigned int exit_nr)
#endif
case BOOKE_INTERRUPT_DATA_STORAGE:
kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear,
kvmppc_core_queue_data_storage(vcpu, 0, vcpu->arch.fault_dear,
vcpu->arch.fault_esr);
kvmppc_account_exit(vcpu, DSI_EXITS);
r = RESUME_GUEST;
@ -1946,7 +1953,8 @@ static int kvmppc_booke_add_watchpoint(struct debug_reg *dbg_reg, uint64_t addr,
dbg_reg->dbcr0 |= DBCR0_IDM;
return 0;
}
void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set)
static void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap,
bool set)
{
/* XXX: Add similar MSR protection for BookE-PR */
#ifdef CONFIG_KVM_BOOKE_HV

3
arch/powerpc/kvm/booke.h
View File

@ -109,4 +109,7 @@ static inline void kvmppc_clear_dbsr(void)
{
mtspr(SPRN_DBSR, mfspr(SPRN_DBSR));
}
int kvmppc_handle_exit(struct kvm_vcpu *vcpu, unsigned int exit_nr);
#endif /* __KVM_BOOKE_H__ */

2
arch/powerpc/kvm/bookehv_interrupts.S
View File

@ -139,7 +139,7 @@ END_BTB_FLUSH_SECTION
* kvmppc_get_last_inst().
*/
li r9, KVM_INST_FETCH_FAILED
stw r9, VCPU_LAST_INST(r4)
PPC_STL r9, VCPU_LAST_INST(r4)
.endif
.if \flags & NEED_ESR

4
arch/powerpc/kvm/e500_mmu_host.c
View File

@ -623,7 +623,7 @@ void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 eaddr, gpa_t gpaddr,
#ifdef CONFIG_KVM_BOOKE_HV
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
enum instruction_fetch_type type, u32 *instr)
enum instruction_fetch_type type, unsigned long *instr)
{
gva_t geaddr;
hpa_t addr;
@ -713,7 +713,7 @@ int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
}
#else
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
enum instruction_fetch_type type, u32 *instr)
enum instruction_fetch_type type, unsigned long *instr)
{
return EMULATE_AGAIN;
}

2
arch/powerpc/kvm/e500mc.c
View File

@ -168,7 +168,7 @@ static void kvmppc_core_vcpu_put_e500mc(struct kvm_vcpu *vcpu)
kvmppc_booke_vcpu_put(vcpu);
}
int kvmppc_e500mc_check_processor_compat(void)
static int kvmppc_e500mc_check_processor_compat(void)
{
int r;

8
arch/powerpc/kvm/emulate.c
View File

@ -194,6 +194,7 @@ static int kvmppc_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
int kvmppc_emulate_instruction(struct kvm_vcpu *vcpu)
{
u32 inst;
ppc_inst_t pinst;
int rs, rt, sprn;
enum emulation_result emulated;
int advance = 1;
@ -201,7 +202,8 @@ int kvmppc_emulate_instruction(struct kvm_vcpu *vcpu)
/* this default type might be overwritten by subcategories */
kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst);
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
inst = ppc_inst_val(pinst);
if (emulated != EMULATE_DONE)
return emulated;
@ -299,6 +301,10 @@ int kvmppc_emulate_instruction(struct kvm_vcpu *vcpu)
trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);
/* Advance past emulated instruction. */
/*
* If this ever handles prefixed instructions, the 4
* will need to become ppc_inst_len(pinst) instead.
*/
if (advance)
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);

14
arch/powerpc/kvm/emulate_loadstore.c
View File

@ -28,7 +28,7 @@
static bool kvmppc_check_fp_disabled(struct kvm_vcpu *vcpu)
{
if (!(kvmppc_get_msr(vcpu) & MSR_FP)) {
kvmppc_core_queue_fpunavail(vcpu);
kvmppc_core_queue_fpunavail(vcpu, kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
return true;
}
@ -40,7 +40,7 @@ static bool kvmppc_check_fp_disabled(struct kvm_vcpu *vcpu)
static bool kvmppc_check_vsx_disabled(struct kvm_vcpu *vcpu)
{
if (!(kvmppc_get_msr(vcpu) & MSR_VSX)) {
kvmppc_core_queue_vsx_unavail(vcpu);
kvmppc_core_queue_vsx_unavail(vcpu, kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
return true;
}
@ -52,7 +52,7 @@ static bool kvmppc_check_vsx_disabled(struct kvm_vcpu *vcpu)
static bool kvmppc_check_altivec_disabled(struct kvm_vcpu *vcpu)
{
if (!(kvmppc_get_msr(vcpu) & MSR_VEC)) {
kvmppc_core_queue_vec_unavail(vcpu);
kvmppc_core_queue_vec_unavail(vcpu, kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
return true;
}
@ -71,7 +71,7 @@ static bool kvmppc_check_altivec_disabled(struct kvm_vcpu *vcpu)
*/
int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)
{
u32 inst;
ppc_inst_t inst;
enum emulation_result emulated = EMULATE_FAIL;
struct instruction_op op;
@ -93,7 +93,7 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)
emulated = EMULATE_FAIL;
vcpu->arch.regs.msr = vcpu->arch.shared->msr;
if (analyse_instr(&op, &vcpu->arch.regs, ppc_inst(inst)) == 0) {
if (analyse_instr(&op, &vcpu->arch.regs, inst) == 0) {
int type = op.type & INSTR_TYPE_MASK;
int size = GETSIZE(op.type);
@ -356,11 +356,11 @@ int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)
}
}
trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);
trace_kvm_ppc_instr(ppc_inst_val(inst), kvmppc_get_pc(vcpu), emulated);
/* Advance past emulated instruction. */
if (emulated != EMULATE_FAIL)
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + ppc_inst_len(inst));
return emulated;
}

8
arch/powerpc/kvm/powerpc.c
View File

@ -304,11 +304,11 @@ int kvmppc_emulate_mmio(struct kvm_vcpu *vcpu)
break;
case EMULATE_FAIL:
{
u32 last_inst;
ppc_inst_t last_inst;
kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
kvm_debug_ratelimited("Guest access to device memory using unsupported instruction (opcode: %#08x)\n",
last_inst);
ppc_inst_val(last_inst));
/*
* Injecting a Data Storage here is a bit more
@ -321,7 +321,9 @@ int kvmppc_emulate_mmio(struct kvm_vcpu *vcpu)
if (vcpu->mmio_is_write)
dsisr |= DSISR_ISSTORE;
kvmppc_core_queue_data_storage(vcpu, vcpu->arch.vaddr_accessed, dsisr);
kvmppc_core_queue_data_storage(vcpu,
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
vcpu->arch.vaddr_accessed, dsisr);
} else {
/*
* BookE does not send a SIGBUS on a bad

10
arch/powerpc/lib/copypage_64.S
View File

@ -18,8 +18,18 @@ FTR_SECTION_ELSE
#endif
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
ori r5,r5,PAGE_SIZE@l
#ifdef CONFIG_PPC_KERNEL_PCREL
/*
* Hack for toolchain - prefixed instructions cause label difference to
* be non-constant even if 8 byte alignment is known, so they can not
* be put in FTR sections.
*/
LOAD_REG_ADDR(r10, ppc64_caches)
BEGIN_FTR_SECTION
#else
BEGIN_FTR_SECTION
LOAD_REG_ADDR(r10, ppc64_caches)
#endif
lwz r11,DCACHEL1LOGBLOCKSIZE(r10) /* log2 of cache block size */
lwz r12,DCACHEL1BLOCKSIZE(r10) /* get cache block size */
li r9,0

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