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net: ipa: a few last IPA register cleanups

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Some last cleanups for the existing IPA register definitions:
  - Remove the definition of IPA_REG_ENABLED_PIPES_OFFSET, because
    it is not used.
  - Use "IPA_" instead of "BAM_" as the prefix on fields associated
    with the FLAVOR_0 register.  We use GSI (not BAM), but the
    fields apply to both GSI and BAM.
  - Get rid of the definition of IPA_CS_RSVD; it is never used.
  - Add two missing field mask definitions for the INIT_DEAGGR
    endpoint register.
  - Eliminate a few of the defined sequencer types, because they
    are unused.  We can add them back when needed.
  - Add a field mask to indicate which bit causes an interrupt on
    the microcontroller.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Alex Elder 2020-11-16 17:38:05 -06:00 committed by Jakub Kicinski
parent 322053105f
commit 716a115b4f
3 changed files with 16 additions and 18 deletions
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6
drivers/net/ipa/ipa_endpoint.c
View File

@ -1545,8 +1545,8 @@ int ipa_endpoint_config(struct ipa *ipa)
val = ioread32(ipa->reg_virt + IPA_REG_FLAVOR_0_OFFSET);
/* Our RX is an IPA producer */
rx_base = u32_get_bits(val, BAM_PROD_LOWEST_FMASK);
max = rx_base + u32_get_bits(val, BAM_MAX_PROD_PIPES_FMASK);
rx_base = u32_get_bits(val, IPA_PROD_LOWEST_FMASK);
max = rx_base + u32_get_bits(val, IPA_MAX_PROD_PIPES_FMASK);
if (max > IPA_ENDPOINT_MAX) {
dev_err(dev, "too many endpoints (%u > %u)\n",
max, IPA_ENDPOINT_MAX);
@ -1555,7 +1555,7 @@ int ipa_endpoint_config(struct ipa *ipa)
rx_mask = GENMASK(max - 1, rx_base);
/* Our TX is an IPA consumer */
max = u32_get_bits(val, BAM_MAX_CONS_PIPES_FMASK);
max = u32_get_bits(val, IPA_MAX_CONS_PIPES_FMASK);
tx_mask = GENMASK(max - 1, 0);
ipa->available = rx_mask | tx_mask;

21
drivers/net/ipa/ipa_reg.h
View File

@ -65,8 +65,6 @@ struct ipa;
* of valid bits for the register.
*/
#define IPA_REG_ENABLED_PIPES_OFFSET 0x00000038
/* The next field is not supported for IPA v4.1 */
#define IPA_REG_COMP_CFG_OFFSET 0x0000003c
#define ENABLE_FMASK GENMASK(0, 0)
@ -248,10 +246,10 @@ static inline u32 ipa_aggr_granularity_val(u32 usec)
#define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19)
#define IPA_REG_FLAVOR_0_OFFSET 0x00000210
#define BAM_MAX_PIPES_FMASK GENMASK(4, 0)
#define BAM_MAX_CONS_PIPES_FMASK GENMASK(12, 8)
#define BAM_MAX_PROD_PIPES_FMASK GENMASK(20, 16)
#define BAM_PROD_LOWEST_FMASK GENMASK(27, 24)
#define IPA_MAX_PIPES_FMASK GENMASK(3, 0)
#define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8)
#define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16)
#define IPA_PROD_LOWEST_FMASK GENMASK(27, 24)
static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version)
{
@ -338,7 +336,6 @@ enum ipa_cs_offload_en {
IPA_CS_OFFLOAD_NONE = 0x0,
IPA_CS_OFFLOAD_UL = 0x1,
IPA_CS_OFFLOAD_DL = 0x2,
IPA_CS_RSVD = 0x3,
};
#define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \
@ -429,8 +426,10 @@ enum ipa_aggr_type {
#define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \
(0x00000834 + 0x0070 * (txep))
#define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0)
#define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6)
#define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7)
#define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8)
#define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14)
#define MAX_PACKET_LEN_FMASK GENMASK(31, 16)
#define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \
@ -457,12 +456,8 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp)
/**
* enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N
* @IPA_SEQ_DMA_ONLY: only DMA is performed
* @IPA_SEQ_PKT_PROCESS_NO_DEC_UCP:
* packet processing + no decipher + microcontroller (Ethernet Bridging)
* @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP:
* second packet processing pass + no decipher + microcontroller
* @IPA_SEQ_DMA_DEC: DMA + cipher/decipher
* @IPA_SEQ_DMA_COMP_DECOMP: DMA + compression/decompression
* @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP:
* packet processing + no decipher + no uCP + HPS REP DMA parser
* @IPA_SEQ_INVALID: invalid sequencer type
@ -472,10 +467,7 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp)
*/
enum ipa_seq_type {
IPA_SEQ_DMA_ONLY = 0x0000,
IPA_SEQ_PKT_PROCESS_NO_DEC_UCP = 0x0002,
IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004,
IPA_SEQ_DMA_DEC = 0x0011,
IPA_SEQ_DMA_COMP_DECOMP = 0x0020,
IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806,
IPA_SEQ_INVALID = 0xffff,
};
@ -565,6 +557,7 @@ enum ipa_irq_id {
IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP)
#define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \
(0x0000301c + 0x1000 * (ee))
#define UC_INTR_FMASK GENMASK(0, 0)
/* ipa->available defines the valid bits in the SUSPEND_INFO register */
#define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \

7
drivers/net/ipa/ipa_uc.c
View File

@ -192,14 +192,19 @@ void ipa_uc_teardown(struct ipa *ipa)
static void send_uc_command(struct ipa *ipa, u32 command, u32 command_param)
{
struct ipa_uc_mem_area *shared = ipa_uc_shared(ipa);
u32 val;
/* Fill in the command data */
shared->command = command;
shared->command_param = cpu_to_le32(command_param);
shared->command_param_hi = 0;
shared->response = 0;
shared->response_param = 0;
iowrite32(1, ipa->reg_virt + IPA_REG_IRQ_UC_OFFSET);
/* Use an interrupt to tell the microcontroller the command is ready */
val = u32_encode_bits(1, UC_INTR_FMASK);
iowrite32(val, ipa->reg_virt + IPA_REG_IRQ_UC_OFFSET);
}
/* Tell the microcontroller the AP is shutting down */