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dt-bindings: clock: Add Qualcomm SC8280XP display clock bindings
The Qualcomm SC8280XP platform has two display clock controllers, add a binding for these. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926203800.16771-2-quic_bjorande@quicinc.com
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Bjorn Andersson
Bjorn Andersson
parent
ece3c31981
commit
73d9c10a96
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains for the two MDSS instances on SC8280XP.
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See also:
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include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
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properties:
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compatible:
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enum:
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- qcom,sc8280xp-dispcc0
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- qcom,sc8280xp-dispcc1
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clocks:
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items:
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- description: AHB interface clock,
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- description: SoC CXO clock
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- description: SoC sleep clock
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- description: DisplayPort 0 link clock
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- description: DisplayPort 0 VCO div clock
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- description: DisplayPort 1 link clock
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- description: DisplayPort 1 VCO div clock
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- description: DisplayPort 2 link clock
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- description: DisplayPort 2 VCO div clock
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- description: DisplayPort 3 link clock
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- description: DisplayPort 3 VCO div clock
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- description: DSI 0 PLL byte clock
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- description: DSI 0 PLL DSI clock
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- description: DSI 1 PLL byte clock
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- description: DSI 1 PLL DSI clock
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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power-domains:
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items:
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- description: MMCX power domain
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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clock-controller@af00000 {
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compatible = "qcom,sc8280xp-dispcc0";
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reg = <0x0af00000 0x20000>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&mdss0_dp_phy0 0>,
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<&mdss0_dp_phy0 1>,
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<&mdss0_dp_phy1 0>,
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<&mdss0_dp_phy1 1>,
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<&mdss0_dp_phy2 0>,
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<&mdss0_dp_phy2 1>,
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<&mdss0_dp_phy3 0>,
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<&mdss0_dp_phy3 1>,
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<&mdss0_dsi0_phy 0>,
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<&mdss0_dsi0_phy 1>,
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<&mdss0_dsi1_phy 0>,
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<&mdss0_dsi1_phy 1>;
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power-domains = <&rpmhpd SC8280XP_MMCX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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100
include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
Normal file
100
include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
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@ -0,0 +1,100 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC8280XP_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC8280XP_H
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/* DISPCC clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_PLL1 1
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#define DISP_CC_PLL1_OUT_EVEN 2
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#define DISP_CC_PLL2 3
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#define DISP_CC_MDSS_AHB1_CLK 4
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#define DISP_CC_MDSS_AHB_CLK 5
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#define DISP_CC_MDSS_AHB_CLK_SRC 6
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#define DISP_CC_MDSS_BYTE0_CLK 7
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 8
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 9
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 10
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#define DISP_CC_MDSS_BYTE1_CLK 11
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#define DISP_CC_MDSS_BYTE1_CLK_SRC 12
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#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 13
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#define DISP_CC_MDSS_BYTE1_INTF_CLK 14
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#define DISP_CC_MDSS_DPTX0_AUX_CLK 15
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#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 16
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#define DISP_CC_MDSS_DPTX0_LINK_CLK 17
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#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 18
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#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 19
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#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 20
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 21
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 22
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 23
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 24
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#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 25
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#define DISP_CC_MDSS_DPTX1_AUX_CLK 26
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#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 27
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#define DISP_CC_MDSS_DPTX1_LINK_CLK 28
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#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 29
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#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 30
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#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 31
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 32
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#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 33
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 34
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#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 35
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#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 36
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#define DISP_CC_MDSS_DPTX2_AUX_CLK 37
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#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 38
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#define DISP_CC_MDSS_DPTX2_LINK_CLK 39
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#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40
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#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41
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#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43
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#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45
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#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46
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#define DISP_CC_MDSS_DPTX3_AUX_CLK 47
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#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48
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#define DISP_CC_MDSS_DPTX3_LINK_CLK 49
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#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 50
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#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 51
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#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 52
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 53
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#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 54
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#define DISP_CC_MDSS_ESC0_CLK 55
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#define DISP_CC_MDSS_ESC0_CLK_SRC 56
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#define DISP_CC_MDSS_ESC1_CLK 57
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#define DISP_CC_MDSS_ESC1_CLK_SRC 58
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#define DISP_CC_MDSS_MDP1_CLK 59
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#define DISP_CC_MDSS_MDP_CLK 60
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#define DISP_CC_MDSS_MDP_CLK_SRC 61
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#define DISP_CC_MDSS_MDP_LUT1_CLK 62
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#define DISP_CC_MDSS_MDP_LUT_CLK 63
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 64
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#define DISP_CC_MDSS_PCLK0_CLK 65
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 66
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#define DISP_CC_MDSS_PCLK1_CLK 67
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#define DISP_CC_MDSS_PCLK1_CLK_SRC 68
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#define DISP_CC_MDSS_ROT1_CLK 69
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#define DISP_CC_MDSS_ROT_CLK 70
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#define DISP_CC_MDSS_ROT_CLK_SRC 71
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#define DISP_CC_MDSS_RSCC_AHB_CLK 72
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 73
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#define DISP_CC_MDSS_VSYNC1_CLK 74
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#define DISP_CC_MDSS_VSYNC_CLK 75
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 76
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#define DISP_CC_SLEEP_CLK 77
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#define DISP_CC_SLEEP_CLK_SRC 78
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#define DISP_CC_XO_CLK 79
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#define DISP_CC_XO_CLK_SRC 80
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/* DISPCC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_RSCC_BCR 1
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/* DISPCC GDSCs */
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#define MDSS_GDSC 0
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#define MDSS_INT2_GDSC 1
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#endif
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