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cxl fixes for v6.10-rc7
- Fix no cxl_nvd during pmem region auto-assemble - Avoid NULLL pointer dereference in region lookup - Add missing checks to interleave capability - Add cxl kdoc fix to address document compilation error -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE5DAy15EJMCV1R6v9YGjFFmlTOEoFAmaC5f0ACgkQYGjFFmlT OEpjug/8DxnDA/hxi45kQHz0iwtMNFPv87qpC5MQ5XEXG0RLY4xka5UI7SKDPuo8 JZGWCi/wObUU0iAtG9tBji3aMkx9BM0PYj3LIMkQaZccUtS47xgzQius4c4KpPCC gGDGEXc1oMVIIBzh7/ZXU6PTd4a3+8c6DZoSIUEyyt1j72R8ef9lans/w4Dl39FI c+SVE4GdlnVe5/34CUTe+It8vn8bV/a9YXwjadIuXnOFxsPym2CdeADssj8IZUOS pmDU5CdGPJAnL9jT+/NtuY312wrGi7ImxhLtD9/3pJhluqs/OMW4OWcIgDoDAP13 Ndn/eLoO2zgZtVAoCeMMuEQcRBZGwCcrIbN1CBVJ2HR+n6XlO7ICmABcOoZvhG0b wdK6ukNnWLoP0xXRpqYWcTsGfjWTadKqom1hs6jJqMeJcK8HcQNzb8xNzoXdk0QR wT8AKYRupwQuAY90mSp4aAlo8aJypAXB6tJzzp05QcgbTd+uif0STiiOzkG9FCAE 1v1snUjjkrIjUwODzX4Me2xw0AxSZdOvk//5mKB3fSQdXYxQUNfRunAI02qIM+8M XPM/QxA+DeJEyD8BTnDo5J5SK5XhoMHaCPrOPYMm5bPYKS0TxHHCY4tMRAQTfhW+ QVcbkqi+WSAvVibl0OcwYmR64TnGMtCwhQrPFqaX+aWBpvhc+1c= =6MV8 -----END PGP SIGNATURE----- Merge tag 'cxl-fixes-6.10-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl Pull cxl fixes from Dave Jiang: - Fix no cxl_nvd during pmem region auto-assemble - Avoid NULLL pointer dereference in region lookup - Add missing checks to interleave capability - Add cxl kdoc fix to address document compilation error * tag 'cxl-fixes-6.10-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: cxl: documentation: add missing files to cxl driver-api cxl/region: check interleave capability cxl/region: Avoid null pointer dereference in region lookup cxl/mem: Fix no cxl_nvd during pmem region auto-assembling
This commit is contained in:
Linus Torvalds
commit
73e931504f
@ -328,6 +328,12 @@ CXL Memory Device
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.. kernel-doc:: drivers/cxl/mem.c
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:doc: cxl mem
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.. kernel-doc:: drivers/cxl/cxlmem.h
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:internal:
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.. kernel-doc:: drivers/cxl/core/memdev.c
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:identifiers:
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CXL Port
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--------
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.. kernel-doc:: drivers/cxl/port.c
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@ -341,6 +347,15 @@ CXL Core
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.. kernel-doc:: drivers/cxl/cxl.h
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:internal:
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.. kernel-doc:: drivers/cxl/core/hdm.c
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:doc: cxl core hdm
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.. kernel-doc:: drivers/cxl/core/hdm.c
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:identifiers:
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.. kernel-doc:: drivers/cxl/core/cdat.c
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:identifiers:
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.. kernel-doc:: drivers/cxl/core/port.c
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:doc: cxl core
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@ -52,6 +52,14 @@ int devm_cxl_add_passthrough_decoder(struct cxl_port *port)
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struct cxl_dport *dport = NULL;
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int single_port_map[1];
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unsigned long index;
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struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
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/*
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* Capability checks are moot for passthrough decoders, support
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* any and all possibilities.
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*/
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cxlhdm->interleave_mask = ~0U;
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cxlhdm->iw_cap_mask = ~0UL;
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cxlsd = cxl_switch_decoder_alloc(port, 1);
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if (IS_ERR(cxlsd))
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@ -79,6 +87,11 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm)
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cxlhdm->interleave_mask |= GENMASK(11, 8);
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if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_14_12, hdm_cap))
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cxlhdm->interleave_mask |= GENMASK(14, 12);
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cxlhdm->iw_cap_mask = BIT(1) | BIT(2) | BIT(4) | BIT(8);
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if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY, hdm_cap))
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cxlhdm->iw_cap_mask |= BIT(3) | BIT(6) | BIT(12);
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if (FIELD_GET(CXL_HDM_DECODER_INTERLEAVE_16_WAY, hdm_cap))
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cxlhdm->iw_cap_mask |= BIT(16);
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}
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static bool should_emulate_decoders(struct cxl_endpoint_dvsec_info *info)
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@ -62,10 +62,14 @@ static int match_nvdimm_bridge(struct device *dev, void *data)
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return is_cxl_nvdimm_bridge(dev);
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}
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struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd)
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/**
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* cxl_find_nvdimm_bridge() - find a bridge device relative to a port
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* @port: any descendant port of an nvdimm-bridge associated
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* root-cxl-port
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*/
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struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port)
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{
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struct cxl_root *cxl_root __free(put_cxl_root) =
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find_cxl_root(cxlmd->endpoint);
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struct cxl_root *cxl_root __free(put_cxl_root) = find_cxl_root(port);
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struct device *dev;
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if (!cxl_root)
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@ -242,18 +246,20 @@ static void cxlmd_release_nvdimm(void *_cxlmd)
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/**
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* devm_cxl_add_nvdimm() - add a bridge between a cxl_memdev and an nvdimm
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* @parent_port: parent port for the (to be added) @cxlmd endpoint port
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* @cxlmd: cxl_memdev instance that will perform LIBNVDIMM operations
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*
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* Return: 0 on success negative error code on failure.
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*/
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int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd)
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int devm_cxl_add_nvdimm(struct cxl_port *parent_port,
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struct cxl_memdev *cxlmd)
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{
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struct cxl_nvdimm_bridge *cxl_nvb;
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struct cxl_nvdimm *cxl_nvd;
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struct device *dev;
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int rc;
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cxl_nvb = cxl_find_nvdimm_bridge(cxlmd);
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cxl_nvb = cxl_find_nvdimm_bridge(parent_port);
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if (!cxl_nvb)
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return -ENODEV;
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@ -1101,6 +1101,26 @@ static int cxl_port_attach_region(struct cxl_port *port,
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}
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cxld = cxl_rr->decoder;
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/*
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* the number of targets should not exceed the target_count
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* of the decoder
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*/
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if (is_switch_decoder(&cxld->dev)) {
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struct cxl_switch_decoder *cxlsd;
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cxlsd = to_cxl_switch_decoder(&cxld->dev);
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if (cxl_rr->nr_targets > cxlsd->nr_targets) {
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dev_dbg(&cxlr->dev,
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"%s:%s %s add: %s:%s @ %d overflows targets: %d\n",
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dev_name(port->uport_dev), dev_name(&port->dev),
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dev_name(&cxld->dev), dev_name(&cxlmd->dev),
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dev_name(&cxled->cxld.dev), pos,
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cxlsd->nr_targets);
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rc = -ENXIO;
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goto out_erase;
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}
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}
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rc = cxl_rr_ep_add(cxl_rr, cxled);
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if (rc) {
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dev_dbg(&cxlr->dev,
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@ -1210,6 +1230,50 @@ static int check_last_peer(struct cxl_endpoint_decoder *cxled,
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return 0;
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}
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static int check_interleave_cap(struct cxl_decoder *cxld, int iw, int ig)
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{
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struct cxl_port *port = to_cxl_port(cxld->dev.parent);
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struct cxl_hdm *cxlhdm = dev_get_drvdata(&port->dev);
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unsigned int interleave_mask;
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u8 eiw;
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u16 eig;
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int high_pos, low_pos;
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if (!test_bit(iw, &cxlhdm->iw_cap_mask))
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return -ENXIO;
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/*
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* Per CXL specification r3.1(8.2.4.20.13 Decoder Protection),
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* if eiw < 8:
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* DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + 8 + eiw]
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* DPAOFFSET[eig + 7: 0] = HPAOFFSET[eig + 7: 0]
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*
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* when the eiw is 0, all the bits of HPAOFFSET[51: 0] are used, the
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* interleave bits are none.
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*
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* if eiw >= 8:
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* DPAOFFSET[51: eig + 8] = HPAOFFSET[51: eig + eiw] / 3
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* DPAOFFSET[eig + 7: 0] = HPAOFFSET[eig + 7: 0]
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*
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* when the eiw is 8, all the bits of HPAOFFSET[51: 0] are used, the
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* interleave bits are none.
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*/
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ways_to_eiw(iw, &eiw);
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if (eiw == 0 || eiw == 8)
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return 0;
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granularity_to_eig(ig, &eig);
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if (eiw > 8)
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high_pos = eiw + eig - 1;
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else
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high_pos = eiw + eig + 7;
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low_pos = eig + 8;
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interleave_mask = GENMASK(high_pos, low_pos);
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if (interleave_mask & ~cxlhdm->interleave_mask)
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return -ENXIO;
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return 0;
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}
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static int cxl_port_setup_targets(struct cxl_port *port,
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struct cxl_region *cxlr,
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struct cxl_endpoint_decoder *cxled)
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@ -1360,6 +1424,15 @@ static int cxl_port_setup_targets(struct cxl_port *port,
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return -ENXIO;
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}
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} else {
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rc = check_interleave_cap(cxld, iw, ig);
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if (rc) {
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dev_dbg(&cxlr->dev,
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"%s:%s iw: %d ig: %d is not supported\n",
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dev_name(port->uport_dev),
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dev_name(&port->dev), iw, ig);
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return rc;
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}
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cxld->interleave_ways = iw;
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cxld->interleave_granularity = ig;
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cxld->hpa_range = (struct range) {
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@ -1796,6 +1869,15 @@ static int cxl_region_attach(struct cxl_region *cxlr,
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struct cxl_dport *dport;
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int rc = -ENXIO;
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rc = check_interleave_cap(&cxled->cxld, p->interleave_ways,
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p->interleave_granularity);
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if (rc) {
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dev_dbg(&cxlr->dev, "%s iw: %d ig: %d is not supported\n",
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dev_name(&cxled->cxld.dev), p->interleave_ways,
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p->interleave_granularity);
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return rc;
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}
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if (cxled->mode != cxlr->mode) {
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dev_dbg(&cxlr->dev, "%s region mode: %d mismatch: %d\n",
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dev_name(&cxled->cxld.dev), cxlr->mode, cxled->mode);
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@ -2688,22 +2770,33 @@ static int __cxl_dpa_to_region(struct device *dev, void *arg)
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{
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struct cxl_dpa_to_region_context *ctx = arg;
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struct cxl_endpoint_decoder *cxled;
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struct cxl_region *cxlr;
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u64 dpa = ctx->dpa;
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if (!is_endpoint_decoder(dev))
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return 0;
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cxled = to_cxl_endpoint_decoder(dev);
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if (!cxled->dpa_res || !resource_size(cxled->dpa_res))
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if (!cxled || !cxled->dpa_res || !resource_size(cxled->dpa_res))
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return 0;
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if (dpa > cxled->dpa_res->end || dpa < cxled->dpa_res->start)
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return 0;
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dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa,
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dev_name(&cxled->cxld.region->dev));
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/*
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* Stop the region search (return 1) when an endpoint mapping is
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* found. The region may not be fully constructed so offering
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* the cxlr in the context structure is not guaranteed.
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*/
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cxlr = cxled->cxld.region;
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if (cxlr)
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dev_dbg(dev, "dpa:0x%llx mapped in region:%s\n", dpa,
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dev_name(&cxlr->dev));
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else
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dev_dbg(dev, "dpa:0x%llx mapped in endpoint:%s\n", dpa,
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dev_name(dev));
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ctx->cxlr = cxled->cxld.region;
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ctx->cxlr = cxlr;
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return 1;
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}
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@ -2847,7 +2940,7 @@ static int cxl_pmem_region_alloc(struct cxl_region *cxlr)
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* bridge for one device is the same for all.
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*/
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if (i == 0) {
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cxl_nvb = cxl_find_nvdimm_bridge(cxlmd);
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cxl_nvb = cxl_find_nvdimm_bridge(cxlmd->endpoint);
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if (!cxl_nvb)
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return -ENODEV;
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cxlr->cxl_nvb = cxl_nvb;
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@ -47,6 +47,8 @@ extern const struct nvdimm_security_ops *cxl_security_ops;
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#define CXL_HDM_DECODER_TARGET_COUNT_MASK GENMASK(7, 4)
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#define CXL_HDM_DECODER_INTERLEAVE_11_8 BIT(8)
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#define CXL_HDM_DECODER_INTERLEAVE_14_12 BIT(9)
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#define CXL_HDM_DECODER_INTERLEAVE_3_6_12_WAY BIT(11)
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#define CXL_HDM_DECODER_INTERLEAVE_16_WAY BIT(12)
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#define CXL_HDM_DECODER_CTRL_OFFSET 0x4
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#define CXL_HDM_DECODER_ENABLE BIT(1)
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#define CXL_HDM_DECODER0_BASE_LOW_OFFSET(i) (0x20 * (i) + 0x10)
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@ -855,8 +857,8 @@ struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(struct device *host,
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struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev);
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bool is_cxl_nvdimm(struct device *dev);
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bool is_cxl_nvdimm_bridge(struct device *dev);
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int devm_cxl_add_nvdimm(struct cxl_memdev *cxlmd);
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struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd);
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int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *cxlmd);
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struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port);
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#ifdef CONFIG_CXL_REGION
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bool is_cxl_pmem_region(struct device *dev);
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@ -395,9 +395,9 @@ enum cxl_devtype {
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/**
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* struct cxl_dpa_perf - DPA performance property entry
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* @dpa_range - range for DPA address
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* @coord - QoS performance data (i.e. latency, bandwidth)
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* @qos_class - QoS Class cookies
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* @dpa_range: range for DPA address
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* @coord: QoS performance data (i.e. latency, bandwidth)
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* @qos_class: QoS Class cookies
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*/
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struct cxl_dpa_perf {
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struct range dpa_range;
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@ -464,13 +464,14 @@ struct cxl_dev_state {
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* @active_persistent_bytes: sum of hard + soft persistent
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* @next_volatile_bytes: volatile capacity change pending device reset
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* @next_persistent_bytes: persistent capacity change pending device reset
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* @ram_perf: performance data entry matched to RAM partition
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* @pmem_perf: performance data entry matched to PMEM partition
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* @event: event log driver state
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* @poison: poison driver state info
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* @security: security driver state info
|
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* @fw: firmware upload / activation state
|
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* @mbox_wait: RCU wait for mbox send completely
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* @mbox_send: @dev specific transport for transmitting mailbox commands
|
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* @ram_perf: performance data entry matched to RAM partition
|
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* @pmem_perf: performance data entry matched to PMEM partition
|
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*
|
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* See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
|
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* details on capacity parameters.
|
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@ -851,11 +852,21 @@ static inline void cxl_mem_active_dec(void)
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|
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int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
|
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|
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/**
|
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* struct cxl_hdm - HDM Decoder registers and cached / decoded capabilities
|
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* @regs: mapped registers, see devm_cxl_setup_hdm()
|
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* @decoder_count: number of decoders for this port
|
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* @target_count: for switch decoders, max downstream port targets
|
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* @interleave_mask: interleave granularity capability, see check_interleave_cap()
|
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* @iw_cap_mask: bitmask of supported interleave ways, see check_interleave_cap()
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* @port: mapped cxl_port, see devm_cxl_setup_hdm()
|
||||
*/
|
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struct cxl_hdm {
|
||||
struct cxl_component_regs regs;
|
||||
unsigned int decoder_count;
|
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unsigned int target_count;
|
||||
unsigned int interleave_mask;
|
||||
unsigned long iw_cap_mask;
|
||||
struct cxl_port *port;
|
||||
};
|
||||
|
||||
|
||||
@ -152,6 +152,15 @@ static int cxl_mem_probe(struct device *dev)
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) {
|
||||
rc = devm_cxl_add_nvdimm(parent_port, cxlmd);
|
||||
if (rc) {
|
||||
if (rc == -ENODEV)
|
||||
dev_info(dev, "PMEM disabled by platform\n");
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
if (dport->rch)
|
||||
endpoint_parent = parent_port->uport_dev;
|
||||
else
|
||||
@ -174,14 +183,6 @@ static int cxl_mem_probe(struct device *dev)
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
if (resource_size(&cxlds->pmem_res) && IS_ENABLED(CONFIG_CXL_PMEM)) {
|
||||
rc = devm_cxl_add_nvdimm(cxlmd);
|
||||
if (rc == -ENODEV)
|
||||
dev_info(dev, "PMEM disabled by platform\n");
|
||||
else
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*
|
||||
* The kernel may be operating out of CXL memory on this device,
|
||||
* there is no spec defined way to determine whether this device
|
||||
|
||||
@ -630,11 +630,15 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port,
|
||||
struct cxl_endpoint_dvsec_info *info)
|
||||
{
|
||||
struct cxl_hdm *cxlhdm = devm_kzalloc(&port->dev, sizeof(*cxlhdm), GFP_KERNEL);
|
||||
struct device *dev = &port->dev;
|
||||
|
||||
if (!cxlhdm)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
cxlhdm->port = port;
|
||||
cxlhdm->interleave_mask = ~0U;
|
||||
cxlhdm->iw_cap_mask = ~0UL;
|
||||
dev_set_drvdata(dev, cxlhdm);
|
||||
return cxlhdm;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user