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dt-bindings: clock: Introduce QCOM sc7180 display clock bindings

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Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SC7180 SoCs.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1573812245-23827-3-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
[sboyd@kernel.org: Add sc7180 to subject]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Taniya Das 2019-11-15 15:34:04 +05:30 committed by Stephen Boyd
parent 5d28e44ba6
commit 75616da712
2 changed files with 47 additions and 0 deletions
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1
Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
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@ -16,6 +16,7 @@ description: |
properties: properties:
compatible: compatible:
enum: enum:
- qcom,sc7180-dispcc
- qcom,sdm845-dispcc - qcom,sdm845-dispcc
clocks: clocks:

46
include/dt-bindings/clock/qcom,dispcc-sc7180.h Normal file
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@ -0,0 +1,46 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
#define DISP_CC_PLL0 0
#define DISP_CC_PLL0_OUT_EVEN 1
#define DISP_CC_MDSS_AHB_CLK 2
#define DISP_CC_MDSS_AHB_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_CLK 4
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
#define DISP_CC_MDSS_DP_AUX_CLK 8
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 9
#define DISP_CC_MDSS_DP_CRYPTO_CLK 10
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11
#define DISP_CC_MDSS_DP_LINK_CLK 12
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 13
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 15
#define DISP_CC_MDSS_DP_PIXEL_CLK 16
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17
#define DISP_CC_MDSS_ESC0_CLK 18
#define DISP_CC_MDSS_ESC0_CLK_SRC 19
#define DISP_CC_MDSS_MDP_CLK 20
#define DISP_CC_MDSS_MDP_CLK_SRC 21
#define DISP_CC_MDSS_MDP_LUT_CLK 22
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23
#define DISP_CC_MDSS_PCLK0_CLK 24
#define DISP_CC_MDSS_PCLK0_CLK_SRC 25
#define DISP_CC_MDSS_ROT_CLK 26
#define DISP_CC_MDSS_ROT_CLK_SRC 27
#define DISP_CC_MDSS_RSCC_AHB_CLK 28
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29
#define DISP_CC_MDSS_VSYNC_CLK 30
#define DISP_CC_MDSS_VSYNC_CLK_SRC 31
#define DISP_CC_XO_CLK 32
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#endif