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tg3: Add MDIO bus address assignments

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The 5717 is a dual port chip that has a shared MDIO bus design.  While
it is impossible for one function to interface with the wrong phy, that
function still needs to know which MDIO bus address to use when
interfacing with its own phy.  This patch adds code to determine which
MDIO bus address to use.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson 2009-09-01 13:21:36 +00:00 committed by David S. Miller
parent a1b950d56d
commit 882e9793fa
2 changed files with 22 additions and 4 deletions
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23
drivers/net/tg3.c
View File

@ -782,7 +782,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
*val = 0x0; *val = 0x0;
frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
MI_COM_PHY_ADDR_MASK); MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK); MI_COM_REG_ADDR_MASK);
@ -833,7 +833,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
udelay(80); udelay(80);
} }
frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
MI_COM_PHY_ADDR_MASK); MI_COM_PHY_ADDR_MASK);
frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
MI_COM_REG_ADDR_MASK); MI_COM_REG_ADDR_MASK);
@ -1021,6 +1021,21 @@ static void tg3_mdio_start(struct tg3 *tp)
tw32_f(MAC_MI_MODE, tp->mi_mode); tw32_f(MAC_MI_MODE, tp->mi_mode);
udelay(80); udelay(80);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
u32 funcnum, is_serdes;
funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
if (funcnum)
tp->phy_addr = 2;
else
tp->phy_addr = 1;
is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
if (is_serdes)
tp->phy_addr += 7;
} else
tp->phy_addr = PHY_ADDR;
if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
tg3_mdio_config_5785(tp); tg3_mdio_config_5785(tp);
@ -9266,7 +9281,7 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
cmd->speed = tp->link_config.active_speed; cmd->speed = tp->link_config.active_speed;
cmd->duplex = tp->link_config.active_duplex; cmd->duplex = tp->link_config.active_duplex;
} }
cmd->phy_address = PHY_ADDR; cmd->phy_address = tp->phy_addr;
cmd->transceiver = XCVR_INTERNAL; cmd->transceiver = XCVR_INTERNAL;
cmd->autoneg = tp->link_config.autoneg; cmd->autoneg = tp->link_config.autoneg;
cmd->maxtxpkt = 0; cmd->maxtxpkt = 0;
@ -10570,7 +10585,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
switch(cmd) { switch(cmd) {
case SIOCGMIIPHY: case SIOCGMIIPHY:
data->phy_id = PHY_ADDR; data->phy_id = tp->phy_addr;
/* fallthru */ /* fallthru */
case SIOCGMIIREG: { case SIOCGMIIREG: {

3
drivers/net/tg3.h
View File

@ -694,6 +694,7 @@
#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
#define SG_DIG_IS_SERDES 0x00000100
#define SG_DIG_COMMA_DETECTOR 0x00000008 #define SG_DIG_COMMA_DETECTOR 0x00000008
#define SG_DIG_MAC_ACK_STATUS 0x00000004 #define SG_DIG_MAC_ACK_STATUS 0x00000004
#define SG_DIG_AUTONEG_COMPLETE 0x00000002 #define SG_DIG_AUTONEG_COMPLETE 0x00000002
@ -2805,6 +2806,8 @@ struct tg3 {
struct mii_bus *mdio_bus; struct mii_bus *mdio_bus;
int mdio_irq[PHY_MAX_ADDR]; int mdio_irq[PHY_MAX_ADDR];
u8 phy_addr;
/* PHY info */ /* PHY info */
u32 phy_id; u32 phy_id;
#define PHY_ID_MASK 0xfffffff0 #define PHY_ID_MASK 0xfffffff0