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net: dsa: microchip: lan9371/2: add 100BaseTX PHY support

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On the LAN9371 and LAN9372, the 4th internal PHY is a 100BaseTX PHY
instead of a 100BaseT1 PHY. The 100BaseTX PHYs have a different base
register offset.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Acked-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Lucas Stach 2024-07-01 10:53:41 +02:00 committed by David S. Miller
parent df18948d33
commit 8d7330b3a9
3 changed files with 6 additions and 0 deletions
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1
drivers/net/dsa/microchip/ksz_common.h
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@ -22,6 +22,7 @@
/* all KSZ switches count ports from 1 */
#define KSZ_PORT_1 0
#define KSZ_PORT_2 1
#define KSZ_PORT_4 3
struct ksz_device;
struct ksz_port;

4
drivers/net/dsa/microchip/lan937x_main.c
View File

@ -55,6 +55,10 @@ static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg)
u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE;
u16 temp;
if ((dev->info->chip_id == LAN9371_CHIP_ID ||
dev->info->chip_id == LAN9372_CHIP_ID) && addr == KSZ_PORT_4)
addr_base = REG_PORT_TX_PHY_CTRL_BASE;
/* get register address based on the logical port */
temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2)));

1
drivers/net/dsa/microchip/lan937x_reg.h
View File

@ -147,6 +147,7 @@
/* 1 - Phy */
#define REG_PORT_T1_PHY_CTRL_BASE 0x0100
#define REG_PORT_TX_PHY_CTRL_BASE 0x0280
/* 3 - xMII */
#define PORT_SGMII_SEL BIT(7)