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ARM: s3c24xx: remove support for ISA drivers on BAST PC/104
BAST is the one machine that theoretically supports unmodified ISA drivers for hardware on its PC/104 connector, using a custom version of the inb()/outb() and inw()/outw() macros. This is incompatible with the generic version used in asm/io.h, and can't easily be used in a multiplatform kernel. Removing the special case for 16-bit I/O port access on BAST gets us closer to multiplatform, at the expense of any PC/104 users with 16-bit cards having to either use an older kernel or modify their ISA drivers to manually ioremap() the area and use readw()/write() in place of inw()/outw(). Either way is probably ok, given that there is a recurring discussion about dropping s3c24xx altogether, and many traditional ISA drivers are already gone. Machines other than BAST already have no support for ISA drivers, though a couple of them do map one of the external chip-selects into the ISA port range, using the same address for 8-bit and 16-bit I/O. It is unlikely that anything actually uses this mapping, but it's also easy to keep this working by mapping it to the normal platform-independent PCI I/O base that is otherwise unused on s3c24xx. The mach/map-base.h file is no longer referenced in global headers and can be moved into the platform directory. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@ -444,7 +444,6 @@ config ARCH_S3C24XX
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select CLKSRC_SAMSUNG_PWM
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select GPIO_SAMSUNG
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select GPIOLIB
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select NEED_MACH_IO_H
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select S3C2410_WATCHDOG
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select SAMSUNG_ATAGS
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select USE_OF
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@ -181,7 +181,6 @@ config MACH_AML_M5900
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config ARCH_BAST
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bool "Simtec Electronics BAST (EB2410ITX)"
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select ISA
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select MACH_BAST_IDE
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select S3C2410_COMMON_DCLK
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select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
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@ -10,7 +10,7 @@
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/map-base.h>
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#include "map-base.h"
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#include "cpu.h"
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unsigned long samsung_cpu_id;
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@ -1,50 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/arm/mach-s3c2410/include/mach/io.h
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* from arch/arm/mach-rpc/include/mach/io.h
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*
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* Copyright (C) 1997 Russell King
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* (C) 2003 Simtec Electronics
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*/
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#ifndef __ASM_ARM_ARCH_IO_S3C24XX_H
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#define __ASM_ARM_ARCH_IO_S3C24XX_H
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#include <mach/map-base.h>
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/*
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* ISA style IO, for each machine to sort out mappings for,
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* if it implements it. We reserve two 16M regions for ISA,
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* so the PC/104 can use separate addresses for 8-bit and
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* 16-bit port I/O.
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*/
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#define PCIO_BASE S3C_ADDR(0x02000000)
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#define IO_SPACE_LIMIT 0x00ffffff
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#define S3C24XX_VA_ISA_WORD (PCIO_BASE)
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#define S3C24XX_VA_ISA_BYTE (PCIO_BASE + 0x01000000)
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#ifdef CONFIG_ISA
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#define inb(p) readb(S3C24XX_VA_ISA_BYTE + (p))
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#define inw(p) readw(S3C24XX_VA_ISA_WORD + (p))
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#define inl(p) readl(S3C24XX_VA_ISA_WORD + (p))
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#define outb(v,p) writeb((v), S3C24XX_VA_ISA_BYTE + (p))
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#define outw(v,p) writew((v), S3C24XX_VA_ISA_WORD + (p))
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#define outl(v,p) writel((v), S3C24XX_VA_ISA_WORD + (p))
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#define insb(p,d,l) readsb(S3C24XX_VA_ISA_BYTE + (p),d,l)
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#define insw(p,d,l) readsw(S3C24XX_VA_ISA_WORD + (p),d,l)
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#define insl(p,d,l) readsl(S3C24XX_VA_ISA_WORD + (p),d,l)
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#define outsb(p,d,l) writesb(S3C24XX_VA_ISA_BYTE + (p),d,l)
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#define outsw(p,d,l) writesw(S3C24XX_VA_ISA_WORD + (p),d,l)
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#define outsl(p,d,l) writesl(S3C24XX_VA_ISA_WORD + (p),d,l)
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#else
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#define __io(x) (PCIO_BASE + (x))
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#endif
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#endif
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@ -1,8 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Krzysztof Kozlowski <krzk@kernel.org>
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*/
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#ifdef CONFIG_ARCH_S3C24XX
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#include "io-s3c24xx.h"
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#endif
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@ -15,7 +15,7 @@
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#include "cpu.h"
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#include "pm.h"
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#include <mach/map-base.h>
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#include "map-base.h"
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#include "map-s3c.h"
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#include "regs-irq.h"
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@ -57,11 +57,6 @@ static struct map_desc anubis_iodesc[] __initdata = {
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.pfn = __phys_to_pfn(0x0),
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.length = SZ_4M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(0x0),
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.length = SZ_4M,
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.type = MT_DEVICE,
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},
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/* we could possibly compress the next set down into a set of smaller tables
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@ -75,11 +75,6 @@ static struct map_desc bast_iodesc[] __initdata = {
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.pfn = PA_CS2(BAST_PA_ISAIO),
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.length = SZ_16M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = PA_CS3(BAST_PA_ISAIO),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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/* bast CPLD control registers, and external interrupt controls */
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{
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@ -58,11 +58,6 @@ static struct map_desc osiris_iodesc[] __initdata = {
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.pfn = __phys_to_pfn(S3C2410_CS5),
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.length = SZ_16M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(S3C2410_CS5),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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/* CPLD control registers */
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@ -48,13 +48,7 @@
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static struct map_desc rx3715_iodesc[] __initdata = {
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/* dump ISA space somewhere unused */
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{
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(S3C2410_CS3),
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.length = SZ_1M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = __phys_to_pfn(S3C2410_CS3),
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.length = SZ_1M,
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@ -53,16 +53,6 @@ static struct map_desc smdk2416_iodesc[] __initdata = {
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/* ISA IO Space map (memory space selected by A24) */
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{
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(S3C2410_CS2),
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.length = 0x10000,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
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.pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
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.length = SZ_4M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = __phys_to_pfn(S3C2410_CS2),
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.length = 0x10000,
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@ -43,16 +43,6 @@ static struct map_desc smdk2440_iodesc[] __initdata = {
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/* ISA IO Space map (memory space selected by A24) */
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{
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(S3C2410_CS2),
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.length = 0x10000,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
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.pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
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.length = SZ_4M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = __phys_to_pfn(S3C2410_CS2),
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.length = 0x10000,
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@ -40,16 +40,6 @@ static struct map_desc smdk2443_iodesc[] __initdata = {
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/* ISA IO Space map (memory space selected by A24) */
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{
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(S3C2410_CS2),
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.length = 0x10000,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD + 0x10000,
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.pfn = __phys_to_pfn(S3C2410_CS2 + (1<<24)),
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.length = SZ_4M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = __phys_to_pfn(S3C2410_CS2),
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.length = 0x10000,
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@ -67,11 +67,6 @@ static struct map_desc vr1000_iodesc[] __initdata = {
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.pfn = PA_CS2(BAST_PA_ISAIO),
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.length = SZ_16M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = PA_CS3(BAST_PA_ISAIO),
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.length = SZ_16M,
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.type = MT_DEVICE,
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},
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/* CPLD control registers, and external interrupt controls */
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@ -33,6 +33,12 @@
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#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
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#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
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/* ISA device mapping for BAST to use with inb()/outb() on 8-bit I/O.
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* 16-bit I/O on BAST now requires driver modifications to manually
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* ioremap CS3.
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*/
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#define S3C24XX_VA_ISA_BYTE PCI_IOBASE
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/* This is used for the CPU specific mappings that may be needed, so that
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* they do not need to directly used S3C_ADDR() and thus make it easier to
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* modify the space for mapping.
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@ -9,7 +9,7 @@
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H
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#include <mach/map-base.h>
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#include "map-base.h"
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#include "map-s3c.h"
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/*
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@ -11,7 +11,7 @@
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H __FILE__
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#include <mach/map-base.h>
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#include "map-base.h"
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#include "map-s3c.h"
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/*
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