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drm: Remove the obsolete driver-mga
Commit 399516ab0fee ("MAINTAINERS: Add a bunch of legacy (UMS) DRM drivers")
marked mga driver obsolete 7 years ago.
And the mesa UMD of this drm driver already in deprecated list
in the link: https://docs.mesa3d.org/systems.html
Matrox-->driver/gpu/drm/mga
It's time to remove this driver.
Signed-off-by: Cai Huoqing <cai.huoqing@linux.dev>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20221203102502.3185-3-cai.huoqing@linux.dev
This commit is contained in:
Cai Huoqing
Thomas Zimmermann
parent
cab18866fe
commit
96ed7db55b
@ -414,15 +414,6 @@ config DRM_R128
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is selected, the module will be called r128. AGP support for
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this card is strongly suggested (unless you have a PCI version).
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config DRM_MGA
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tristate "Matrox g200/g400"
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depends on DRM && PCI
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select FW_LOADER
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help
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Choose this option if you have a Matrox G200, G400 or G450 graphics
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card. If M is selected, the module will be called mga. AGP
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support is required for this driver to work.
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config DRM_SIS
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tristate "SiS video cards"
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depends on DRM && AGP
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@ -137,7 +137,6 @@ obj-$(CONFIG_DRM_TDFX) += tdfx/
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obj-$(CONFIG_DRM_R128) += r128/
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obj-$(CONFIG_DRM_RADEON)+= radeon/
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obj-$(CONFIG_DRM_AMDGPU)+= amd/amdgpu/
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obj-$(CONFIG_DRM_MGA) += mga/
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obj-$(CONFIG_DRM_I915) += i915/
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obj-$(CONFIG_DRM_KMB_DISPLAY) += kmb/
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obj-$(CONFIG_DRM_MGAG200) += mgag200/
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@ -1,11 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Makefile for the drm device driver. This driver provides support for the
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# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
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mga-y := mga_drv.o mga_dma.o mga_state.o mga_warp.o mga_irq.o
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mga-$(CONFIG_COMPAT) += mga_ioc32.o
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obj-$(CONFIG_DRM_MGA) += mga.o
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File diff suppressed because it is too large
Load Diff
@ -1,104 +0,0 @@
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/* mga_drv.c -- Matrox G200/G400 driver -*- linux-c -*-
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* Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com
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*
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Rickard E. (Rik) Faith <faith@valinux.com>
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* Gareth Hughes <gareth@valinux.com>
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*/
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#include <linux/module.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_pciids.h>
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#include "mga_drv.h"
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static struct pci_device_id pciidlist[] = {
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mga_PCI_IDS
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};
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static const struct file_operations mga_driver_fops = {
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.owner = THIS_MODULE,
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.open = drm_open,
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.release = drm_release,
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.unlocked_ioctl = drm_ioctl,
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.mmap = drm_legacy_mmap,
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.poll = drm_poll,
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#ifdef CONFIG_COMPAT
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.compat_ioctl = mga_compat_ioctl,
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#endif
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.llseek = noop_llseek,
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};
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static struct drm_driver driver = {
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.driver_features =
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DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_LEGACY |
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DRIVER_HAVE_DMA | DRIVER_HAVE_IRQ,
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.dev_priv_size = sizeof(drm_mga_buf_priv_t),
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.load = mga_driver_load,
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.unload = mga_driver_unload,
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.lastclose = mga_driver_lastclose,
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.dma_quiescent = mga_driver_dma_quiescent,
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.get_vblank_counter = mga_get_vblank_counter,
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.enable_vblank = mga_enable_vblank,
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.disable_vblank = mga_disable_vblank,
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.irq_preinstall = mga_driver_irq_preinstall,
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.irq_postinstall = mga_driver_irq_postinstall,
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.irq_uninstall = mga_driver_irq_uninstall,
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.irq_handler = mga_driver_irq_handler,
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.ioctls = mga_ioctls,
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.dma_ioctl = mga_dma_buffers,
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.fops = &mga_driver_fops,
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.name = DRIVER_NAME,
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.desc = DRIVER_DESC,
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.date = DRIVER_DATE,
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.major = DRIVER_MAJOR,
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.minor = DRIVER_MINOR,
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.patchlevel = DRIVER_PATCHLEVEL,
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};
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static struct pci_driver mga_pci_driver = {
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.name = DRIVER_NAME,
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.id_table = pciidlist,
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};
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static int __init mga_init(void)
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{
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driver.num_ioctls = mga_max_ioctl;
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return drm_legacy_pci_init(&driver, &mga_pci_driver);
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}
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static void __exit mga_exit(void)
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{
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drm_legacy_pci_exit(&driver, &mga_pci_driver);
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}
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module_init(mga_init);
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module_exit(mga_exit);
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MODULE_AUTHOR(DRIVER_AUTHOR);
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MODULE_DESCRIPTION(DRIVER_DESC);
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MODULE_LICENSE("GPL and additional rights");
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@ -1,685 +0,0 @@
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/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
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* Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
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*
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Gareth Hughes <gareth@valinux.com>
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*/
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#ifndef __MGA_DRV_H__
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#define __MGA_DRV_H__
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#include <linux/irqreturn.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <drm/drm_device.h>
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#include <drm/drm_file.h>
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#include <drm/drm_ioctl.h>
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#include <drm/drm_legacy.h>
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#include <drm/drm_print.h>
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#include <drm/drm_sarea.h>
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#include <drm/drm_vblank.h>
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#include <drm/mga_drm.h>
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/* General customization:
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*/
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#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
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#define DRIVER_NAME "mga"
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#define DRIVER_DESC "Matrox G200/G400"
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#define DRIVER_DATE "20051102"
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#define DRIVER_MAJOR 3
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#define DRIVER_MINOR 2
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#define DRIVER_PATCHLEVEL 1
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typedef struct drm_mga_primary_buffer {
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u8 *start;
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u8 *end;
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int size;
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u32 tail;
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int space;
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volatile long wrapped;
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volatile u32 *status;
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u32 last_flush;
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u32 last_wrap;
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u32 high_mark;
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} drm_mga_primary_buffer_t;
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typedef struct drm_mga_freelist {
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struct drm_mga_freelist *next;
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struct drm_mga_freelist *prev;
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drm_mga_age_t age;
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struct drm_buf *buf;
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} drm_mga_freelist_t;
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typedef struct {
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drm_mga_freelist_t *list_entry;
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int discard;
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int dispatched;
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} drm_mga_buf_priv_t;
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typedef struct drm_mga_private {
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drm_mga_primary_buffer_t prim;
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drm_mga_sarea_t *sarea_priv;
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drm_mga_freelist_t *head;
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drm_mga_freelist_t *tail;
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unsigned int warp_pipe;
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unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
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int chipset;
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int usec_timeout;
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/**
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* If set, the new DMA initialization sequence was used. This is
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* primarilly used to select how the driver should uninitialized its
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* internal DMA structures.
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*/
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int used_new_dma_init;
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/**
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* If AGP memory is used for DMA buffers, this will be the value
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* \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer).
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*/
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u32 dma_access;
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/**
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* If AGP memory is used for DMA buffers, this will be the value
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* \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI
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* transfer).
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*/
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u32 wagp_enable;
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/**
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* \name MMIO region parameters.
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*
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* \sa drm_mga_private_t::mmio
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*/
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/*@{ */
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resource_size_t mmio_base; /**< Bus address of base of MMIO. */
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resource_size_t mmio_size; /**< Size of the MMIO region. */
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/*@} */
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u32 clear_cmd;
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u32 maccess;
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atomic_t vbl_received; /**< Number of vblanks received. */
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wait_queue_head_t fence_queue;
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atomic_t last_fence_retired;
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u32 next_fence_to_post;
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unsigned int fb_cpp;
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unsigned int front_offset;
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unsigned int front_pitch;
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unsigned int back_offset;
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unsigned int back_pitch;
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unsigned int depth_cpp;
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unsigned int depth_offset;
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unsigned int depth_pitch;
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unsigned int texture_offset;
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unsigned int texture_size;
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drm_local_map_t *sarea;
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drm_local_map_t *mmio;
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drm_local_map_t *status;
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drm_local_map_t *warp;
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drm_local_map_t *primary;
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drm_local_map_t *agp_textures;
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unsigned long agp_handle;
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unsigned int agp_size;
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} drm_mga_private_t;
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extern const struct drm_ioctl_desc mga_ioctls[];
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extern int mga_max_ioctl;
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/* mga_dma.c */
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extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int mga_dma_init(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int mga_getparam(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int mga_dma_flush(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int mga_dma_reset(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int mga_dma_buffers(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
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extern void mga_driver_unload(struct drm_device *dev);
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extern void mga_driver_lastclose(struct drm_device *dev);
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extern int mga_driver_dma_quiescent(struct drm_device *dev);
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extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv);
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extern void mga_do_dma_flush(drm_mga_private_t *dev_priv);
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extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv);
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extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv);
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extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf);
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/* mga_warp.c */
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extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv);
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extern int mga_warp_init(drm_mga_private_t *dev_priv);
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/* mga_irq.c */
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extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe);
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extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe);
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extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
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extern void mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
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extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
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extern irqreturn_t mga_driver_irq_handler(int irq, void *arg);
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extern void mga_driver_irq_preinstall(struct drm_device *dev);
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extern int mga_driver_irq_postinstall(struct drm_device *dev);
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extern void mga_driver_irq_uninstall(struct drm_device *dev);
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extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
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unsigned long arg);
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#define mga_flush_write_combine() wmb()
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#define MGA_READ8(reg) \
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readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
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#define MGA_READ(reg) \
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readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
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#define MGA_WRITE8(reg, val) \
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writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
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#define MGA_WRITE(reg, val) \
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writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
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#define DWGREG0 0x1c00
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#define DWGREG0_END 0x1dff
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#define DWGREG1 0x2c00
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#define DWGREG1_END 0x2dff
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#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
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#define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
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#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
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#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
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/* ================================================================
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* Helper macross...
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*/
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#define MGA_EMIT_STATE(dev_priv, dirty) \
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do { \
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if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) { \
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if (dev_priv->chipset >= MGA_CARD_TYPE_G400) \
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mga_g400_emit_state(dev_priv); \
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else \
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mga_g200_emit_state(dev_priv); \
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} \
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} while (0)
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#define WRAP_TEST_WITH_RETURN(dev_priv) \
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do { \
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if (test_bit(0, &dev_priv->prim.wrapped)) { \
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if (mga_is_idle(dev_priv)) { \
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mga_do_dma_wrap_end(dev_priv); \
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} else if (dev_priv->prim.space < \
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dev_priv->prim.high_mark) { \
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if (MGA_DMA_DEBUG) \
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DRM_INFO("wrap...\n"); \
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return -EBUSY; \
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} \
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} \
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} while (0)
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#define WRAP_WAIT_WITH_RETURN(dev_priv) \
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do { \
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if (test_bit(0, &dev_priv->prim.wrapped)) { \
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if (mga_do_wait_for_idle(dev_priv) < 0) { \
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if (MGA_DMA_DEBUG) \
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DRM_INFO("wrap...\n"); \
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return -EBUSY; \
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} \
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mga_do_dma_wrap_end(dev_priv); \
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} \
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} while (0)
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/* ================================================================
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* Primary DMA command stream
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*/
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#define MGA_VERBOSE 0
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#define DMA_LOCALS unsigned int write; volatile u8 *prim;
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#define DMA_BLOCK_SIZE (5 * sizeof(u32))
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#define BEGIN_DMA(n) \
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do { \
|
||||
if (MGA_VERBOSE) { \
|
||||
DRM_INFO("BEGIN_DMA(%d)\n", (n)); \
|
||||
DRM_INFO(" space=0x%x req=0x%zx\n", \
|
||||
dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \
|
||||
} \
|
||||
prim = dev_priv->prim.start; \
|
||||
write = dev_priv->prim.tail; \
|
||||
} while (0)
|
||||
|
||||
#define BEGIN_DMA_WRAP() \
|
||||
do { \
|
||||
if (MGA_VERBOSE) { \
|
||||
DRM_INFO("BEGIN_DMA()\n"); \
|
||||
DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \
|
||||
} \
|
||||
prim = dev_priv->prim.start; \
|
||||
write = dev_priv->prim.tail; \
|
||||
} while (0)
|
||||
|
||||
#define ADVANCE_DMA() \
|
||||
do { \
|
||||
dev_priv->prim.tail = write; \
|
||||
if (MGA_VERBOSE) \
|
||||
DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
|
||||
write, dev_priv->prim.space); \
|
||||
} while (0)
|
||||
|
||||
#define FLUSH_DMA() \
|
||||
do { \
|
||||
if (0) { \
|
||||
DRM_INFO("\n"); \
|
||||
DRM_INFO(" tail=0x%06x head=0x%06lx\n", \
|
||||
dev_priv->prim.tail, \
|
||||
(unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \
|
||||
dev_priv->primary->offset)); \
|
||||
} \
|
||||
if (!test_bit(0, &dev_priv->prim.wrapped)) { \
|
||||
if (dev_priv->prim.space < dev_priv->prim.high_mark) \
|
||||
mga_do_dma_wrap_start(dev_priv); \
|
||||
else \
|
||||
mga_do_dma_flush(dev_priv); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
|
||||
*/
|
||||
#define DMA_WRITE(offset, val) \
|
||||
do { \
|
||||
if (MGA_VERBOSE) \
|
||||
DRM_INFO(" DMA_WRITE( 0x%08x ) at 0x%04zx\n", \
|
||||
(u32)(val), write + (offset) * sizeof(u32)); \
|
||||
*(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
|
||||
} while (0)
|
||||
|
||||
#define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
|
||||
do { \
|
||||
DMA_WRITE(0, ((DMAREG(reg0) << 0) | \
|
||||
(DMAREG(reg1) << 8) | \
|
||||
(DMAREG(reg2) << 16) | \
|
||||
(DMAREG(reg3) << 24))); \
|
||||
DMA_WRITE(1, val0); \
|
||||
DMA_WRITE(2, val1); \
|
||||
DMA_WRITE(3, val2); \
|
||||
DMA_WRITE(4, val3); \
|
||||
write += DMA_BLOCK_SIZE; \
|
||||
} while (0)
|
||||
|
||||
/* Buffer aging via primary DMA stream head pointer.
|
||||
*/
|
||||
|
||||
#define SET_AGE(age, h, w) \
|
||||
do { \
|
||||
(age)->head = h; \
|
||||
(age)->wrap = w; \
|
||||
} while (0)
|
||||
|
||||
#define TEST_AGE(age, h, w) ((age)->wrap < w || \
|
||||
((age)->wrap == w && \
|
||||
(age)->head < h))
|
||||
|
||||
#define AGE_BUFFER(buf_priv) \
|
||||
do { \
|
||||
drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
|
||||
if ((buf_priv)->dispatched) { \
|
||||
entry->age.head = (dev_priv->prim.tail + \
|
||||
dev_priv->primary->offset); \
|
||||
entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
|
||||
} else { \
|
||||
entry->age.head = 0; \
|
||||
entry->age.wrap = 0; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
|
||||
MGA_DWGENGSTS | \
|
||||
MGA_ENDPRDMASTS)
|
||||
#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
|
||||
MGA_ENDPRDMASTS)
|
||||
|
||||
#define MGA_DMA_DEBUG 0
|
||||
|
||||
/* A reduced set of the mga registers.
|
||||
*/
|
||||
#define MGA_CRTC_INDEX 0x1fd4
|
||||
#define MGA_CRTC_DATA 0x1fd5
|
||||
|
||||
/* CRTC11 */
|
||||
#define MGA_VINTCLR (1 << 4)
|
||||
#define MGA_VINTEN (1 << 5)
|
||||
|
||||
#define MGA_ALPHACTRL 0x2c7c
|
||||
#define MGA_AR0 0x1c60
|
||||
#define MGA_AR1 0x1c64
|
||||
#define MGA_AR2 0x1c68
|
||||
#define MGA_AR3 0x1c6c
|
||||
#define MGA_AR4 0x1c70
|
||||
#define MGA_AR5 0x1c74
|
||||
#define MGA_AR6 0x1c78
|
||||
|
||||
#define MGA_CXBNDRY 0x1c80
|
||||
#define MGA_CXLEFT 0x1ca0
|
||||
#define MGA_CXRIGHT 0x1ca4
|
||||
|
||||
#define MGA_DMAPAD 0x1c54
|
||||
#define MGA_DSTORG 0x2cb8
|
||||
#define MGA_DWGCTL 0x1c00
|
||||
# define MGA_OPCOD_MASK (15 << 0)
|
||||
# define MGA_OPCOD_TRAP (4 << 0)
|
||||
# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
|
||||
# define MGA_OPCOD_BITBLT (8 << 0)
|
||||
# define MGA_OPCOD_ILOAD (9 << 0)
|
||||
# define MGA_ATYPE_MASK (7 << 4)
|
||||
# define MGA_ATYPE_RPL (0 << 4)
|
||||
# define MGA_ATYPE_RSTR (1 << 4)
|
||||
# define MGA_ATYPE_ZI (3 << 4)
|
||||
# define MGA_ATYPE_BLK (4 << 4)
|
||||
# define MGA_ATYPE_I (7 << 4)
|
||||
# define MGA_LINEAR (1 << 7)
|
||||
# define MGA_ZMODE_MASK (7 << 8)
|
||||
# define MGA_ZMODE_NOZCMP (0 << 8)
|
||||
# define MGA_ZMODE_ZE (2 << 8)
|
||||
# define MGA_ZMODE_ZNE (3 << 8)
|
||||
# define MGA_ZMODE_ZLT (4 << 8)
|
||||
# define MGA_ZMODE_ZLTE (5 << 8)
|
||||
# define MGA_ZMODE_ZGT (6 << 8)
|
||||
# define MGA_ZMODE_ZGTE (7 << 8)
|
||||
# define MGA_SOLID (1 << 11)
|
||||
# define MGA_ARZERO (1 << 12)
|
||||
# define MGA_SGNZERO (1 << 13)
|
||||
# define MGA_SHIFTZERO (1 << 14)
|
||||
# define MGA_BOP_MASK (15 << 16)
|
||||
# define MGA_BOP_ZERO (0 << 16)
|
||||
# define MGA_BOP_DST (10 << 16)
|
||||
# define MGA_BOP_SRC (12 << 16)
|
||||
# define MGA_BOP_ONE (15 << 16)
|
||||
# define MGA_TRANS_SHIFT 20
|
||||
# define MGA_TRANS_MASK (15 << 20)
|
||||
# define MGA_BLTMOD_MASK (15 << 25)
|
||||
# define MGA_BLTMOD_BMONOLEF (0 << 25)
|
||||
# define MGA_BLTMOD_BMONOWF (4 << 25)
|
||||
# define MGA_BLTMOD_PLAN (1 << 25)
|
||||
# define MGA_BLTMOD_BFCOL (2 << 25)
|
||||
# define MGA_BLTMOD_BU32BGR (3 << 25)
|
||||
# define MGA_BLTMOD_BU32RGB (7 << 25)
|
||||
# define MGA_BLTMOD_BU24BGR (11 << 25)
|
||||
# define MGA_BLTMOD_BU24RGB (15 << 25)
|
||||
# define MGA_PATTERN (1 << 29)
|
||||
# define MGA_TRANSC (1 << 30)
|
||||
# define MGA_CLIPDIS (1 << 31)
|
||||
#define MGA_DWGSYNC 0x2c4c
|
||||
|
||||
#define MGA_FCOL 0x1c24
|
||||
#define MGA_FIFOSTATUS 0x1e10
|
||||
#define MGA_FOGCOL 0x1cf4
|
||||
#define MGA_FXBNDRY 0x1c84
|
||||
#define MGA_FXLEFT 0x1ca8
|
||||
#define MGA_FXRIGHT 0x1cac
|
||||
|
||||
#define MGA_ICLEAR 0x1e18
|
||||
# define MGA_SOFTRAPICLR (1 << 0)
|
||||
# define MGA_VLINEICLR (1 << 5)
|
||||
#define MGA_IEN 0x1e1c
|
||||
# define MGA_SOFTRAPIEN (1 << 0)
|
||||
# define MGA_VLINEIEN (1 << 5)
|
||||
|
||||
#define MGA_LEN 0x1c5c
|
||||
|
||||
#define MGA_MACCESS 0x1c04
|
||||
|
||||
#define MGA_PITCH 0x1c8c
|
||||
#define MGA_PLNWT 0x1c1c
|
||||
#define MGA_PRIMADDRESS 0x1e58
|
||||
# define MGA_DMA_GENERAL (0 << 0)
|
||||
# define MGA_DMA_BLIT (1 << 0)
|
||||
# define MGA_DMA_VECTOR (2 << 0)
|
||||
# define MGA_DMA_VERTEX (3 << 0)
|
||||
#define MGA_PRIMEND 0x1e5c
|
||||
# define MGA_PRIMNOSTART (1 << 0)
|
||||
# define MGA_PAGPXFER (1 << 1)
|
||||
#define MGA_PRIMPTR 0x1e50
|
||||
# define MGA_PRIMPTREN0 (1 << 0)
|
||||
# define MGA_PRIMPTREN1 (1 << 1)
|
||||
|
||||
#define MGA_RST 0x1e40
|
||||
# define MGA_SOFTRESET (1 << 0)
|
||||
# define MGA_SOFTEXTRST (1 << 1)
|
||||
|
||||
#define MGA_SECADDRESS 0x2c40
|
||||
#define MGA_SECEND 0x2c44
|
||||
#define MGA_SETUPADDRESS 0x2cd0
|
||||
#define MGA_SETUPEND 0x2cd4
|
||||
#define MGA_SGN 0x1c58
|
||||
#define MGA_SOFTRAP 0x2c48
|
||||
#define MGA_SRCORG 0x2cb4
|
||||
# define MGA_SRMMAP_MASK (1 << 0)
|
||||
# define MGA_SRCMAP_FB (0 << 0)
|
||||
# define MGA_SRCMAP_SYSMEM (1 << 0)
|
||||
# define MGA_SRCACC_MASK (1 << 1)
|
||||
# define MGA_SRCACC_PCI (0 << 1)
|
||||
# define MGA_SRCACC_AGP (1 << 1)
|
||||
#define MGA_STATUS 0x1e14
|
||||
# define MGA_SOFTRAPEN (1 << 0)
|
||||
# define MGA_VSYNCPEN (1 << 4)
|
||||
# define MGA_VLINEPEN (1 << 5)
|
||||
# define MGA_DWGENGSTS (1 << 16)
|
||||
# define MGA_ENDPRDMASTS (1 << 17)
|
||||
#define MGA_STENCIL 0x2cc8
|
||||
#define MGA_STENCILCTL 0x2ccc
|
||||
|
||||
#define MGA_TDUALSTAGE0 0x2cf8
|
||||
#define MGA_TDUALSTAGE1 0x2cfc
|
||||
#define MGA_TEXBORDERCOL 0x2c5c
|
||||
#define MGA_TEXCTL 0x2c30
|
||||
#define MGA_TEXCTL2 0x2c3c
|
||||
# define MGA_DUALTEX (1 << 7)
|
||||
# define MGA_G400_TC2_MAGIC (1 << 15)
|
||||
# define MGA_MAP1_ENABLE (1 << 31)
|
||||
#define MGA_TEXFILTER 0x2c58
|
||||
#define MGA_TEXHEIGHT 0x2c2c
|
||||
#define MGA_TEXORG 0x2c24
|
||||
# define MGA_TEXORGMAP_MASK (1 << 0)
|
||||
# define MGA_TEXORGMAP_FB (0 << 0)
|
||||
# define MGA_TEXORGMAP_SYSMEM (1 << 0)
|
||||
# define MGA_TEXORGACC_MASK (1 << 1)
|
||||
# define MGA_TEXORGACC_PCI (0 << 1)
|
||||
# define MGA_TEXORGACC_AGP (1 << 1)
|
||||
#define MGA_TEXORG1 0x2ca4
|
||||
#define MGA_TEXORG2 0x2ca8
|
||||
#define MGA_TEXORG3 0x2cac
|
||||
#define MGA_TEXORG4 0x2cb0
|
||||
#define MGA_TEXTRANS 0x2c34
|
||||
#define MGA_TEXTRANSHIGH 0x2c38
|
||||
#define MGA_TEXWIDTH 0x2c28
|
||||
|
||||
#define MGA_WACCEPTSEQ 0x1dd4
|
||||
#define MGA_WCODEADDR 0x1e6c
|
||||
#define MGA_WFLAG 0x1dc4
|
||||
#define MGA_WFLAG1 0x1de0
|
||||
#define MGA_WFLAGNB 0x1e64
|
||||
#define MGA_WFLAGNB1 0x1e08
|
||||
#define MGA_WGETMSB 0x1dc8
|
||||
#define MGA_WIADDR 0x1dc0
|
||||
#define MGA_WIADDR2 0x1dd8
|
||||
# define MGA_WMODE_SUSPEND (0 << 0)
|
||||
# define MGA_WMODE_RESUME (1 << 0)
|
||||
# define MGA_WMODE_JUMP (2 << 0)
|
||||
# define MGA_WMODE_START (3 << 0)
|
||||
# define MGA_WAGP_ENABLE (1 << 2)
|
||||
#define MGA_WMISC 0x1e70
|
||||
# define MGA_WUCODECACHE_ENABLE (1 << 0)
|
||||
# define MGA_WMASTER_ENABLE (1 << 1)
|
||||
# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
|
||||
#define MGA_WVRTXSZ 0x1dcc
|
||||
|
||||
#define MGA_YBOT 0x1c9c
|
||||
#define MGA_YDST 0x1c90
|
||||
#define MGA_YDSTLEN 0x1c88
|
||||
#define MGA_YDSTORG 0x1c94
|
||||
#define MGA_YTOP 0x1c98
|
||||
|
||||
#define MGA_ZORG 0x1c0c
|
||||
|
||||
/* This finishes the current batch of commands
|
||||
*/
|
||||
#define MGA_EXEC 0x0100
|
||||
|
||||
/* AGP PLL encoding (for G200 only).
|
||||
*/
|
||||
#define MGA_AGP_PLL 0x1e4c
|
||||
# define MGA_AGP2XPLL_DISABLE (0 << 0)
|
||||
# define MGA_AGP2XPLL_ENABLE (1 << 0)
|
||||
|
||||
/* Warp registers
|
||||
*/
|
||||
#define MGA_WR0 0x2d00
|
||||
#define MGA_WR1 0x2d04
|
||||
#define MGA_WR2 0x2d08
|
||||
#define MGA_WR3 0x2d0c
|
||||
#define MGA_WR4 0x2d10
|
||||
#define MGA_WR5 0x2d14
|
||||
#define MGA_WR6 0x2d18
|
||||
#define MGA_WR7 0x2d1c
|
||||
#define MGA_WR8 0x2d20
|
||||
#define MGA_WR9 0x2d24
|
||||
#define MGA_WR10 0x2d28
|
||||
#define MGA_WR11 0x2d2c
|
||||
#define MGA_WR12 0x2d30
|
||||
#define MGA_WR13 0x2d34
|
||||
#define MGA_WR14 0x2d38
|
||||
#define MGA_WR15 0x2d3c
|
||||
#define MGA_WR16 0x2d40
|
||||
#define MGA_WR17 0x2d44
|
||||
#define MGA_WR18 0x2d48
|
||||
#define MGA_WR19 0x2d4c
|
||||
#define MGA_WR20 0x2d50
|
||||
#define MGA_WR21 0x2d54
|
||||
#define MGA_WR22 0x2d58
|
||||
#define MGA_WR23 0x2d5c
|
||||
#define MGA_WR24 0x2d60
|
||||
#define MGA_WR25 0x2d64
|
||||
#define MGA_WR26 0x2d68
|
||||
#define MGA_WR27 0x2d6c
|
||||
#define MGA_WR28 0x2d70
|
||||
#define MGA_WR29 0x2d74
|
||||
#define MGA_WR30 0x2d78
|
||||
#define MGA_WR31 0x2d7c
|
||||
#define MGA_WR32 0x2d80
|
||||
#define MGA_WR33 0x2d84
|
||||
#define MGA_WR34 0x2d88
|
||||
#define MGA_WR35 0x2d8c
|
||||
#define MGA_WR36 0x2d90
|
||||
#define MGA_WR37 0x2d94
|
||||
#define MGA_WR38 0x2d98
|
||||
#define MGA_WR39 0x2d9c
|
||||
#define MGA_WR40 0x2da0
|
||||
#define MGA_WR41 0x2da4
|
||||
#define MGA_WR42 0x2da8
|
||||
#define MGA_WR43 0x2dac
|
||||
#define MGA_WR44 0x2db0
|
||||
#define MGA_WR45 0x2db4
|
||||
#define MGA_WR46 0x2db8
|
||||
#define MGA_WR47 0x2dbc
|
||||
#define MGA_WR48 0x2dc0
|
||||
#define MGA_WR49 0x2dc4
|
||||
#define MGA_WR50 0x2dc8
|
||||
#define MGA_WR51 0x2dcc
|
||||
#define MGA_WR52 0x2dd0
|
||||
#define MGA_WR53 0x2dd4
|
||||
#define MGA_WR54 0x2dd8
|
||||
#define MGA_WR55 0x2ddc
|
||||
#define MGA_WR56 0x2de0
|
||||
#define MGA_WR57 0x2de4
|
||||
#define MGA_WR58 0x2de8
|
||||
#define MGA_WR59 0x2dec
|
||||
#define MGA_WR60 0x2df0
|
||||
#define MGA_WR61 0x2df4
|
||||
#define MGA_WR62 0x2df8
|
||||
#define MGA_WR63 0x2dfc
|
||||
# define MGA_G400_WR_MAGIC (1 << 6)
|
||||
# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
|
||||
|
||||
#define MGA_ILOAD_ALIGN 64
|
||||
#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
|
||||
|
||||
#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
|
||||
MGA_ATYPE_I | \
|
||||
MGA_ZMODE_NOZCMP | \
|
||||
MGA_ARZERO | \
|
||||
MGA_SGNZERO | \
|
||||
MGA_BOP_SRC | \
|
||||
(15 << MGA_TRANS_SHIFT))
|
||||
|
||||
#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
|
||||
MGA_ZMODE_NOZCMP | \
|
||||
MGA_SOLID | \
|
||||
MGA_ARZERO | \
|
||||
MGA_SGNZERO | \
|
||||
MGA_SHIFTZERO | \
|
||||
MGA_BOP_SRC | \
|
||||
(0 << MGA_TRANS_SHIFT) | \
|
||||
MGA_BLTMOD_BMONOLEF | \
|
||||
MGA_TRANSC | \
|
||||
MGA_CLIPDIS)
|
||||
|
||||
#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
|
||||
MGA_ATYPE_RPL | \
|
||||
MGA_SGNZERO | \
|
||||
MGA_SHIFTZERO | \
|
||||
MGA_BOP_SRC | \
|
||||
(0 << MGA_TRANS_SHIFT) | \
|
||||
MGA_BLTMOD_BFCOL | \
|
||||
MGA_CLIPDIS)
|
||||
|
||||
/* Simple idle test.
|
||||
*/
|
||||
static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv)
|
||||
{
|
||||
u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
|
||||
return (status == MGA_ENDPRDMASTS);
|
||||
}
|
||||
|
||||
#endif
|
||||
@ -1,197 +0,0 @@
|
||||
/*
|
||||
* \file mga_ioc32.c
|
||||
*
|
||||
* 32-bit ioctl compatibility routines for the MGA DRM.
|
||||
*
|
||||
* \author Dave Airlie <airlied@linux.ie> with code from patches by Egbert Eich
|
||||
*
|
||||
*
|
||||
* Copyright (C) Paul Mackerras 2005
|
||||
* Copyright (C) Egbert Eich 2003,2004
|
||||
* Copyright (C) Dave Airlie 2005
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/compat.h>
|
||||
|
||||
#include "mga_drv.h"
|
||||
|
||||
typedef struct drm32_mga_init {
|
||||
int func;
|
||||
u32 sarea_priv_offset;
|
||||
struct_group(always32bit,
|
||||
int chipset;
|
||||
int sgram;
|
||||
unsigned int maccess;
|
||||
unsigned int fb_cpp;
|
||||
unsigned int front_offset, front_pitch;
|
||||
unsigned int back_offset, back_pitch;
|
||||
unsigned int depth_cpp;
|
||||
unsigned int depth_offset, depth_pitch;
|
||||
unsigned int texture_offset[MGA_NR_TEX_HEAPS];
|
||||
unsigned int texture_size[MGA_NR_TEX_HEAPS];
|
||||
);
|
||||
u32 fb_offset;
|
||||
u32 mmio_offset;
|
||||
u32 status_offset;
|
||||
u32 warp_offset;
|
||||
u32 primary_offset;
|
||||
u32 buffers_offset;
|
||||
} drm_mga_init32_t;
|
||||
|
||||
static int compat_mga_init(struct file *file, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
drm_mga_init32_t init32;
|
||||
drm_mga_init_t init;
|
||||
|
||||
if (copy_from_user(&init32, (void __user *)arg, sizeof(init32)))
|
||||
return -EFAULT;
|
||||
|
||||
init.func = init32.func;
|
||||
init.sarea_priv_offset = init32.sarea_priv_offset;
|
||||
memcpy(&init.always32bit, &init32.always32bit,
|
||||
sizeof(init32.always32bit));
|
||||
init.fb_offset = init32.fb_offset;
|
||||
init.mmio_offset = init32.mmio_offset;
|
||||
init.status_offset = init32.status_offset;
|
||||
init.warp_offset = init32.warp_offset;
|
||||
init.primary_offset = init32.primary_offset;
|
||||
init.buffers_offset = init32.buffers_offset;
|
||||
|
||||
return drm_ioctl_kernel(file, mga_dma_init, &init,
|
||||
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY);
|
||||
}
|
||||
|
||||
typedef struct drm_mga_getparam32 {
|
||||
int param;
|
||||
u32 value;
|
||||
} drm_mga_getparam32_t;
|
||||
|
||||
static int compat_mga_getparam(struct file *file, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
drm_mga_getparam32_t getparam32;
|
||||
drm_mga_getparam_t getparam;
|
||||
|
||||
if (copy_from_user(&getparam32, (void __user *)arg, sizeof(getparam32)))
|
||||
return -EFAULT;
|
||||
|
||||
getparam.param = getparam32.param;
|
||||
getparam.value = compat_ptr(getparam32.value);
|
||||
return drm_ioctl_kernel(file, mga_getparam, &getparam, DRM_AUTH);
|
||||
}
|
||||
|
||||
typedef struct drm_mga_drm_bootstrap32 {
|
||||
u32 texture_handle;
|
||||
u32 texture_size;
|
||||
u32 primary_size;
|
||||
u32 secondary_bin_count;
|
||||
u32 secondary_bin_size;
|
||||
u32 agp_mode;
|
||||
u8 agp_size;
|
||||
} drm_mga_dma_bootstrap32_t;
|
||||
|
||||
static int compat_mga_dma_bootstrap(struct file *file, unsigned int cmd,
|
||||
unsigned long arg)
|
||||
{
|
||||
drm_mga_dma_bootstrap32_t dma_bootstrap32;
|
||||
drm_mga_dma_bootstrap_t dma_bootstrap;
|
||||
int err;
|
||||
|
||||
if (copy_from_user(&dma_bootstrap32, (void __user *)arg,
|
||||
sizeof(dma_bootstrap32)))
|
||||
return -EFAULT;
|
||||
|
||||
dma_bootstrap.texture_handle = dma_bootstrap32.texture_handle;
|
||||
dma_bootstrap.texture_size = dma_bootstrap32.texture_size;
|
||||
dma_bootstrap.primary_size = dma_bootstrap32.primary_size;
|
||||
dma_bootstrap.secondary_bin_count = dma_bootstrap32.secondary_bin_count;
|
||||
dma_bootstrap.secondary_bin_size = dma_bootstrap32.secondary_bin_size;
|
||||
dma_bootstrap.agp_mode = dma_bootstrap32.agp_mode;
|
||||
dma_bootstrap.agp_size = dma_bootstrap32.agp_size;
|
||||
|
||||
err = drm_ioctl_kernel(file, mga_dma_bootstrap, &dma_bootstrap,
|
||||
DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
dma_bootstrap32.texture_handle = dma_bootstrap.texture_handle;
|
||||
dma_bootstrap32.texture_size = dma_bootstrap.texture_size;
|
||||
dma_bootstrap32.primary_size = dma_bootstrap.primary_size;
|
||||
dma_bootstrap32.secondary_bin_count = dma_bootstrap.secondary_bin_count;
|
||||
dma_bootstrap32.secondary_bin_size = dma_bootstrap.secondary_bin_size;
|
||||
dma_bootstrap32.agp_mode = dma_bootstrap.agp_mode;
|
||||
dma_bootstrap32.agp_size = dma_bootstrap.agp_size;
|
||||
if (copy_to_user((void __user *)arg, &dma_bootstrap32,
|
||||
sizeof(dma_bootstrap32)))
|
||||
return -EFAULT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct {
|
||||
drm_ioctl_compat_t *fn;
|
||||
char *name;
|
||||
} mga_compat_ioctls[] = {
|
||||
#define DRM_IOCTL32_DEF(n, f)[DRM_##n] = {.fn = f, .name = #n}
|
||||
DRM_IOCTL32_DEF(MGA_INIT, compat_mga_init),
|
||||
DRM_IOCTL32_DEF(MGA_GETPARAM, compat_mga_getparam),
|
||||
DRM_IOCTL32_DEF(MGA_DMA_BOOTSTRAP, compat_mga_dma_bootstrap),
|
||||
};
|
||||
|
||||
/**
|
||||
* mga_compat_ioctl - Called whenever a 32-bit process running under
|
||||
* a 64-bit kernel performs an ioctl on /dev/dri/card<n>.
|
||||
*
|
||||
* @filp: file pointer.
|
||||
* @cmd: command.
|
||||
* @arg: user argument.
|
||||
* return: zero on success or negative number on failure.
|
||||
*/
|
||||
long mga_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
|
||||
{
|
||||
unsigned int nr = DRM_IOCTL_NR(cmd);
|
||||
struct drm_file *file_priv = filp->private_data;
|
||||
drm_ioctl_compat_t *fn = NULL;
|
||||
int ret;
|
||||
|
||||
if (nr < DRM_COMMAND_BASE)
|
||||
return drm_compat_ioctl(filp, cmd, arg);
|
||||
|
||||
if (nr >= DRM_COMMAND_BASE + ARRAY_SIZE(mga_compat_ioctls))
|
||||
return drm_ioctl(filp, cmd, arg);
|
||||
|
||||
fn = mga_compat_ioctls[nr - DRM_COMMAND_BASE].fn;
|
||||
if (!fn)
|
||||
return drm_ioctl(filp, cmd, arg);
|
||||
|
||||
DRM_DEBUG("pid=%d, dev=0x%lx, auth=%d, %s\n",
|
||||
task_pid_nr(current),
|
||||
(long)old_encode_dev(file_priv->minor->kdev->devt),
|
||||
file_priv->authenticated,
|
||||
mga_compat_ioctls[nr - DRM_COMMAND_BASE].name);
|
||||
ret = (*fn) (filp, cmd, arg);
|
||||
if (ret)
|
||||
DRM_DEBUG("ret = %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
@ -1,169 +0,0 @@
|
||||
/* mga_irq.c -- IRQ handling for radeon -*- linux-c -*-
|
||||
*/
|
||||
/*
|
||||
* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
|
||||
*
|
||||
* The Weather Channel (TM) funded Tungsten Graphics to develop the
|
||||
* initial release of the Radeon 8500 driver under the XFree86 license.
|
||||
* This notice must be preserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Keith Whitwell <keith@tungstengraphics.com>
|
||||
* Eric Anholt <anholt@FreeBSD.org>
|
||||
*/
|
||||
|
||||
#include "mga_drv.h"
|
||||
|
||||
u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
|
||||
{
|
||||
const drm_mga_private_t *const dev_priv =
|
||||
(drm_mga_private_t *) dev->dev_private;
|
||||
|
||||
if (pipe != 0)
|
||||
return 0;
|
||||
|
||||
return atomic_read(&dev_priv->vbl_received);
|
||||
}
|
||||
|
||||
|
||||
irqreturn_t mga_driver_irq_handler(int irq, void *arg)
|
||||
{
|
||||
struct drm_device *dev = (struct drm_device *) arg;
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
|
||||
int status;
|
||||
int handled = 0;
|
||||
|
||||
status = MGA_READ(MGA_STATUS);
|
||||
|
||||
/* VBLANK interrupt */
|
||||
if (status & MGA_VLINEPEN) {
|
||||
MGA_WRITE(MGA_ICLEAR, MGA_VLINEICLR);
|
||||
atomic_inc(&dev_priv->vbl_received);
|
||||
drm_handle_vblank(dev, 0);
|
||||
handled = 1;
|
||||
}
|
||||
|
||||
/* SOFTRAP interrupt */
|
||||
if (status & MGA_SOFTRAPEN) {
|
||||
const u32 prim_start = MGA_READ(MGA_PRIMADDRESS);
|
||||
const u32 prim_end = MGA_READ(MGA_PRIMEND);
|
||||
|
||||
|
||||
MGA_WRITE(MGA_ICLEAR, MGA_SOFTRAPICLR);
|
||||
|
||||
/* In addition to clearing the interrupt-pending bit, we
|
||||
* have to write to MGA_PRIMEND to re-start the DMA operation.
|
||||
*/
|
||||
if ((prim_start & ~0x03) != (prim_end & ~0x03))
|
||||
MGA_WRITE(MGA_PRIMEND, prim_end);
|
||||
|
||||
atomic_inc(&dev_priv->last_fence_retired);
|
||||
wake_up(&dev_priv->fence_queue);
|
||||
handled = 1;
|
||||
}
|
||||
|
||||
if (handled)
|
||||
return IRQ_HANDLED;
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
int mga_enable_vblank(struct drm_device *dev, unsigned int pipe)
|
||||
{
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
|
||||
|
||||
if (pipe != 0) {
|
||||
DRM_ERROR("tried to enable vblank on non-existent crtc %u\n",
|
||||
pipe);
|
||||
return 0;
|
||||
}
|
||||
|
||||
MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void mga_disable_vblank(struct drm_device *dev, unsigned int pipe)
|
||||
{
|
||||
if (pipe != 0) {
|
||||
DRM_ERROR("tried to disable vblank on non-existent crtc %u\n",
|
||||
pipe);
|
||||
}
|
||||
|
||||
/* Do *NOT* disable the vertical refresh interrupt. MGA doesn't have
|
||||
* a nice hardware counter that tracks the number of refreshes when
|
||||
* the interrupt is disabled, and the kernel doesn't know the refresh
|
||||
* rate to calculate an estimate.
|
||||
*/
|
||||
/* MGA_WRITE(MGA_IEN, MGA_VLINEIEN | MGA_SOFTRAPEN); */
|
||||
}
|
||||
|
||||
void mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence)
|
||||
{
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
|
||||
unsigned int cur_fence;
|
||||
|
||||
/* Assume that the user has missed the current sequence number
|
||||
* by about a day rather than she wants to wait for years
|
||||
* using fences.
|
||||
*/
|
||||
wait_event_timeout(dev_priv->fence_queue,
|
||||
(((cur_fence = atomic_read(&dev_priv->last_fence_retired))
|
||||
- *sequence) <= (1 << 23)),
|
||||
msecs_to_jiffies(3000));
|
||||
|
||||
*sequence = cur_fence;
|
||||
}
|
||||
|
||||
void mga_driver_irq_preinstall(struct drm_device *dev)
|
||||
{
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
|
||||
|
||||
/* Disable *all* interrupts */
|
||||
MGA_WRITE(MGA_IEN, 0);
|
||||
/* Clear bits if they're already high */
|
||||
MGA_WRITE(MGA_ICLEAR, ~0);
|
||||
}
|
||||
|
||||
int mga_driver_irq_postinstall(struct drm_device *dev)
|
||||
{
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
|
||||
|
||||
init_waitqueue_head(&dev_priv->fence_queue);
|
||||
|
||||
/* Turn on soft trap interrupt. Vertical blank interrupts are enabled
|
||||
* in mga_enable_vblank.
|
||||
*/
|
||||
MGA_WRITE(MGA_IEN, MGA_SOFTRAPEN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mga_driver_irq_uninstall(struct drm_device *dev)
|
||||
{
|
||||
drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
|
||||
if (!dev_priv)
|
||||
return;
|
||||
|
||||
/* Disable *all* interrupts */
|
||||
MGA_WRITE(MGA_IEN, 0);
|
||||
|
||||
dev->irq_enabled = false;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,167 +0,0 @@
|
||||
/* mga_warp.c -- Matrox G200/G400 WARP engine management -*- linux-c -*-
|
||||
* Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com
|
||||
*
|
||||
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Gareth Hughes <gareth@valinux.com>
|
||||
*/
|
||||
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/ihex.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "mga_drv.h"
|
||||
|
||||
#define FIRMWARE_G200 "matrox/g200_warp.fw"
|
||||
#define FIRMWARE_G400 "matrox/g400_warp.fw"
|
||||
|
||||
MODULE_FIRMWARE(FIRMWARE_G200);
|
||||
MODULE_FIRMWARE(FIRMWARE_G400);
|
||||
|
||||
#define MGA_WARP_CODE_ALIGN 256 /* in bytes */
|
||||
|
||||
#define WARP_UCODE_SIZE(size) ALIGN(size, MGA_WARP_CODE_ALIGN)
|
||||
|
||||
int mga_warp_install_microcode(drm_mga_private_t *dev_priv)
|
||||
{
|
||||
unsigned char *vcbase = dev_priv->warp->handle;
|
||||
unsigned long pcbase = dev_priv->warp->offset;
|
||||
const char *firmware_name;
|
||||
struct platform_device *pdev;
|
||||
const struct firmware *fw = NULL;
|
||||
const struct ihex_binrec *rec;
|
||||
unsigned int size;
|
||||
int n_pipes, where;
|
||||
int rc = 0;
|
||||
|
||||
switch (dev_priv->chipset) {
|
||||
case MGA_CARD_TYPE_G400:
|
||||
case MGA_CARD_TYPE_G550:
|
||||
firmware_name = FIRMWARE_G400;
|
||||
n_pipes = MGA_MAX_G400_PIPES;
|
||||
break;
|
||||
case MGA_CARD_TYPE_G200:
|
||||
firmware_name = FIRMWARE_G200;
|
||||
n_pipes = MGA_MAX_G200_PIPES;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pdev = platform_device_register_simple("mga_warp", 0, NULL, 0);
|
||||
if (IS_ERR(pdev)) {
|
||||
DRM_ERROR("mga: Failed to register microcode\n");
|
||||
return PTR_ERR(pdev);
|
||||
}
|
||||
rc = request_ihex_firmware(&fw, firmware_name, &pdev->dev);
|
||||
platform_device_unregister(pdev);
|
||||
if (rc) {
|
||||
DRM_ERROR("mga: Failed to load microcode \"%s\"\n",
|
||||
firmware_name);
|
||||
return rc;
|
||||
}
|
||||
|
||||
size = 0;
|
||||
where = 0;
|
||||
for (rec = (const struct ihex_binrec *)fw->data;
|
||||
rec;
|
||||
rec = ihex_next_binrec(rec)) {
|
||||
size += WARP_UCODE_SIZE(be16_to_cpu(rec->len));
|
||||
where++;
|
||||
}
|
||||
|
||||
if (where != n_pipes) {
|
||||
DRM_ERROR("mga: Invalid microcode \"%s\"\n", firmware_name);
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
size = PAGE_ALIGN(size);
|
||||
DRM_DEBUG("MGA ucode size = %d bytes\n", size);
|
||||
if (size > dev_priv->warp->size) {
|
||||
DRM_ERROR("microcode too large! (%u > %lu)\n",
|
||||
size, dev_priv->warp->size);
|
||||
rc = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
||||
memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
|
||||
|
||||
where = 0;
|
||||
for (rec = (const struct ihex_binrec *)fw->data;
|
||||
rec;
|
||||
rec = ihex_next_binrec(rec)) {
|
||||
unsigned int src_size, dst_size;
|
||||
|
||||
DRM_DEBUG(" pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase);
|
||||
dev_priv->warp_pipe_phys[where] = pcbase;
|
||||
src_size = be16_to_cpu(rec->len);
|
||||
dst_size = WARP_UCODE_SIZE(src_size);
|
||||
memcpy(vcbase, rec->data, src_size);
|
||||
pcbase += dst_size;
|
||||
vcbase += dst_size;
|
||||
where++;
|
||||
}
|
||||
|
||||
out:
|
||||
release_firmware(fw);
|
||||
return rc;
|
||||
}
|
||||
|
||||
#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE)
|
||||
|
||||
int mga_warp_init(drm_mga_private_t *dev_priv)
|
||||
{
|
||||
u32 wmisc;
|
||||
|
||||
/* FIXME: Get rid of these damned magic numbers...
|
||||
*/
|
||||
switch (dev_priv->chipset) {
|
||||
case MGA_CARD_TYPE_G400:
|
||||
case MGA_CARD_TYPE_G550:
|
||||
MGA_WRITE(MGA_WIADDR2, MGA_WMODE_SUSPEND);
|
||||
MGA_WRITE(MGA_WGETMSB, 0x00000E00);
|
||||
MGA_WRITE(MGA_WVRTXSZ, 0x00001807);
|
||||
MGA_WRITE(MGA_WACCEPTSEQ, 0x18000000);
|
||||
break;
|
||||
case MGA_CARD_TYPE_G200:
|
||||
MGA_WRITE(MGA_WIADDR, MGA_WMODE_SUSPEND);
|
||||
MGA_WRITE(MGA_WGETMSB, 0x1606);
|
||||
MGA_WRITE(MGA_WVRTXSZ, 7);
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
MGA_WRITE(MGA_WMISC, (MGA_WUCODECACHE_ENABLE |
|
||||
MGA_WMASTER_ENABLE | MGA_WCACHEFLUSH_ENABLE));
|
||||
wmisc = MGA_READ(MGA_WMISC);
|
||||
if (wmisc != WMISC_EXPECTED) {
|
||||
DRM_ERROR("WARP engine config failed! 0x%x != 0x%x\n",
|
||||
wmisc, WMISC_EXPECTED);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,429 +0,0 @@
|
||||
/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
|
||||
* Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
|
||||
*
|
||||
* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
|
||||
* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Jeff Hartmann <jhartmann@valinux.com>
|
||||
* Keith Whitwell <keith@tungstengraphics.com>
|
||||
*
|
||||
* Rewritten by:
|
||||
* Gareth Hughes <gareth@valinux.com>
|
||||
*/
|
||||
|
||||
#ifndef __MGA_DRM_H__
|
||||
#define __MGA_DRM_H__
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* WARNING: If you change any of these defines, make sure to change the
|
||||
* defines in the Xserver file (mga_sarea.h)
|
||||
*/
|
||||
|
||||
#ifndef __MGA_SAREA_DEFINES__
|
||||
#define __MGA_SAREA_DEFINES__
|
||||
|
||||
/* WARP pipe flags
|
||||
*/
|
||||
#define MGA_F 0x1 /* fog */
|
||||
#define MGA_A 0x2 /* alpha */
|
||||
#define MGA_S 0x4 /* specular */
|
||||
#define MGA_T2 0x8 /* multitexture */
|
||||
|
||||
#define MGA_WARP_TGZ 0
|
||||
#define MGA_WARP_TGZF (MGA_F)
|
||||
#define MGA_WARP_TGZA (MGA_A)
|
||||
#define MGA_WARP_TGZAF (MGA_F|MGA_A)
|
||||
#define MGA_WARP_TGZS (MGA_S)
|
||||
#define MGA_WARP_TGZSF (MGA_S|MGA_F)
|
||||
#define MGA_WARP_TGZSA (MGA_S|MGA_A)
|
||||
#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
|
||||
#define MGA_WARP_T2GZ (MGA_T2)
|
||||
#define MGA_WARP_T2GZF (MGA_T2|MGA_F)
|
||||
#define MGA_WARP_T2GZA (MGA_T2|MGA_A)
|
||||
#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
|
||||
#define MGA_WARP_T2GZS (MGA_T2|MGA_S)
|
||||
#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
|
||||
#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
|
||||
#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
|
||||
|
||||
#define MGA_MAX_G200_PIPES 8 /* no multitex */
|
||||
#define MGA_MAX_G400_PIPES 16
|
||||
#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
|
||||
#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
|
||||
|
||||
#define MGA_CARD_TYPE_G200 1
|
||||
#define MGA_CARD_TYPE_G400 2
|
||||
#define MGA_CARD_TYPE_G450 3 /* not currently used */
|
||||
#define MGA_CARD_TYPE_G550 4
|
||||
|
||||
#define MGA_FRONT 0x1
|
||||
#define MGA_BACK 0x2
|
||||
#define MGA_DEPTH 0x4
|
||||
|
||||
/* What needs to be changed for the current vertex dma buffer?
|
||||
*/
|
||||
#define MGA_UPLOAD_CONTEXT 0x1
|
||||
#define MGA_UPLOAD_TEX0 0x2
|
||||
#define MGA_UPLOAD_TEX1 0x4
|
||||
#define MGA_UPLOAD_PIPE 0x8
|
||||
#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
|
||||
#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
|
||||
#define MGA_UPLOAD_2D 0x40
|
||||
#define MGA_WAIT_AGE 0x80 /* handled client-side */
|
||||
#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
|
||||
#if 0
|
||||
#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
|
||||
quiescent */
|
||||
#endif
|
||||
|
||||
/* 32 buffers of 64k each, total 2 meg.
|
||||
*/
|
||||
#define MGA_BUFFER_SIZE (1 << 16)
|
||||
#define MGA_NUM_BUFFERS 128
|
||||
|
||||
/* Keep these small for testing.
|
||||
*/
|
||||
#define MGA_NR_SAREA_CLIPRECTS 8
|
||||
|
||||
/* 2 heaps (1 for card, 1 for agp), each divided into up to 128
|
||||
* regions, subject to a minimum region size of (1<<16) == 64k.
|
||||
*
|
||||
* Clients may subdivide regions internally, but when sharing between
|
||||
* clients, the region size is the minimum granularity.
|
||||
*/
|
||||
|
||||
#define MGA_CARD_HEAP 0
|
||||
#define MGA_AGP_HEAP 1
|
||||
#define MGA_NR_TEX_HEAPS 2
|
||||
#define MGA_NR_TEX_REGIONS 16
|
||||
#define MGA_LOG_MIN_TEX_REGION_SIZE 16
|
||||
|
||||
#define DRM_MGA_IDLE_RETRY 2048
|
||||
|
||||
#endif /* __MGA_SAREA_DEFINES__ */
|
||||
|
||||
/* Setup registers for 3D context
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned int dstorg;
|
||||
unsigned int maccess;
|
||||
unsigned int plnwt;
|
||||
unsigned int dwgctl;
|
||||
unsigned int alphactrl;
|
||||
unsigned int fogcolor;
|
||||
unsigned int wflag;
|
||||
unsigned int tdualstage0;
|
||||
unsigned int tdualstage1;
|
||||
unsigned int fcol;
|
||||
unsigned int stencil;
|
||||
unsigned int stencilctl;
|
||||
} drm_mga_context_regs_t;
|
||||
|
||||
/* Setup registers for 2D, X server
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned int pitch;
|
||||
} drm_mga_server_regs_t;
|
||||
|
||||
/* Setup registers for each texture unit
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned int texctl;
|
||||
unsigned int texctl2;
|
||||
unsigned int texfilter;
|
||||
unsigned int texbordercol;
|
||||
unsigned int texorg;
|
||||
unsigned int texwidth;
|
||||
unsigned int texheight;
|
||||
unsigned int texorg1;
|
||||
unsigned int texorg2;
|
||||
unsigned int texorg3;
|
||||
unsigned int texorg4;
|
||||
} drm_mga_texture_regs_t;
|
||||
|
||||
/* General aging mechanism
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned int head; /* Position of head pointer */
|
||||
unsigned int wrap; /* Primary DMA wrap count */
|
||||
} drm_mga_age_t;
|
||||
|
||||
typedef struct _drm_mga_sarea {
|
||||
/* The channel for communication of state information to the kernel
|
||||
* on firing a vertex dma buffer.
|
||||
*/
|
||||
drm_mga_context_regs_t context_state;
|
||||
drm_mga_server_regs_t server_state;
|
||||
drm_mga_texture_regs_t tex_state[2];
|
||||
unsigned int warp_pipe;
|
||||
unsigned int dirty;
|
||||
unsigned int vertsize;
|
||||
|
||||
/* The current cliprects, or a subset thereof.
|
||||
*/
|
||||
struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
|
||||
unsigned int nbox;
|
||||
|
||||
/* Information about the most recently used 3d drawable. The
|
||||
* client fills in the req_* fields, the server fills in the
|
||||
* exported_ fields and puts the cliprects into boxes, above.
|
||||
*
|
||||
* The client clears the exported_drawable field before
|
||||
* clobbering the boxes data.
|
||||
*/
|
||||
unsigned int req_drawable; /* the X drawable id */
|
||||
unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
|
||||
|
||||
unsigned int exported_drawable;
|
||||
unsigned int exported_index;
|
||||
unsigned int exported_stamp;
|
||||
unsigned int exported_buffers;
|
||||
unsigned int exported_nfront;
|
||||
unsigned int exported_nback;
|
||||
int exported_back_x, exported_front_x, exported_w;
|
||||
int exported_back_y, exported_front_y, exported_h;
|
||||
struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
|
||||
|
||||
/* Counters for aging textures and for client-side throttling.
|
||||
*/
|
||||
unsigned int status[4];
|
||||
unsigned int last_wrap;
|
||||
|
||||
drm_mga_age_t last_frame;
|
||||
unsigned int last_enqueue; /* last time a buffer was enqueued */
|
||||
unsigned int last_dispatch; /* age of the most recently dispatched buffer */
|
||||
unsigned int last_quiescent; /* */
|
||||
|
||||
/* LRU lists for texture memory in agp space and on the card.
|
||||
*/
|
||||
struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
|
||||
unsigned int texAge[MGA_NR_TEX_HEAPS];
|
||||
|
||||
/* Mechanism to validate card state.
|
||||
*/
|
||||
int ctxOwner;
|
||||
} drm_mga_sarea_t;
|
||||
|
||||
/* MGA specific ioctls
|
||||
* The device specific ioctl range is 0x40 to 0x79.
|
||||
*/
|
||||
#define DRM_MGA_INIT 0x00
|
||||
#define DRM_MGA_FLUSH 0x01
|
||||
#define DRM_MGA_RESET 0x02
|
||||
#define DRM_MGA_SWAP 0x03
|
||||
#define DRM_MGA_CLEAR 0x04
|
||||
#define DRM_MGA_VERTEX 0x05
|
||||
#define DRM_MGA_INDICES 0x06
|
||||
#define DRM_MGA_ILOAD 0x07
|
||||
#define DRM_MGA_BLIT 0x08
|
||||
#define DRM_MGA_GETPARAM 0x09
|
||||
|
||||
/* 3.2:
|
||||
* ioctls for operating on fences.
|
||||
*/
|
||||
#define DRM_MGA_SET_FENCE 0x0a
|
||||
#define DRM_MGA_WAIT_FENCE 0x0b
|
||||
#define DRM_MGA_DMA_BOOTSTRAP 0x0c
|
||||
|
||||
#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
|
||||
#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, struct drm_lock)
|
||||
#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
|
||||
#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
|
||||
#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
|
||||
#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
|
||||
#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
|
||||
#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
|
||||
#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
|
||||
#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
|
||||
#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32)
|
||||
#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32)
|
||||
#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
|
||||
|
||||
typedef struct _drm_mga_warp_index {
|
||||
int installed;
|
||||
unsigned long phys_addr;
|
||||
int size;
|
||||
} drm_mga_warp_index_t;
|
||||
|
||||
typedef struct drm_mga_init {
|
||||
enum {
|
||||
MGA_INIT_DMA = 0x01,
|
||||
MGA_CLEANUP_DMA = 0x02
|
||||
} func;
|
||||
|
||||
unsigned long sarea_priv_offset;
|
||||
|
||||
__struct_group(/* no tag */, always32bit, /* no attrs */,
|
||||
int chipset;
|
||||
int sgram;
|
||||
|
||||
unsigned int maccess;
|
||||
|
||||
unsigned int fb_cpp;
|
||||
unsigned int front_offset, front_pitch;
|
||||
unsigned int back_offset, back_pitch;
|
||||
|
||||
unsigned int depth_cpp;
|
||||
unsigned int depth_offset, depth_pitch;
|
||||
|
||||
unsigned int texture_offset[MGA_NR_TEX_HEAPS];
|
||||
unsigned int texture_size[MGA_NR_TEX_HEAPS];
|
||||
);
|
||||
|
||||
unsigned long fb_offset;
|
||||
unsigned long mmio_offset;
|
||||
unsigned long status_offset;
|
||||
unsigned long warp_offset;
|
||||
unsigned long primary_offset;
|
||||
unsigned long buffers_offset;
|
||||
} drm_mga_init_t;
|
||||
|
||||
typedef struct drm_mga_dma_bootstrap {
|
||||
/**
|
||||
* \name AGP texture region
|
||||
*
|
||||
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
|
||||
* be filled in with the actual AGP texture settings.
|
||||
*
|
||||
* \warning
|
||||
* If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
|
||||
* is zero, it means that PCI memory (most likely through the use of
|
||||
* an IOMMU) is being used for "AGP" textures.
|
||||
*/
|
||||
/*@{ */
|
||||
unsigned long texture_handle; /**< Handle used to map AGP textures. */
|
||||
__u32 texture_size; /**< Size of the AGP texture region. */
|
||||
/*@} */
|
||||
|
||||
/**
|
||||
* Requested size of the primary DMA region.
|
||||
*
|
||||
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
|
||||
* filled in with the actual AGP mode. If AGP was not available
|
||||
*/
|
||||
__u32 primary_size;
|
||||
|
||||
/**
|
||||
* Requested number of secondary DMA buffers.
|
||||
*
|
||||
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
|
||||
* filled in with the actual number of secondary DMA buffers
|
||||
* allocated. Particularly when PCI DMA is used, this may be
|
||||
* (subtantially) less than the number requested.
|
||||
*/
|
||||
__u32 secondary_bin_count;
|
||||
|
||||
/**
|
||||
* Requested size of each secondary DMA buffer.
|
||||
*
|
||||
* While the kernel \b is free to reduce
|
||||
* dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
|
||||
* to reduce dma_mga_dma_bootstrap::secondary_bin_size.
|
||||
*/
|
||||
__u32 secondary_bin_size;
|
||||
|
||||
/**
|
||||
* Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
|
||||
* \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
|
||||
* zero, it means that PCI DMA should be used, even if AGP is
|
||||
* possible.
|
||||
*
|
||||
* On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
|
||||
* filled in with the actual AGP mode. If AGP was not available
|
||||
* (i.e., PCI DMA was used), this value will be zero.
|
||||
*/
|
||||
__u32 agp_mode;
|
||||
|
||||
/**
|
||||
* Desired AGP GART size, measured in megabytes.
|
||||
*/
|
||||
__u8 agp_size;
|
||||
} drm_mga_dma_bootstrap_t;
|
||||
|
||||
typedef struct drm_mga_clear {
|
||||
unsigned int flags;
|
||||
unsigned int clear_color;
|
||||
unsigned int clear_depth;
|
||||
unsigned int color_mask;
|
||||
unsigned int depth_mask;
|
||||
} drm_mga_clear_t;
|
||||
|
||||
typedef struct drm_mga_vertex {
|
||||
int idx; /* buffer to queue */
|
||||
int used; /* bytes in use */
|
||||
int discard; /* client finished with buffer? */
|
||||
} drm_mga_vertex_t;
|
||||
|
||||
typedef struct drm_mga_indices {
|
||||
int idx; /* buffer to queue */
|
||||
unsigned int start;
|
||||
unsigned int end;
|
||||
int discard; /* client finished with buffer? */
|
||||
} drm_mga_indices_t;
|
||||
|
||||
typedef struct drm_mga_iload {
|
||||
int idx;
|
||||
unsigned int dstorg;
|
||||
unsigned int length;
|
||||
} drm_mga_iload_t;
|
||||
|
||||
typedef struct _drm_mga_blit {
|
||||
unsigned int planemask;
|
||||
unsigned int srcorg;
|
||||
unsigned int dstorg;
|
||||
int src_pitch, dst_pitch;
|
||||
int delta_sx, delta_sy;
|
||||
int delta_dx, delta_dy;
|
||||
int height, ydir; /* flip image vertically */
|
||||
int source_pitch, dest_pitch;
|
||||
} drm_mga_blit_t;
|
||||
|
||||
/* 3.1: An ioctl to get parameters that aren't available to the 3d
|
||||
* client any other way.
|
||||
*/
|
||||
#define MGA_PARAM_IRQ_NR 1
|
||||
|
||||
/* 3.2: Query the actual card type. The DDX only distinguishes between
|
||||
* G200 chips and non-G200 chips, which it calls G400. It turns out that
|
||||
* there are some very sublte differences between the G4x0 chips and the G550
|
||||
* chips. Using this parameter query, a client-side driver can detect the
|
||||
* difference between a G4x0 and a G550.
|
||||
*/
|
||||
#define MGA_PARAM_CARD_TYPE 2
|
||||
|
||||
typedef struct drm_mga_getparam {
|
||||
int param;
|
||||
void __user *value;
|
||||
} drm_mga_getparam_t;
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user