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Blackfin: update anomaly lists to latest public info
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
4e12b08b72
commit
979365ba4e
@ -11,10 +11,9 @@
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*/
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/* This file should be up to date with:
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* - Revision E, 01/26/2010; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
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* - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
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*/
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/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
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#if __SILICON_REVISION__ < 0
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# error will not work on BF518 silicon version
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#endif
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@ -77,19 +76,29 @@
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* PLL Latches Incorrect Settings During Reset */
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#define ANOMALY_05000469 (1)
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#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
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/* Incorrect Default MSEL Value in PLL_CTL */
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#define ANOMALY_05000472 (1)
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#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* IFLUSH sucks at life */
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/* PLL Latches Incorrect Settings During Reset */
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#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
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/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
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#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
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/* SPI Master Boot Can Fail Under Certain Conditions */
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#define ANOMALY_05000490 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_05000491 (1)
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
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#define ANOMALY_05000494 (1)
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/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
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#define ANOMALY_05000498 (1)
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
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#define ANOMALY_05000501 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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@ -157,6 +166,5 @@
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#define ANOMALY_05000474 (0)
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#define ANOMALY_05000475 (0)
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#define ANOMALY_05000480 (0)
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#define ANOMALY_05000485 (0)
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#endif
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@ -11,8 +11,8 @@
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*/
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/* This file should be up to date with:
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* - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
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* - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
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* - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
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* - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -57,7 +57,7 @@
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/* Incorrect Access of OTP_STATUS During otp_write() Function */
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#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
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/* Host DMA Boot Modes Are Not Functional */
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#define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
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#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
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/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
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#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
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/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
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@ -135,7 +135,7 @@
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/* Incorrect Default Internal Voltage Regulator Setting */
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#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
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/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
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#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))
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#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
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/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
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#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
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/* DEB2_URGENT Bit Not Functional */
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@ -181,11 +181,11 @@
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* The WURESET Bit in the SYSCR Register is not Functional */
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#define ANOMALY_05000445 (1)
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/* USB DMA Mode 1 Short Packet Data Corruption */
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#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
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/* USB DMA Short Packet Data Corruption */
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#define ANOMALY_05000450 (1)
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/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
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#define ANOMALY_05000451 (1)
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#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
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/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
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#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
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/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
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@ -198,19 +198,19 @@
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* USB Rx DMA hang */
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/* USB Rx DMA Hang */
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#define ANOMALY_05000465 (1)
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/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
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#define ANOMALY_05000466 (1)
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/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
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/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
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#define ANOMALY_05000467 (1)
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/* PLL Latches Incorrect Settings During Reset */
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#define ANOMALY_05000469 (1)
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/* Incorrect Default MSEL Value in PLL_CTL */
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#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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/* Possible Lockup Condition when Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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@ -219,11 +219,19 @@
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/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
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#define ANOMALY_05000483 (1)
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/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
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#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
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#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
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/* The CODEC Zero-Cross Detect Feature is not Functional */
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#define ANOMALY_05000487 (1)
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/* IFLUSH sucks at life */
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/* SPI Master Boot Can Fail Under Certain Conditions */
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#define ANOMALY_05000490 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_05000491 (1)
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
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#define ANOMALY_05000494 (1)
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/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
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#define ANOMALY_05000498 (1)
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
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#define ANOMALY_05000501 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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@ -11,7 +11,7 @@
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*/
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/* This file should be up to date with:
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* - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
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* - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -152,7 +152,7 @@
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#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
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/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
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#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
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/* False Hardware Error Exception when ISR Context Is Not Restored */
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/* False Hardware Error when ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
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/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
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#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
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@ -210,18 +210,25 @@
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#define ANOMALY_05000462 (1)
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/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
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#define ANOMALY_05000471 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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/* Possible Lockup Condition when Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* IFLUSH sucks at life */
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/* PLL May Latch Incorrect Values Coming Out of Reset */
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#define ANOMALY_05000489 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_05000491 (1)
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
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#define ANOMALY_05000494 (1)
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
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#define ANOMALY_05000501 (1)
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/* These anomalies have been "phased" out of analog.com anomaly sheets and are
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/*
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* These anomalies have been "phased" out of analog.com anomaly sheets and are
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* here to show running on older silicon just isn't feasible.
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*/
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@ -11,7 +11,7 @@
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*/
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/* This file should be up to date with:
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* - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
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* - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -44,18 +44,12 @@
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
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#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
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/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
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#define ANOMALY_05000180 (1)
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/* Instruction Cache Is Not Functional */
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#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
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/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
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#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Buffered CLKIN Output Is Disabled by Default */
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#define ANOMALY_05000247 (1)
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/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
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#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
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/* EMAC TX DMA Error After an Early Frame Abort */
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@ -98,7 +92,7 @@
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#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
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/* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
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#define ANOMALY_05000280 (1)
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/* False Hardware Error Exception when ISR Context Is Not Restored */
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/* False Hardware Error when ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
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/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
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#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
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@ -162,9 +156,9 @@
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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/* Possible Lockup Condition when Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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@ -172,8 +166,26 @@
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#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* IFLUSH sucks at life */
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/* PLL May Latch Incorrect Values Coming Out of Reset */
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#define ANOMALY_05000489 (1)
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/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
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#define ANOMALY_05000491 (1)
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/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
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#define ANOMALY_05000494 (1)
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/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
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#define ANOMALY_05000501 (1)
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/*
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* These anomalies have been "phased" out of analog.com anomaly sheets and are
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* here to show running on older silicon just isn't feasible.
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*/
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/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
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#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
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/* Instruction Cache Is Not Functional */
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#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
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/* Buffered CLKIN Output Is Disabled by Default */
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#define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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@ -11,8 +11,8 @@
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*/
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/* This file should be up to date with:
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* - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
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* - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
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* - Revision J, 05/23/2011; ADSP-BF538/BF538F Blackfin Processor Anomaly List
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* - Revision O, 05/23/2011; ADSP-BF539/BF539F Blackfin Processor Anomaly List
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*/
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#ifndef _MACH_ANOMALY_H_
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@ -56,25 +56,21 @@
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#define ANOMALY_05000229 (1)
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/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
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#define ANOMALY_05000233 (1)
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/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
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#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Maximum External Clock Speed for Timers */
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#define ANOMALY_05000253 (1)
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/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
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#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
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#define ANOMALY_05000270 (__SILICON_REVISION__ < 4)
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
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#define ANOMALY_05000272 (1)
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#define ANOMALY_05000272 (ANOMALY_BF538)
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/* Writes to Synchronous SDRAM Memory May Be Lost */
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#define ANOMALY_05000273 (__SILICON_REVISION__ < 4)
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/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
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#define ANOMALY_05000277 (__SILICON_REVISION__ < 4)
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/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
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#define ANOMALY_05000278 (__SILICON_REVISION__ < 4)
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/* False Hardware Error Exception when ISR Context Is Not Restored */
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/* False Hardware Error when ISR Context Is Not Restored */
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#define ANOMALY_05000281 (__SILICON_REVISION__ < 4)
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/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
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#define ANOMALY_05000282 (__SILICON_REVISION__ < 4)
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@ -102,8 +98,10 @@
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#define ANOMALY_05000313 (__SILICON_REVISION__ < 4)
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/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
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#define ANOMALY_05000315 (__SILICON_REVISION__ < 4)
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/* PFx Glitch on Write to PORTFIO or PORTFIO_TOGGLE */
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#define ANOMALY_05000317 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000318 */
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/* PFx Glitch on Write to FIO_FLAG_D or FIO_FLAG_T */
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#define ANOMALY_05000318 (ANOMALY_BF539 && __SILICON_REVISION__ < 4)
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#define ANOMALY_05000318 (__SILICON_REVISION__ < 4) /* XXX: Same as 05000317 */
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/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
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#define ANOMALY_05000355 (__SILICON_REVISION__ < 5)
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/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
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@ -134,16 +132,32 @@
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
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#define ANOMALY_05000473 (1)
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/* Possible Lockup Condition whem Modifying PLL from External Memory */
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/* Possible Lockup Condition when Modifying PLL from External Memory */
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#define ANOMALY_05000475 (1)
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/* TESTSET Instruction Cannot Be Interrupted */
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#define ANOMALY_05000477 (1)
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/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
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#define ANOMALY_05000481 (1)
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/* IFLUSH sucks at life */
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/* PLL May Latch Incorrect Values Coming Out of Reset */
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||||
#define ANOMALY_05000489 (1)
|
||||
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
|
||||
#define ANOMALY_05000491 (1)
|
||||
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
|
||||
#define ANOMALY_05000494 (1)
|
||||
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
|
||||
#define ANOMALY_05000501 (1)
|
||||
|
||||
/*
|
||||
* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
*/
|
||||
|
||||
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
|
||||
#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
|
||||
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
|
||||
#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
*/
|
||||
|
||||
/* This file should be up to date with:
|
||||
* - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
* - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
@ -29,25 +29,147 @@
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
|
||||
#define ANOMALY_05000220 (1)
|
||||
#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
|
||||
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
|
||||
#define ANOMALY_05000245 (1)
|
||||
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (1)
|
||||
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
|
||||
#define ANOMALY_05000272 (1)
|
||||
/* False Hardware Error Exception when ISR Context Is Not Restored */
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* FIFO Boot Mode Not Functional */
|
||||
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
|
||||
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
|
||||
/*
|
||||
* Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
|
||||
* shows that the fix itself does not cover all cases.
|
||||
*/
|
||||
#define ANOMALY_05000353 (1)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* External Memory Read Access Hangs Core With PLL Bypass */
|
||||
#define ANOMALY_05000360 (1)
|
||||
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
|
||||
#define ANOMALY_05000365 (1)
|
||||
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
|
||||
#define ANOMALY_05000369 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
|
||||
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
|
||||
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
|
||||
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000379 (1)
|
||||
/* Lockbox SESR Disallows Certain User Interrupts */
|
||||
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
|
||||
#define ANOMALY_05000405 (1)
|
||||
/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
|
||||
#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
|
||||
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
|
||||
#define ANOMALY_05000408 (1)
|
||||
/* Lockbox firmware leaves MDMA0 channel enabled */
|
||||
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
|
||||
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
|
||||
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
|
||||
/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
|
||||
#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
|
||||
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
|
||||
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
|
||||
#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
|
||||
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
|
||||
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
|
||||
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
|
||||
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
|
||||
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
|
||||
#define ANOMALY_05000434 (1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
|
||||
#define ANOMALY_05000446 (1)
|
||||
/* UART IrDA Receiver Fails on Extended Bit Pulses */
|
||||
#define ANOMALY_05000447 (1)
|
||||
/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
|
||||
#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
|
||||
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
|
||||
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
|
||||
/* USB DMA Short Packet Data Corruption */
|
||||
#define ANOMALY_05000450 (1)
|
||||
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
|
||||
#define ANOMALY_05000456 (1)
|
||||
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
|
||||
#define ANOMALY_05000457 (1)
|
||||
/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
|
||||
#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
|
||||
#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
|
||||
/* USB DMA RX Data Corruption */
|
||||
#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
|
||||
/* USB TX DMA Hang */
|
||||
#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
|
||||
/* USB Rx DMA Hang */
|
||||
#define ANOMALY_05000465 (1)
|
||||
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
|
||||
#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
|
||||
/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
|
||||
#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
|
||||
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
|
||||
#define ANOMALY_05000473 (1)
|
||||
/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
|
||||
#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
|
||||
/* TESTSET Instruction Cannot Be Interrupted */
|
||||
#define ANOMALY_05000477 (1)
|
||||
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
|
||||
#define ANOMALY_05000481 (1)
|
||||
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
|
||||
#define ANOMALY_05000483 (1)
|
||||
/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
|
||||
#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
|
||||
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
|
||||
#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
|
||||
/* PLL May Latch Incorrect Values Coming Out of Reset */
|
||||
#define ANOMALY_05000489 (1)
|
||||
/* SPI Master Boot Can Fail Under Certain Conditions */
|
||||
#define ANOMALY_05000490 (1)
|
||||
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
|
||||
#define ANOMALY_05000491 (1)
|
||||
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
|
||||
#define ANOMALY_05000494 (1)
|
||||
/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
|
||||
#define ANOMALY_05000498 (1)
|
||||
/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
|
||||
#define ANOMALY_05000500 (1)
|
||||
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
|
||||
#define ANOMALY_05000501 (1)
|
||||
/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
|
||||
#define ANOMALY_05000502 (1)
|
||||
|
||||
/*
|
||||
* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
*/
|
||||
|
||||
/* False Hardware Error when ISR Context Is Not Restored */
|
||||
#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
|
||||
/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
|
||||
#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
|
||||
/* TWI Slave Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
|
||||
/* FIFO Boot Mode Not Functional */
|
||||
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
|
||||
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
|
||||
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
|
||||
/* Incorrect Access of OTP_STATUS During otp_write() Function */
|
||||
@ -80,40 +202,18 @@
|
||||
#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
|
||||
/* PLL Status Register Is Inaccurate */
|
||||
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
|
||||
/*
|
||||
* Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
|
||||
* shows that the fix itself does not cover all cases.
|
||||
*/
|
||||
#define ANOMALY_05000353 (1)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
|
||||
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
|
||||
#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* External Memory Read Access Hangs Core With PLL Bypass */
|
||||
#define ANOMALY_05000360 (1)
|
||||
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
|
||||
#define ANOMALY_05000365 (1)
|
||||
/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
|
||||
#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
|
||||
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
|
||||
#define ANOMALY_05000369 (1)
|
||||
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
|
||||
#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
|
||||
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
|
||||
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
|
||||
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
|
||||
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
|
||||
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000379 (1)
|
||||
/* 8-Bit NAND Flash Boot Mode Not Functional */
|
||||
#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
|
||||
/* Some ATAPI Modes Are Not Functional */
|
||||
#define ANOMALY_05000383 (1)
|
||||
/* Boot from OTP Memory Not Functional */
|
||||
#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Firmware Routine Not Functional */
|
||||
@ -140,92 +240,10 @@
|
||||
#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
|
||||
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
|
||||
#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
|
||||
/* Lockbox SESR Disallows Certain User Interrupts */
|
||||
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
|
||||
#define ANOMALY_05000405 (1)
|
||||
/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
|
||||
#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
|
||||
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
|
||||
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
|
||||
#define ANOMALY_05000408 (1)
|
||||
/* Lockbox firmware leaves MDMA0 channel enabled */
|
||||
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
|
||||
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
|
||||
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
|
||||
/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
|
||||
#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
|
||||
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
|
||||
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
|
||||
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
|
||||
#define ANOMALY_05000416 (1)
|
||||
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
|
||||
#define ANOMALY_05000425 (1)
|
||||
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
|
||||
#define ANOMALY_05000426 (1)
|
||||
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
|
||||
#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
|
||||
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
|
||||
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
|
||||
/* Software System Reset Corrupts PLL_LOCKCNT Register */
|
||||
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
|
||||
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
|
||||
#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
|
||||
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
|
||||
#define ANOMALY_05000434 (1)
|
||||
/* OTP Write Accesses Not Supported */
|
||||
#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
|
||||
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
|
||||
#define ANOMALY_05000443 (1)
|
||||
/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
|
||||
#define ANOMALY_05000446 (1)
|
||||
/* UART IrDA Receiver Fails on Extended Bit Pulses */
|
||||
#define ANOMALY_05000447 (1)
|
||||
/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
|
||||
#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
|
||||
/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
|
||||
#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
|
||||
/* USB DMA Mode 1 Short Packet Data Corruption */
|
||||
#define ANOMALY_05000450 (1)
|
||||
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
|
||||
#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
|
||||
/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
|
||||
#define ANOMALY_05000456 (1)
|
||||
/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
|
||||
#define ANOMALY_05000457 (1)
|
||||
/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
|
||||
#define ANOMALY_05000460 (1)
|
||||
/* False Hardware Error when RETI Points to Invalid Memory */
|
||||
#define ANOMALY_05000461 (1)
|
||||
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
|
||||
#define ANOMALY_05000462 (1)
|
||||
/* USB DMA RX Data Corruption */
|
||||
#define ANOMALY_05000463 (1)
|
||||
/* USB TX DMA Hang */
|
||||
#define ANOMALY_05000464 (1)
|
||||
/* USB Rx DMA hang */
|
||||
#define ANOMALY_05000465 (1)
|
||||
/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
|
||||
#define ANOMALY_05000466 (1)
|
||||
/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
|
||||
#define ANOMALY_05000467 (1)
|
||||
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
|
||||
#define ANOMALY_05000473 (1)
|
||||
/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
|
||||
#define ANOMALY_05000474 (1)
|
||||
/* TESTSET Instruction Cannot Be Interrupted */
|
||||
#define ANOMALY_05000477 (1)
|
||||
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
|
||||
#define ANOMALY_05000481 (1)
|
||||
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
|
||||
#define ANOMALY_05000483 (1)
|
||||
/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
|
||||
#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
|
||||
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
|
||||
#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
|
||||
/* IFLUSH sucks at life */
|
||||
#define ANOMALY_05000491 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000099 (0)
|
||||
|
||||
@ -11,7 +11,7 @@
|
||||
*/
|
||||
|
||||
/* This file should be up to date with:
|
||||
* - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
* - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
@ -26,62 +26,16 @@
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
|
||||
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
|
||||
/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
|
||||
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
|
||||
/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
|
||||
#define ANOMALY_05000120 (1)
|
||||
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
|
||||
#define ANOMALY_05000122 (1)
|
||||
/* Erroneous Exception when Enabling Cache */
|
||||
#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
|
||||
/* SIGNBITS Instruction Not Functional under Certain Conditions */
|
||||
#define ANOMALY_05000127 (1)
|
||||
/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
|
||||
#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
|
||||
/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
|
||||
#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
|
||||
/* Stall in multi-unit DMA operations */
|
||||
#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
|
||||
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
|
||||
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
|
||||
/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
|
||||
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
|
||||
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
|
||||
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
|
||||
/* DMA and TESTSET conflict when both are accessing external memory */
|
||||
#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
|
||||
/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
|
||||
#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
|
||||
/* MDMA may lose the first few words of a descriptor chain */
|
||||
#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
|
||||
/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
|
||||
#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
|
||||
/* IMDMA S1/D1 Channel May Stall */
|
||||
#define ANOMALY_05000149 (1)
|
||||
/* DMA engine may lose data due to incorrect handshaking */
|
||||
#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
|
||||
/* DMA stalls when all three controllers read data from the same source */
|
||||
#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
|
||||
/* Execution stall when executing in L2 and doing external accesses */
|
||||
#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
|
||||
/* Frame Delay in SPORT Multichannel Mode */
|
||||
#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
|
||||
/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
|
||||
#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
|
||||
/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
|
||||
#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
|
||||
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
|
||||
#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
|
||||
/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
|
||||
#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
|
||||
/* A read from external memory may return a wrong value with data cache enabled */
|
||||
#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
|
||||
/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
|
||||
#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
|
||||
/* DMEM_CONTROL<12> is not set on Reset */
|
||||
#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
|
||||
/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
|
||||
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
|
||||
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
|
||||
#define ANOMALY_05000166 (1)
|
||||
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
|
||||
@ -92,10 +46,6 @@
|
||||
#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
|
||||
/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
|
||||
#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
|
||||
/* DSPID register values incorrect */
|
||||
#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
|
||||
/* DMA vs Core accesses to external memory */
|
||||
#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
|
||||
/* Cache Fill Buffer Data lost */
|
||||
#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
|
||||
/* Overlapping Sequencer and Memory Stalls */
|
||||
@ -124,8 +74,6 @@
|
||||
#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Not Functional at Core Voltage < 1Volt */
|
||||
#define ANOMALY_05000190 (1)
|
||||
/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
|
||||
#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
|
||||
/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
|
||||
#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
|
||||
/* Restarting SPORT in Specific Modes May Cause Data Corruption */
|
||||
@ -217,10 +165,10 @@
|
||||
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
|
||||
#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
|
||||
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
|
||||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
|
||||
#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
|
||||
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
|
||||
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
|
||||
/* False Hardware Error Exception when ISR Context Is Not Restored */
|
||||
/* False Hardware Error when ISR Context Is Not Restored */
|
||||
/* Temporarily walk around for bug 5423 till this issue is confirmed by
|
||||
* official anomaly document. It looks 05000281 still exists on bf561
|
||||
* v0.5.
|
||||
@ -274,8 +222,6 @@
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
|
||||
@ -298,16 +244,82 @@
|
||||
#define ANOMALY_05000462 (1)
|
||||
/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
|
||||
#define ANOMALY_05000471 (1)
|
||||
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
|
||||
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
|
||||
#define ANOMALY_05000473 (1)
|
||||
/* Possible Lockup Condition whem Modifying PLL from External Memory */
|
||||
/* Possible Lockup Condition when Modifying PLL from External Memory */
|
||||
#define ANOMALY_05000475 (1)
|
||||
/* TESTSET Instruction Cannot Be Interrupted */
|
||||
#define ANOMALY_05000477 (1)
|
||||
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
|
||||
#define ANOMALY_05000481 (1)
|
||||
/* IFLUSH sucks at life */
|
||||
/* PLL May Latch Incorrect Values Coming Out of Reset */
|
||||
#define ANOMALY_05000489 (1)
|
||||
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
|
||||
#define ANOMALY_05000491 (1)
|
||||
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
|
||||
#define ANOMALY_05000494 (1)
|
||||
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
|
||||
#define ANOMALY_05000501 (1)
|
||||
|
||||
/*
|
||||
* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
*/
|
||||
|
||||
/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
|
||||
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
|
||||
/* Erroneous Exception when Enabling Cache */
|
||||
#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
|
||||
/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
|
||||
#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
|
||||
/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
|
||||
#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
|
||||
/* Stall in multi-unit DMA operations */
|
||||
#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
|
||||
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
|
||||
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
|
||||
/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
|
||||
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
|
||||
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
|
||||
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
|
||||
/* DMA and TESTSET conflict when both are accessing external memory */
|
||||
#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
|
||||
/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
|
||||
#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
|
||||
/* MDMA may lose the first few words of a descriptor chain */
|
||||
#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
|
||||
/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
|
||||
#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
|
||||
/* DMA engine may lose data due to incorrect handshaking */
|
||||
#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
|
||||
/* DMA stalls when all three controllers read data from the same source */
|
||||
#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
|
||||
/* Execution stall when executing in L2 and doing external accesses */
|
||||
#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
|
||||
/* Frame Delay in SPORT Multichannel Mode */
|
||||
#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
|
||||
/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
|
||||
#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
|
||||
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
|
||||
#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
|
||||
/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
|
||||
#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
|
||||
/* A read from external memory may return a wrong value with data cache enabled */
|
||||
#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
|
||||
/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
|
||||
#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
|
||||
/* DMEM_CONTROL<12> is not set on Reset */
|
||||
#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
|
||||
/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
|
||||
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
|
||||
/* DSPID register values incorrect */
|
||||
#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
|
||||
/* DMA vs Core accesses to external memory */
|
||||
#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
|
||||
/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
|
||||
#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000119 (0)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user