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dt-bindings: clock: document Amlogic S4 SoC peripherals clock controller
Add the S4 peripherals clock controller dt-bindings in the S4 SoC family. Signed-off-by: Yu Tu <yu.tu@amlogic.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230904075504.23263-3-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This commit is contained in:
Yu Tu
Jerome Brunet
parent
923a77a2e1
commit
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amlogic S4 Peripherals Clock Controller
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maintainers:
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- Yu Tu <yu.tu@amlogic.com>
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properties:
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compatible:
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const: amlogic,s4-peripherals-clkc
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reg:
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maxItems: 1
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clocks:
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minItems: 14
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items:
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- description: input fixed pll div2
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- description: input fixed pll div2p5
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- description: input fixed pll div3
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- description: input fixed pll div4
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- description: input fixed pll div5
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- description: input fixed pll div7
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- description: input hifi pll
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- description: input gp0 pll
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- description: input mpll0
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- description: input mpll1
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- description: input mpll2
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- description: input mpll3
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- description: input hdmi pll
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- description: input oscillator (usually at 24MHz)
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- description: input external 32kHz reference (optional)
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clock-names:
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minItems: 14
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items:
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- const: fclk_div2
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- const: fclk_div2p5
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- const: fclk_div3
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- const: fclk_div4
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- const: fclk_div5
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- const: fclk_div7
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- const: hifi_pll
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- const: gp0_pll
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- const: mpll0
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- const: mpll1
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- const: mpll2
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- const: mpll3
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- const: hdmi_pll
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- const: xtal
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- const: ext_32k
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
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clkc_periphs: clock-controller@fe000000 {
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compatible = "amlogic,s4-peripherals-clkc";
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reg = <0xfe000000 0x49c>;
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clocks = <&clkc_pll 3>,
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<&clkc_pll 13>,
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<&clkc_pll 5>,
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<&clkc_pll 7>,
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<&clkc_pll 9>,
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<&clkc_pll 11>,
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<&clkc_pll 17>,
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<&clkc_pll 15>,
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<&clkc_pll 25>,
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<&clkc_pll 27>,
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<&clkc_pll 29>,
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<&clkc_pll 31>,
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<&clkc_pll 20>,
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<&xtal>;
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clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4",
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"fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll",
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"mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal";
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#clock-cells = <1>;
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};
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...
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236
include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
Normal file
236
include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.
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* Author: Yu Tu <yu.tu@amlogic.com>
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*/
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#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
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#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
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#define CLKID_RTC_32K_CLKIN 0
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#define CLKID_RTC_32K_DIV 1
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#define CLKID_RTC_32K_SEL 2
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#define CLKID_RTC_32K_XATL 3
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#define CLKID_RTC 4
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#define CLKID_SYS_CLK_B_SEL 5
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#define CLKID_SYS_CLK_B_DIV 6
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#define CLKID_SYS_CLK_B 7
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#define CLKID_SYS_CLK_A_SEL 8
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#define CLKID_SYS_CLK_A_DIV 9
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#define CLKID_SYS_CLK_A 10
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#define CLKID_SYS 11
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#define CLKID_CECA_32K_CLKIN 12
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#define CLKID_CECA_32K_DIV 13
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#define CLKID_CECA_32K_SEL_PRE 14
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#define CLKID_CECA_32K_SEL 15
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#define CLKID_CECA_32K_CLKOUT 16
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#define CLKID_CECB_32K_CLKIN 17
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#define CLKID_CECB_32K_DIV 18
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#define CLKID_CECB_32K_SEL_PRE 19
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#define CLKID_CECB_32K_SEL 20
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#define CLKID_CECB_32K_CLKOUT 21
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#define CLKID_SC_CLK_SEL 22
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#define CLKID_SC_CLK_DIV 23
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#define CLKID_SC 24
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#define CLKID_12_24M 25
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#define CLKID_12M_CLK_DIV 26
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#define CLKID_12_24M_CLK_SEL 27
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#define CLKID_VID_PLL_DIV 28
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#define CLKID_VID_PLL_SEL 29
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#define CLKID_VID_PLL 30
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#define CLKID_VCLK_SEL 31
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#define CLKID_VCLK2_SEL 32
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#define CLKID_VCLK_INPUT 33
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#define CLKID_VCLK2_INPUT 34
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#define CLKID_VCLK_DIV 35
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#define CLKID_VCLK2_DIV 36
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#define CLKID_VCLK 37
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#define CLKID_VCLK2 38
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#define CLKID_VCLK_DIV1 39
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#define CLKID_VCLK_DIV2_EN 40
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#define CLKID_VCLK_DIV4_EN 41
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#define CLKID_VCLK_DIV6_EN 42
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#define CLKID_VCLK_DIV12_EN 43
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#define CLKID_VCLK2_DIV1 44
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#define CLKID_VCLK2_DIV2_EN 45
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#define CLKID_VCLK2_DIV4_EN 46
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#define CLKID_VCLK2_DIV6_EN 47
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#define CLKID_VCLK2_DIV12_EN 48
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#define CLKID_VCLK_DIV2 49
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#define CLKID_VCLK_DIV4 50
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#define CLKID_VCLK_DIV6 51
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#define CLKID_VCLK_DIV12 52
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#define CLKID_VCLK2_DIV2 53
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#define CLKID_VCLK2_DIV4 54
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#define CLKID_VCLK2_DIV6 55
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#define CLKID_VCLK2_DIV12 56
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#define CLKID_CTS_ENCI_SEL 57
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#define CLKID_CTS_ENCP_SEL 58
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#define CLKID_CTS_VDAC_SEL 59
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#define CLKID_HDMI_TX_SEL 60
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#define CLKID_CTS_ENCI 61
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#define CLKID_CTS_ENCP 62
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#define CLKID_CTS_VDAC 63
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#define CLKID_HDMI_TX 64
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#define CLKID_HDMI_SEL 65
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#define CLKID_HDMI_DIV 66
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#define CLKID_HDMI 67
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#define CLKID_TS_CLK_DIV 68
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#define CLKID_TS 69
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#define CLKID_MALI_0_SEL 70
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#define CLKID_MALI_0_DIV 71
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#define CLKID_MALI_0 72
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#define CLKID_MALI_1_SEL 73
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#define CLKID_MALI_1_DIV 74
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#define CLKID_MALI_1 75
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#define CLKID_MALI_SEL 76
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#define CLKID_VDEC_P0_SEL 77
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#define CLKID_VDEC_P0_DIV 78
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#define CLKID_VDEC_P0 79
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#define CLKID_VDEC_P1_SEL 80
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#define CLKID_VDEC_P1_DIV 81
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#define CLKID_VDEC_P1 82
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#define CLKID_VDEC_SEL 83
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#define CLKID_HEVCF_P0_SEL 84
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#define CLKID_HEVCF_P0_DIV 85
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#define CLKID_HEVCF_P0 86
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#define CLKID_HEVCF_P1_SEL 87
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#define CLKID_HEVCF_P1_DIV 88
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#define CLKID_HEVCF_P1 89
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#define CLKID_HEVCF_SEL 90
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#define CLKID_VPU_0_SEL 91
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#define CLKID_VPU_0_DIV 92
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#define CLKID_VPU_0 93
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#define CLKID_VPU_1_SEL 94
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#define CLKID_VPU_1_DIV 95
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#define CLKID_VPU_1 96
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#define CLKID_VPU 97
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#define CLKID_VPU_CLKB_TMP_SEL 98
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#define CLKID_VPU_CLKB_TMP_DIV 99
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#define CLKID_VPU_CLKB_TMP 100
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#define CLKID_VPU_CLKB_DIV 101
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#define CLKID_VPU_CLKB 102
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#define CLKID_VPU_CLKC_P0_SEL 103
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#define CLKID_VPU_CLKC_P0_DIV 104
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#define CLKID_VPU_CLKC_P0 105
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#define CLKID_VPU_CLKC_P1_SEL 106
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#define CLKID_VPU_CLKC_P1_DIV 107
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#define CLKID_VPU_CLKC_P1 108
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#define CLKID_VPU_CLKC_SEL 109
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#define CLKID_VAPB_0_SEL 110
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#define CLKID_VAPB_0_DIV 111
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#define CLKID_VAPB_0 112
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#define CLKID_VAPB_1_SEL 113
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#define CLKID_VAPB_1_DIV 114
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#define CLKID_VAPB_1 115
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#define CLKID_VAPB 116
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#define CLKID_GE2D 117
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#define CLKID_VDIN_MEAS_SEL 118
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#define CLKID_VDIN_MEAS_DIV 119
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#define CLKID_VDIN_MEAS 120
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#define CLKID_SD_EMMC_C_CLK_SEL 121
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#define CLKID_SD_EMMC_C_CLK_DIV 122
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#define CLKID_SD_EMMC_C 123
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#define CLKID_SD_EMMC_A_CLK_SEL 124
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#define CLKID_SD_EMMC_A_CLK_DIV 125
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#define CLKID_SD_EMMC_A 126
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#define CLKID_SD_EMMC_B_CLK_SEL 127
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#define CLKID_SD_EMMC_B_CLK_DIV 128
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#define CLKID_SD_EMMC_B 129
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#define CLKID_SPICC0_SEL 130
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#define CLKID_SPICC0_DIV 131
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#define CLKID_SPICC0_EN 132
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#define CLKID_PWM_A_SEL 133
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#define CLKID_PWM_A_DIV 134
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#define CLKID_PWM_A 135
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#define CLKID_PWM_B_SEL 136
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#define CLKID_PWM_B_DIV 137
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#define CLKID_PWM_B 138
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#define CLKID_PWM_C_SEL 139
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#define CLKID_PWM_C_DIV 140
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#define CLKID_PWM_C 141
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#define CLKID_PWM_D_SEL 142
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#define CLKID_PWM_D_DIV 143
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#define CLKID_PWM_D 144
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#define CLKID_PWM_E_SEL 145
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#define CLKID_PWM_E_DIV 146
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#define CLKID_PWM_E 147
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#define CLKID_PWM_F_SEL 148
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#define CLKID_PWM_F_DIV 149
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#define CLKID_PWM_F 150
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#define CLKID_PWM_G_SEL 151
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#define CLKID_PWM_G_DIV 152
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#define CLKID_PWM_G 153
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#define CLKID_PWM_H_SEL 154
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#define CLKID_PWM_H_DIV 155
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#define CLKID_PWM_H 156
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#define CLKID_PWM_I_SEL 157
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#define CLKID_PWM_I_DIV 158
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#define CLKID_PWM_I 159
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#define CLKID_PWM_J_SEL 160
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#define CLKID_PWM_J_DIV 161
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#define CLKID_PWM_J 162
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#define CLKID_SARADC_SEL 163
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#define CLKID_SARADC_DIV 164
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#define CLKID_SARADC 165
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#define CLKID_GEN_SEL 166
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#define CLKID_GEN_DIV 167
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#define CLKID_GEN 168
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#define CLKID_DDR 169
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#define CLKID_DOS 170
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#define CLKID_ETHPHY 171
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#define CLKID_MALI 172
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#define CLKID_AOCPU 173
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#define CLKID_AUCPU 174
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#define CLKID_CEC 175
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#define CLKID_SDEMMC_A 176
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#define CLKID_SDEMMC_B 177
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#define CLKID_NAND 178
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#define CLKID_SMARTCARD 179
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#define CLKID_ACODEC 180
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#define CLKID_SPIFC 181
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#define CLKID_MSR 182
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#define CLKID_IR_CTRL 183
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#define CLKID_AUDIO 184
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#define CLKID_ETH 185
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#define CLKID_UART_A 186
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#define CLKID_UART_B 187
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#define CLKID_UART_C 188
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#define CLKID_UART_D 189
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#define CLKID_UART_E 190
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#define CLKID_AIFIFO 191
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#define CLKID_TS_DDR 192
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#define CLKID_TS_PLL 193
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#define CLKID_G2D 194
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#define CLKID_SPICC0 195
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#define CLKID_SPICC1 196
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#define CLKID_USB 197
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#define CLKID_I2C_M_A 198
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#define CLKID_I2C_M_B 199
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#define CLKID_I2C_M_C 200
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#define CLKID_I2C_M_D 201
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#define CLKID_I2C_M_E 202
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#define CLKID_HDMITX_APB 203
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#define CLKID_I2C_S_A 204
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#define CLKID_USB1_TO_DDR 205
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#define CLKID_HDCP22 206
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#define CLKID_MMC_APB 207
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#define CLKID_RSA 208
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#define CLKID_CPU_DEBUG 209
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#define CLKID_VPU_INTR 210
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#define CLKID_DEMOD 211
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#define CLKID_SAR_ADC 212
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#define CLKID_GIC 213
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#define CLKID_PWM_AB 214
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#define CLKID_PWM_CD 215
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#define CLKID_PWM_EF 216
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#define CLKID_PWM_GH 217
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#define CLKID_PWM_IJ 218
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#define CLKID_HDCP22_ESMCLK_SEL 219
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#define CLKID_HDCP22_ESMCLK_DIV 220
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#define CLKID_HDCP22_ESMCLK 221
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#define CLKID_HDCP22_SKPCLK_SEL 222
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#define CLKID_HDCP22_SKPCLK_DIV 223
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#define CLKID_HDCP22_SKPCLK 224
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#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */
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