mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-01-17 02:15:57 +00:00
- added support for QCN550x (ath79)
- enabled KCSAN - removed TX39XX support - various cleanups and fixes -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmI91VkaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHBFDQ/9FA6rU1FgoHbwBPDUSWdq sdUwm4ndfzPa1zm9vH0jl9ZGEeDJq9f/ntmdouvnW4YIpUYcRx+BhRN/m0W84Pm5 WDvL6FxsWnwgeugbpCKiTE+fJR1febEehyTWxDX3qoQPh1DabnGlHSQUhYhZPwD+ 1ZaGMuWfKdstwR5dYiHLR1BGqunuc/ENoqYrwY+bDvjTL5VL6ZPB1D2JEIZGmmCl d4/DvbXSHcXCY5JGu6Il9SjI5o8LpDJx7IueAxiiLn0m/MoZ7Bt7OHyOYZgMaJob XYUG8UipREGZaOy4DMy1DRgXBVGSEOr/3oWIFJWFzDxw7J99TWvy+lkMdNiiW/lO QRt/2hb1Rfa1LinpbF+ac1hhj+SMI8T+tuMaiv4oG8/qwttMssMoLQN5h+f2fJf+ QkGVEMkvpi/xWkjZ3sQj9SCMKDpBG7az7fleRowX1ahCRApGUkw2pPdl5bt75kpv Qx5J1fpmofzPW63NHRjsvjEq7Z9BhDf/O0aZnAEnmIhw44sM9zpoorQcvvIUYBzr zLPzOCIegJISNiV28oinov1CrwaR/ZF3y4HabbsrAs9VxBBUOjJIERbkB7KKvjYG GN30xtoX3tjNfeIy98kyWm4m0lvc4+eCdUIHbCsEnEAmgMEbRpxZXCBlVF5Ulh2q eaEO9aRVCz1wGY1DW7HVRLc= =xFZN -----END PGP SIGNATURE----- Merge tag 'mips_5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - added support for QCN550x (ath79) - enabled KCSAN - removed TX39XX support - various cleanups and fixes * tag 'mips_5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (31 commits) MIPS: Fix build error for loongson64 and sgi-ip27 MIPS: ingenic: correct unit node address MIPS: Fix wrong comments in asm/prom.h MIPS: Remove redundant definitions of device_tree_init() MIPS: Remove redundant check in device_tree_init() MIPS: pgalloc: fix memory leak caused by pgd_free() MIPS: RB532: fix return value of __setup handler MIPS: Only use current_stack_pointer on GCC MIPS: boot/compressed: Use array reference for image bounds mips: cdmm: Fix refcount leak in mips_cdmm_phys_base mips: remove reference to "newer Loongson-3" mips: Always permit to build u-boot images MIPS: Sanitise Cavium switch cases in TLB handler synthesizers DEC: Limit PMAX memory probing to R3k systems mips: DEC: honor CONFIG_MIPS_FP_SUPPORT=n MIPS: fix fortify panic when copying asm exception handlers mips: ralink: fix a refcount leak in ill_acc_of_setup() mips: Implement "current_stack_pointer" MIPS: Remove TX39XX support MIPS: Modernize READ_IMPLIES_EXEC ...
This commit is contained in:
Linus Torvalds
commit
9a8b3d5f71
@ -32,7 +32,6 @@ platform-$(CONFIG_SIBYTE_SB1250) += sibyte/
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|||||||
platform-$(CONFIG_SIBYTE_BCM1x55) += sibyte/
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platform-$(CONFIG_SIBYTE_BCM1x55) += sibyte/
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platform-$(CONFIG_SIBYTE_BCM1x80) += sibyte/
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platform-$(CONFIG_SIBYTE_BCM1x80) += sibyte/
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platform-$(CONFIG_SNI_RM) += sni/
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platform-$(CONFIG_SNI_RM) += sni/
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||||||
platform-$(CONFIG_MACH_TX39XX) += txx9/
|
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platform-$(CONFIG_MACH_TX49XX) += txx9/
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platform-$(CONFIG_MACH_TX49XX) += txx9/
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platform-$(CONFIG_MACH_VR41XX) += vr41xx/
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platform-$(CONFIG_MACH_VR41XX) += vr41xx/
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|
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@ -4,6 +4,7 @@ config MIPS
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default y
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default y
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select ARCH_32BIT_OFF_T if !64BIT
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select ARCH_32BIT_OFF_T if !64BIT
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select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
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select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
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select ARCH_HAS_CURRENT_STACK_POINTER if !CC_IS_CLANG || CLANG_VERSION >= 140000
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select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
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select ARCH_HAS_DEBUG_VIRTUAL if !64BIT
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select ARCH_HAS_FORTIFY_SOURCE
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select ARCH_HAS_FORTIFY_SOURCE
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select ARCH_HAS_KCOV
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select ARCH_HAS_KCOV
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@ -101,6 +102,7 @@ config MIPS
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select TRACE_IRQFLAGS_SUPPORT
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select TRACE_IRQFLAGS_SUPPORT
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select VIRT_TO_BUS
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select VIRT_TO_BUS
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select ARCH_HAS_ELFCORE_COMPAT
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select ARCH_HAS_ELFCORE_COMPAT
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select HAVE_ARCH_KCSAN if 64BIT
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config MIPS_FIXUP_BIGPHYS_ADDR
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config MIPS_FIXUP_BIGPHYS_ADDR
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bool
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bool
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@ -511,6 +513,7 @@ config MACH_LOONGSON64
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select USE_OF
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select USE_OF
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select BUILTIN_DTB
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select BUILTIN_DTB
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select PCI_HOST_GENERIC
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select PCI_HOST_GENERIC
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select HAVE_ARCH_NODEDATA_EXTENSION if NUMA
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help
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help
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This enables the support of Loongson-2/3 family of machines.
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This enables the support of Loongson-2/3 family of machines.
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@ -707,6 +710,7 @@ config SGI_IP27
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select WAR_R10000_LLSC
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select WAR_R10000_LLSC
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select MIPS_L1_CACHE_SHIFT_7
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select MIPS_L1_CACHE_SHIFT_7
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select NUMA
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select NUMA
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select HAVE_ARCH_NODEDATA_EXTENSION
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help
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help
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This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
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This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
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workstations. To compile a Linux kernel that runs on these, say Y
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workstations. To compile a Linux kernel that runs on these, say Y
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@ -926,9 +930,6 @@ config SNI_RM
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Technology and now in turn merged with Fujitsu. Say Y here to
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Technology and now in turn merged with Fujitsu. Say Y here to
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support this machine type.
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support this machine type.
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|
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config MACH_TX39XX
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bool "Toshiba TX39 series based machines"
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config MACH_TX49XX
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config MACH_TX49XX
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bool "Toshiba TX49 series based machines"
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bool "Toshiba TX49 series based machines"
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select WAR_TX49XX_ICACHE_INDEX_INV
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select WAR_TX49XX_ICACHE_INDEX_INV
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@ -1343,19 +1344,14 @@ config LOONGSON3_ENHANCEMENT
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new Loongson-3 machines only, please say 'Y' here.
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new Loongson-3 machines only, please say 'Y' here.
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|
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config CPU_LOONGSON3_WORKAROUNDS
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config CPU_LOONGSON3_WORKAROUNDS
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bool "Old Loongson-3 LLSC Workarounds"
|
bool "Loongson-3 LLSC Workarounds"
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default y if SMP
|
default y if SMP
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depends on CPU_LOONGSON64
|
depends on CPU_LOONGSON64
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help
|
help
|
||||||
Loongson-3 processors have the llsc issues which require workarounds.
|
Loongson-3 processors have the llsc issues which require workarounds.
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Without workarounds the system may hang unexpectedly.
|
Without workarounds the system may hang unexpectedly.
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|
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Newer Loongson-3 will fix these issues and no workarounds are needed.
|
Say Y, unless you know what you are doing.
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The workarounds have no significant side effect on them but may
|
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decrease the performance of the system so this option should be
|
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||||||
disabled unless the kernel is intended to be run on old systems.
|
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|
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If unsure, please say Y.
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|
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config CPU_LOONGSON3_CPUCFG_EMULATION
|
config CPU_LOONGSON3_CPUCFG_EMULATION
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bool "Emulate the CPUCFG instruction on older Loongson cores"
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bool "Emulate the CPUCFG instruction on older Loongson cores"
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@ -1583,12 +1579,6 @@ config CPU_R3000
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might be a safe bet. If the resulting kernel does not work,
|
might be a safe bet. If the resulting kernel does not work,
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try to recompile with R3000.
|
try to recompile with R3000.
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|
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config CPU_TX39XX
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bool "R39XX"
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depends on SYS_HAS_CPU_TX39XX
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_R3K_TLB
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config CPU_VR41XX
|
config CPU_VR41XX
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bool "R41xx"
|
bool "R41xx"
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depends on SYS_HAS_CPU_VR41XX
|
depends on SYS_HAS_CPU_VR41XX
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@ -1915,9 +1905,6 @@ config SYS_HAS_CPU_P5600
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config SYS_HAS_CPU_R3000
|
config SYS_HAS_CPU_R3000
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bool
|
bool
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||||||
|
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config SYS_HAS_CPU_TX39XX
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bool
|
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config SYS_HAS_CPU_VR41XX
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config SYS_HAS_CPU_VR41XX
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bool
|
bool
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|
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@ -2148,7 +2135,7 @@ config PAGE_SIZE_8KB
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|
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config PAGE_SIZE_16KB
|
config PAGE_SIZE_16KB
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bool "16kB"
|
bool "16kB"
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depends on !CPU_R3000 && !CPU_TX39XX
|
depends on !CPU_R3000
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help
|
help
|
||||||
Using 16kB page size will result in higher performance kernel at
|
Using 16kB page size will result in higher performance kernel at
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the price of higher memory consumption. This option is available on
|
the price of higher memory consumption. This option is available on
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@ -2167,7 +2154,7 @@ config PAGE_SIZE_32KB
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|||||||
|
|
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config PAGE_SIZE_64KB
|
config PAGE_SIZE_64KB
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bool "64kB"
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bool "64kB"
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||||||
depends on !CPU_R3000 && !CPU_TX39XX
|
depends on !CPU_R3000
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||||||
help
|
help
|
||||||
Using 64kB page size will result in higher performance kernel at
|
Using 64kB page size will result in higher performance kernel at
|
||||||
the price of higher memory consumption. This option is available on
|
the price of higher memory consumption. This option is available on
|
||||||
@ -2235,7 +2222,7 @@ config CPU_HAS_PREFETCH
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|||||||
|
|
||||||
config CPU_GENERIC_DUMP_TLB
|
config CPU_GENERIC_DUMP_TLB
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||||||
bool
|
bool
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||||||
default y if !(CPU_R3000 || CPU_TX39XX)
|
default y if !CPU_R3000
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||||||
|
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||||||
config MIPS_FP_SUPPORT
|
config MIPS_FP_SUPPORT
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||||||
bool "Floating Point support" if EXPERT
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bool "Floating Point support" if EXPERT
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||||||
@ -2255,7 +2242,7 @@ config MIPS_FP_SUPPORT
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|||||||
config CPU_R2300_FPU
|
config CPU_R2300_FPU
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||||||
bool
|
bool
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||||||
depends on MIPS_FP_SUPPORT
|
depends on MIPS_FP_SUPPORT
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||||||
default y if CPU_R3000 || CPU_TX39XX
|
default y if CPU_R3000
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||||||
|
|
||||||
config CPU_R3K_TLB
|
config CPU_R3K_TLB
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||||||
bool
|
bool
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||||||
@ -2520,13 +2507,51 @@ config CPU_HAS_SYNC
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|||||||
#
|
#
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||||||
# CPU non-features
|
# CPU non-features
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||||||
#
|
#
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||||||
|
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||||||
|
# Work around the "daddi" and "daddiu" CPU errata:
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||||||
|
#
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||||||
|
# - The `daddi' instruction fails to trap on overflow.
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|
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
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|
# erratum #23
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||||||
|
#
|
||||||
|
# - The `daddiu' instruction can produce an incorrect result.
|
||||||
|
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
|
||||||
|
# erratum #41
|
||||||
|
# "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
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|
# #15
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|
# "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
|
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|
# "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
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config CPU_DADDI_WORKAROUNDS
|
config CPU_DADDI_WORKAROUNDS
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bool
|
bool
|
||||||
|
|
||||||
|
# Work around certain R4000 CPU errata (as implemented by GCC):
|
||||||
|
#
|
||||||
|
# - A double-word or a variable shift may give an incorrect result
|
||||||
|
# if executed immediately after starting an integer division:
|
||||||
|
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
|
||||||
|
# erratum #28
|
||||||
|
# "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
|
||||||
|
# #19
|
||||||
|
#
|
||||||
|
# - A double-word or a variable shift may give an incorrect result
|
||||||
|
# if executed while an integer multiplication is in progress:
|
||||||
|
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
|
||||||
|
# errata #16 & #28
|
||||||
|
#
|
||||||
|
# - An integer division may give an incorrect result if started in
|
||||||
|
# a delay slot of a taken branch or a jump:
|
||||||
|
# "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
|
||||||
|
# erratum #52
|
||||||
config CPU_R4000_WORKAROUNDS
|
config CPU_R4000_WORKAROUNDS
|
||||||
bool
|
bool
|
||||||
select CPU_R4400_WORKAROUNDS
|
select CPU_R4400_WORKAROUNDS
|
||||||
|
|
||||||
|
# Work around certain R4400 CPU errata (as implemented by GCC):
|
||||||
|
#
|
||||||
|
# - A double-word or a variable shift may give an incorrect result
|
||||||
|
# if executed immediately after starting an integer division:
|
||||||
|
# "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
|
||||||
|
# "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
|
||||||
config CPU_R4400_WORKAROUNDS
|
config CPU_R4400_WORKAROUNDS
|
||||||
bool
|
bool
|
||||||
|
|
||||||
@ -2536,13 +2561,13 @@ config CPU_R4X00_BUGS64
|
|||||||
|
|
||||||
config MIPS_ASID_SHIFT
|
config MIPS_ASID_SHIFT
|
||||||
int
|
int
|
||||||
default 6 if CPU_R3000 || CPU_TX39XX
|
default 6 if CPU_R3000
|
||||||
default 0
|
default 0
|
||||||
|
|
||||||
config MIPS_ASID_BITS
|
config MIPS_ASID_BITS
|
||||||
int
|
int
|
||||||
default 0 if MIPS_ASID_BITS_VARIABLE
|
default 0 if MIPS_ASID_BITS_VARIABLE
|
||||||
default 6 if CPU_R3000 || CPU_TX39XX
|
default 6 if CPU_R3000
|
||||||
default 8
|
default 8
|
||||||
|
|
||||||
config MIPS_ASID_BITS_VARIABLE
|
config MIPS_ASID_BITS_VARIABLE
|
||||||
@ -2685,6 +2710,9 @@ config NUMA
|
|||||||
config SYS_SUPPORTS_NUMA
|
config SYS_SUPPORTS_NUMA
|
||||||
bool
|
bool
|
||||||
|
|
||||||
|
config HAVE_ARCH_NODEDATA_EXTENSION
|
||||||
|
bool
|
||||||
|
|
||||||
config RELOCATABLE
|
config RELOCATABLE
|
||||||
bool "Relocatable kernel"
|
bool "Relocatable kernel"
|
||||||
depends on SYS_SUPPORTS_RELOCATABLE
|
depends on SYS_SUPPORTS_RELOCATABLE
|
||||||
@ -3202,6 +3230,10 @@ config MIPS32_N32
|
|||||||
|
|
||||||
If unsure, say N.
|
If unsure, say N.
|
||||||
|
|
||||||
|
config CC_HAS_MNO_BRANCH_LIKELY
|
||||||
|
def_bool y
|
||||||
|
depends on $(cc-option,-mno-branch-likely)
|
||||||
|
|
||||||
menu "Power management options"
|
menu "Power management options"
|
||||||
|
|
||||||
config ARCH_HIBERNATION_POSSIBLE
|
config ARCH_HIBERNATION_POSSIBLE
|
||||||
|
|||||||
@ -158,7 +158,6 @@ cflags-y += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
|
|||||||
# CPU-dependent compiler/assembler options for optimization.
|
# CPU-dependent compiler/assembler options for optimization.
|
||||||
#
|
#
|
||||||
cflags-$(CONFIG_CPU_R3000) += -march=r3000
|
cflags-$(CONFIG_CPU_R3000) += -march=r3000
|
||||||
cflags-$(CONFIG_CPU_TX39XX) += -march=r3900
|
|
||||||
cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
|
cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
|
||||||
cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
|
cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
|
||||||
cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
|
cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
|
||||||
@ -340,14 +339,12 @@ drivers-$(CONFIG_PM) += arch/mips/power/
|
|||||||
boot-y := vmlinux.bin
|
boot-y := vmlinux.bin
|
||||||
boot-y += vmlinux.ecoff
|
boot-y += vmlinux.ecoff
|
||||||
boot-y += vmlinux.srec
|
boot-y += vmlinux.srec
|
||||||
ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0)
|
|
||||||
boot-y += uImage
|
boot-y += uImage
|
||||||
boot-y += uImage.bin
|
boot-y += uImage.bin
|
||||||
boot-y += uImage.bz2
|
boot-y += uImage.bz2
|
||||||
boot-y += uImage.gz
|
boot-y += uImage.gz
|
||||||
boot-y += uImage.lzma
|
boot-y += uImage.lzma
|
||||||
boot-y += uImage.lzo
|
boot-y += uImage.lzo
|
||||||
endif
|
|
||||||
boot-y += vmlinux.itb
|
boot-y += vmlinux.itb
|
||||||
boot-y += vmlinux.gz.itb
|
boot-y += vmlinux.gz.itb
|
||||||
boot-y += vmlinux.bz2.itb
|
boot-y += vmlinux.bz2.itb
|
||||||
@ -359,9 +356,7 @@ bootz-y := vmlinuz
|
|||||||
bootz-y += vmlinuz.bin
|
bootz-y += vmlinuz.bin
|
||||||
bootz-y += vmlinuz.ecoff
|
bootz-y += vmlinuz.ecoff
|
||||||
bootz-y += vmlinuz.srec
|
bootz-y += vmlinuz.srec
|
||||||
ifeq ($(shell expr $(zload-y) \< 0xffffffff80000000 2> /dev/null), 0)
|
|
||||||
bootz-y += uzImage.bin
|
bootz-y += uzImage.bin
|
||||||
endif
|
|
||||||
bootz-y += vmlinuz.itb
|
bootz-y += vmlinuz.itb
|
||||||
|
|
||||||
#
|
#
|
||||||
|
|||||||
@ -112,7 +112,7 @@ static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
|
static const struct irq_domain_ops ar2315_misc_irq_domain_ops = {
|
||||||
.map = ar2315_misc_irq_map,
|
.map = ar2315_misc_irq_map,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -116,7 +116,7 @@ static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
|
static const struct irq_domain_ops ar5312_misc_irq_domain_ops = {
|
||||||
.map = ar5312_misc_irq_map,
|
.map = ar5312_misc_irq_map,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -121,6 +121,7 @@ static void prom_putchar_init(void)
|
|||||||
case REV_ID_MAJOR_QCA9558:
|
case REV_ID_MAJOR_QCA9558:
|
||||||
case REV_ID_MAJOR_TP9343:
|
case REV_ID_MAJOR_TP9343:
|
||||||
case REV_ID_MAJOR_QCA956X:
|
case REV_ID_MAJOR_QCA956X:
|
||||||
|
case REV_ID_MAJOR_QCN550X:
|
||||||
_prom_putchar = prom_putchar_ar71xx;
|
_prom_putchar = prom_putchar_ar71xx;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
|||||||
@ -168,6 +168,12 @@ static void __init ath79_detect_sys_type(void)
|
|||||||
rev = id & QCA956X_REV_ID_REVISION_MASK;
|
rev = id & QCA956X_REV_ID_REVISION_MASK;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
case REV_ID_MAJOR_QCN550X:
|
||||||
|
ath79_soc = ATH79_SOC_QCA956X;
|
||||||
|
chip = "550X";
|
||||||
|
rev = id & QCA956X_REV_ID_REVISION_MASK;
|
||||||
|
break;
|
||||||
|
|
||||||
case REV_ID_MAJOR_TP9343:
|
case REV_ID_MAJOR_TP9343:
|
||||||
ath79_soc = ATH79_SOC_TP9343;
|
ath79_soc = ATH79_SOC_TP9343;
|
||||||
chip = "9343";
|
chip = "9343";
|
||||||
@ -263,8 +269,3 @@ void __init arch_init_irq(void)
|
|||||||
{
|
{
|
||||||
irqchip_init();
|
irqchip_init();
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init device_tree_init(void)
|
|
||||||
{
|
|
||||||
unflatten_and_copy_device_tree();
|
|
||||||
}
|
|
||||||
|
|||||||
@ -38,6 +38,7 @@ KBUILD_AFLAGS := $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
|
|||||||
KCOV_INSTRUMENT := n
|
KCOV_INSTRUMENT := n
|
||||||
GCOV_PROFILE := n
|
GCOV_PROFILE := n
|
||||||
UBSAN_SANITIZE := n
|
UBSAN_SANITIZE := n
|
||||||
|
KCSAN_SANITIZE := n
|
||||||
|
|
||||||
# decompressor objects (linked with vmlinuz)
|
# decompressor objects (linked with vmlinuz)
|
||||||
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/bswapsi.o
|
vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/bswapsi.o
|
||||||
|
|||||||
@ -26,7 +26,7 @@ unsigned long free_mem_ptr;
|
|||||||
unsigned long free_mem_end_ptr;
|
unsigned long free_mem_end_ptr;
|
||||||
|
|
||||||
/* The linker tells us where the image is. */
|
/* The linker tells us where the image is. */
|
||||||
extern unsigned char __image_begin, __image_end;
|
extern unsigned char __image_begin[], __image_end[];
|
||||||
|
|
||||||
/* debug interfaces */
|
/* debug interfaces */
|
||||||
#ifdef CONFIG_DEBUG_ZBOOT
|
#ifdef CONFIG_DEBUG_ZBOOT
|
||||||
@ -91,9 +91,9 @@ void decompress_kernel(unsigned long boot_heap_start)
|
|||||||
{
|
{
|
||||||
unsigned long zimage_start, zimage_size;
|
unsigned long zimage_start, zimage_size;
|
||||||
|
|
||||||
zimage_start = (unsigned long)(&__image_begin);
|
zimage_start = (unsigned long)(__image_begin);
|
||||||
zimage_size = (unsigned long)(&__image_end) -
|
zimage_size = (unsigned long)(__image_end) -
|
||||||
(unsigned long)(&__image_begin);
|
(unsigned long)(__image_begin);
|
||||||
|
|
||||||
puts("zimage at: ");
|
puts("zimage at: ");
|
||||||
puthex(zimage_start);
|
puthex(zimage_start);
|
||||||
@ -121,7 +121,7 @@ void decompress_kernel(unsigned long boot_heap_start)
|
|||||||
dtb_size = fdt_totalsize((void *)&__appended_dtb);
|
dtb_size = fdt_totalsize((void *)&__appended_dtb);
|
||||||
|
|
||||||
/* last four bytes is always image size in little endian */
|
/* last four bytes is always image size in little endian */
|
||||||
image_size = get_unaligned_le32((void *)&__image_end - 4);
|
image_size = get_unaligned_le32((void *)__image_end - 4);
|
||||||
|
|
||||||
/* The device tree's address must be properly aligned */
|
/* The device tree's address must be properly aligned */
|
||||||
image_size = ALIGN(image_size, STRUCT_ALIGNMENT);
|
image_size = ALIGN(image_size, STRUCT_ALIGNMENT);
|
||||||
|
|||||||
@ -510,7 +510,7 @@
|
|||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
|
|
||||||
eth0_addr: eth-mac-addr@0x22 {
|
eth0_addr: eth-mac-addr@22 {
|
||||||
reg = <0x22 0x6>;
|
reg = <0x22 0x6>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|||||||
@ -1274,13 +1274,13 @@ static int octeon_irq_gpio_map(struct irq_domain *d,
|
|||||||
return r;
|
return r;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_domain_ops octeon_irq_domain_ciu_ops = {
|
static const struct irq_domain_ops octeon_irq_domain_ciu_ops = {
|
||||||
.map = octeon_irq_ciu_map,
|
.map = octeon_irq_ciu_map,
|
||||||
.unmap = octeon_irq_free_cd,
|
.unmap = octeon_irq_free_cd,
|
||||||
.xlate = octeon_irq_ciu_xlat,
|
.xlate = octeon_irq_ciu_xlat,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
|
static const struct irq_domain_ops octeon_irq_domain_gpio_ops = {
|
||||||
.map = octeon_irq_gpio_map,
|
.map = octeon_irq_gpio_map,
|
||||||
.unmap = octeon_irq_free_cd,
|
.unmap = octeon_irq_free_cd,
|
||||||
.xlate = octeon_irq_gpio_xlat,
|
.xlate = octeon_irq_gpio_xlat,
|
||||||
@ -1974,7 +1974,7 @@ static int octeon_irq_ciu2_map(struct irq_domain *d,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_domain_ops octeon_irq_domain_ciu2_ops = {
|
static const struct irq_domain_ops octeon_irq_domain_ciu2_ops = {
|
||||||
.map = octeon_irq_ciu2_map,
|
.map = octeon_irq_ciu2_map,
|
||||||
.unmap = octeon_irq_free_cd,
|
.unmap = octeon_irq_free_cd,
|
||||||
.xlate = octeon_irq_ciu2_xlat,
|
.xlate = octeon_irq_ciu2_xlat,
|
||||||
@ -2226,7 +2226,7 @@ static int octeon_irq_cib_map(struct irq_domain *d,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_domain_ops octeon_irq_domain_cib_ops = {
|
static const struct irq_domain_ops octeon_irq_domain_cib_ops = {
|
||||||
.map = octeon_irq_cib_map,
|
.map = octeon_irq_cib_map,
|
||||||
.unmap = octeon_irq_free_cd,
|
.unmap = octeon_irq_free_cd,
|
||||||
.xlate = octeon_irq_cib_xlat,
|
.xlate = octeon_irq_cib_xlat,
|
||||||
@ -2578,7 +2578,7 @@ static int octeon_irq_ciu3_map(struct irq_domain *d,
|
|||||||
return octeon_irq_ciu3_mapx(d, virq, hw, &octeon_irq_chip_ciu3);
|
return octeon_irq_ciu3_mapx(d, virq, hw, &octeon_irq_chip_ciu3);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_domain_ops octeon_dflt_domain_ciu3_ops = {
|
static const struct irq_domain_ops octeon_dflt_domain_ciu3_ops = {
|
||||||
.map = octeon_irq_ciu3_map,
|
.map = octeon_irq_ciu3_map,
|
||||||
.unmap = octeon_irq_free_cd,
|
.unmap = octeon_irq_free_cd,
|
||||||
.xlate = octeon_irq_ciu3_xlat,
|
.xlate = octeon_irq_ciu3_xlat,
|
||||||
|
|||||||
@ -1,50 +0,0 @@
|
|||||||
CONFIG_SYSVIPC=y
|
|
||||||
CONFIG_LOG_BUF_SHIFT=14
|
|
||||||
CONFIG_EXPERT=y
|
|
||||||
CONFIG_SLAB=y
|
|
||||||
CONFIG_MACH_TX39XX=y
|
|
||||||
CONFIG_TOSHIBA_JMR3927=y
|
|
||||||
# CONFIG_SECCOMP is not set
|
|
||||||
CONFIG_PCI=y
|
|
||||||
CONFIG_NET=y
|
|
||||||
CONFIG_PACKET=y
|
|
||||||
CONFIG_UNIX=y
|
|
||||||
CONFIG_INET=y
|
|
||||||
CONFIG_IP_PNP=y
|
|
||||||
CONFIG_IP_PNP_BOOTP=y
|
|
||||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
|
||||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
|
||||||
# CONFIG_INET_DIAG is not set
|
|
||||||
# CONFIG_IPV6 is not set
|
|
||||||
CONFIG_MTD=y
|
|
||||||
CONFIG_MTD_CMDLINE_PARTS=y
|
|
||||||
CONFIG_MTD_CFI=y
|
|
||||||
CONFIG_MTD_JEDECPROBE=y
|
|
||||||
CONFIG_MTD_CFI_AMDSTD=y
|
|
||||||
CONFIG_MTD_PHYSMAP=y
|
|
||||||
CONFIG_NETDEVICES=y
|
|
||||||
CONFIG_TC35815=y
|
|
||||||
# CONFIG_INPUT is not set
|
|
||||||
# CONFIG_SERIO is not set
|
|
||||||
# CONFIG_VT is not set
|
|
||||||
# CONFIG_UNIX98_PTYS is not set
|
|
||||||
CONFIG_SERIAL_NONSTANDARD=y
|
|
||||||
CONFIG_SERIAL_TXX9_CONSOLE=y
|
|
||||||
CONFIG_SERIAL_TXX9_STDSERIAL=y
|
|
||||||
# CONFIG_HW_RANDOM is not set
|
|
||||||
# CONFIG_HWMON is not set
|
|
||||||
CONFIG_WATCHDOG=y
|
|
||||||
CONFIG_TXX9_WDT=y
|
|
||||||
# CONFIG_USB_SUPPORT is not set
|
|
||||||
CONFIG_NEW_LEDS=y
|
|
||||||
CONFIG_LEDS_CLASS=y
|
|
||||||
CONFIG_LEDS_GPIO=y
|
|
||||||
CONFIG_LEDS_TRIGGERS=y
|
|
||||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
|
||||||
CONFIG_RTC_CLASS=y
|
|
||||||
CONFIG_RTC_DRV_DS1742=y
|
|
||||||
CONFIG_PROC_KCORE=y
|
|
||||||
# CONFIG_MISC_FILESYSTEMS is not set
|
|
||||||
CONFIG_NFS_FS=y
|
|
||||||
CONFIG_ROOT_NFS=y
|
|
||||||
@ -4,6 +4,7 @@ CONFIG_HIGH_RES_TIMERS=y
|
|||||||
CONFIG_LOG_BUF_SHIFT=15
|
CONFIG_LOG_BUF_SHIFT=15
|
||||||
CONFIG_NAMESPACES=y
|
CONFIG_NAMESPACES=y
|
||||||
CONFIG_RELAY=y
|
CONFIG_RELAY=y
|
||||||
|
CONFIG_BLK_DEV_INITRD=y
|
||||||
CONFIG_EXPERT=y
|
CONFIG_EXPERT=y
|
||||||
# CONFIG_COMPAT_BRK is not set
|
# CONFIG_COMPAT_BRK is not set
|
||||||
CONFIG_SLAB=y
|
CONFIG_SLAB=y
|
||||||
|
|||||||
@ -131,7 +131,7 @@
|
|||||||
*/
|
*/
|
||||||
mfc0 t0,CP0_CAUSE # get pending interrupts
|
mfc0 t0,CP0_CAUSE # get pending interrupts
|
||||||
mfc0 t1,CP0_STATUS
|
mfc0 t1,CP0_STATUS
|
||||||
#ifdef CONFIG_32BIT
|
#if defined(CONFIG_32BIT) && defined(CONFIG_MIPS_FP_SUPPORT)
|
||||||
lw t2,cpu_fpu_mask
|
lw t2,cpu_fpu_mask
|
||||||
#endif
|
#endif
|
||||||
andi t0,ST0_IM # CAUSE.CE may be non-zero!
|
andi t0,ST0_IM # CAUSE.CE may be non-zero!
|
||||||
@ -139,7 +139,7 @@
|
|||||||
|
|
||||||
beqz t0,spurious
|
beqz t0,spurious
|
||||||
|
|
||||||
#ifdef CONFIG_32BIT
|
#if defined(CONFIG_32BIT) && defined(CONFIG_MIPS_FP_SUPPORT)
|
||||||
and t2,t0
|
and t2,t0
|
||||||
bnez t2,fpu # handle FPU immediately
|
bnez t2,fpu # handle FPU immediately
|
||||||
#endif
|
#endif
|
||||||
@ -280,7 +280,7 @@ handle_it:
|
|||||||
j dec_irq_dispatch
|
j dec_irq_dispatch
|
||||||
nop
|
nop
|
||||||
|
|
||||||
#ifdef CONFIG_32BIT
|
#if defined(CONFIG_32BIT) && defined(CONFIG_MIPS_FP_SUPPORT)
|
||||||
fpu:
|
fpu:
|
||||||
lw t0,fpu_kstat_irq
|
lw t0,fpu_kstat_irq
|
||||||
nop
|
nop
|
||||||
|
|||||||
@ -6,4 +6,4 @@
|
|||||||
|
|
||||||
lib-y += init.o memory.o cmdline.o identify.o console.o
|
lib-y += init.o memory.o cmdline.o identify.o console.o
|
||||||
|
|
||||||
lib-$(CONFIG_32BIT) += locore.o
|
lib-$(CONFIG_CPU_R3000) += locore.o
|
||||||
|
|||||||
@ -746,7 +746,8 @@ void __init arch_init_irq(void)
|
|||||||
dec_interrupt[DEC_IRQ_HALT] = -1;
|
dec_interrupt[DEC_IRQ_HALT] = -1;
|
||||||
|
|
||||||
/* Register board interrupts: FPU and cascade. */
|
/* Register board interrupts: FPU and cascade. */
|
||||||
if (dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) {
|
if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT) &&
|
||||||
|
dec_interrupt[DEC_IRQ_FPU] >= 0 && cpu_has_fpu) {
|
||||||
struct irq_desc *desc_fpu;
|
struct irq_desc *desc_fpu;
|
||||||
int irq_fpu;
|
int irq_fpu;
|
||||||
|
|
||||||
|
|||||||
@ -120,9 +120,6 @@
|
|||||||
#ifndef cpu_has_4k_cache
|
#ifndef cpu_has_4k_cache
|
||||||
#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
|
#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
|
||||||
#endif
|
#endif
|
||||||
#ifndef cpu_has_tx39_cache
|
|
||||||
#define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE)
|
|
||||||
#endif
|
|
||||||
#ifndef cpu_has_octeon_cache
|
#ifndef cpu_has_octeon_cache
|
||||||
#define cpu_has_octeon_cache 0
|
#define cpu_has_octeon_cache 0
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -105,12 +105,6 @@ static inline int __pure __get_cpu_type(const int cpu_type)
|
|||||||
case CPU_R3081E:
|
case CPU_R3081E:
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_HAS_CPU_TX39XX
|
|
||||||
case CPU_TX3912:
|
|
||||||
case CPU_TX3922:
|
|
||||||
case CPU_TX3927:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_HAS_CPU_VR41XX
|
#ifdef CONFIG_SYS_HAS_CPU_VR41XX
|
||||||
case CPU_VR41XX:
|
case CPU_VR41XX:
|
||||||
case CPU_VR4111:
|
case CPU_VR4111:
|
||||||
|
|||||||
@ -309,11 +309,6 @@ enum cpu_type_enum {
|
|||||||
CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
|
CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
|
||||||
CPU_SR71000, CPU_TX49XX,
|
CPU_SR71000, CPU_TX49XX,
|
||||||
|
|
||||||
/*
|
|
||||||
* TX3900 class processors
|
|
||||||
*/
|
|
||||||
CPU_TX3912, CPU_TX3922, CPU_TX3927,
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* MIPS32 class processors
|
* MIPS32 class processors
|
||||||
*/
|
*/
|
||||||
@ -367,7 +362,6 @@ enum cpu_type_enum {
|
|||||||
#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
|
#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
|
||||||
#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
|
#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
|
||||||
#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
|
#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
|
||||||
#define MIPS_CPU_TX39_CACHE BIT_ULL( 4) /* TX3900-style caches */
|
|
||||||
#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
|
#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
|
||||||
#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
|
#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
|
||||||
#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
|
#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
|
||||||
|
|||||||
@ -43,16 +43,11 @@
|
|||||||
*/
|
*/
|
||||||
#define REX_PROM_MAGIC 0x30464354
|
#define REX_PROM_MAGIC 0x30464354
|
||||||
|
|
||||||
#ifdef CONFIG_64BIT
|
/* KN04 and KN05 are REX PROMs, so only do the check for R3k systems. */
|
||||||
|
static inline bool prom_is_rex(u32 magic)
|
||||||
#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */
|
{
|
||||||
|
return !IS_ENABLED(CONFIG_CPU_R3000) || magic == REX_PROM_MAGIC;
|
||||||
#else /* !CONFIG_64BIT */
|
}
|
||||||
|
|
||||||
#define prom_is_rex(magic) ((magic) == REX_PROM_MAGIC)
|
|
||||||
|
|
||||||
#endif /* !CONFIG_64BIT */
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
|
* 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
|
||||||
|
|||||||
@ -17,7 +17,6 @@
|
|||||||
#include <asm/compiler.h>
|
#include <asm/compiler.h>
|
||||||
#include <asm/errno.h>
|
#include <asm/errno.h>
|
||||||
#include <asm/sync.h>
|
#include <asm/sync.h>
|
||||||
#include <asm/war.h>
|
|
||||||
|
|
||||||
#define arch_futex_atomic_op_inuser arch_futex_atomic_op_inuser
|
#define arch_futex_atomic_op_inuser arch_futex_atomic_op_inuser
|
||||||
#define futex_atomic_cmpxchg_inatomic futex_atomic_cmpxchg_inatomic
|
#define futex_atomic_cmpxchg_inatomic futex_atomic_cmpxchg_inatomic
|
||||||
|
|||||||
@ -10,7 +10,7 @@
|
|||||||
#ifndef __ASM_ISADEP_H
|
#ifndef __ASM_ISADEP_H
|
||||||
#define __ASM_ISADEP_H
|
#define __ASM_ISADEP_H
|
||||||
|
|
||||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
#if defined(CONFIG_CPU_R3000)
|
||||||
/*
|
/*
|
||||||
* R2000 or R3000
|
* R2000 or R3000
|
||||||
*/
|
*/
|
||||||
|
|||||||
@ -18,7 +18,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_sb1_cache 0
|
#define cpu_has_sb1_cache 0
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
|
|||||||
@ -862,6 +862,7 @@
|
|||||||
#define REV_ID_MAJOR_QCA9558 0x1130
|
#define REV_ID_MAJOR_QCA9558 0x1130
|
||||||
#define REV_ID_MAJOR_TP9343 0x0150
|
#define REV_ID_MAJOR_TP9343 0x0150
|
||||||
#define REV_ID_MAJOR_QCA956X 0x1150
|
#define REV_ID_MAJOR_QCA956X 0x1150
|
||||||
|
#define REV_ID_MAJOR_QCN550X 0x2170
|
||||||
|
|
||||||
#define AR71XX_REV_ID_MINOR_MASK 0x3
|
#define AR71XX_REV_ID_MINOR_MASK 0x3
|
||||||
#define AR71XX_REV_ID_MINOR_AR7130 0x0
|
#define AR71XX_REV_ID_MINOR_AR7130 0x0
|
||||||
|
|||||||
@ -16,7 +16,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_sb1_cache 0
|
#define cpu_has_sb1_cache 0
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
|
|||||||
@ -21,7 +21,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
#define cpu_has_counter 1
|
#define cpu_has_counter 1
|
||||||
|
|||||||
@ -6,7 +6,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
#define cpu_has_counter 1
|
#define cpu_has_counter 1
|
||||||
|
|||||||
@ -21,7 +21,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 0
|
#define cpu_has_4k_cache 0
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_counter 1
|
#define cpu_has_counter 1
|
||||||
#define cpu_has_watch 1
|
#define cpu_has_watch 1
|
||||||
#define cpu_has_divec 1
|
#define cpu_has_divec 1
|
||||||
|
|||||||
@ -13,7 +13,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_32fpr 1
|
#define cpu_has_32fpr 1
|
||||||
#define cpu_has_counter 1
|
#define cpu_has_counter 1
|
||||||
#define cpu_has_watch 0
|
#define cpu_has_watch 0
|
||||||
|
|||||||
@ -17,7 +17,6 @@
|
|||||||
#define cpu_has_rixiex 0
|
#define cpu_has_rixiex 0
|
||||||
#define cpu_has_maar 0
|
#define cpu_has_maar 0
|
||||||
#define cpu_has_rw_llb 0
|
#define cpu_has_rw_llb 0
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_divec 0
|
#define cpu_has_divec 0
|
||||||
#define cpu_has_prefetch 0
|
#define cpu_has_prefetch 0
|
||||||
#define cpu_has_mcheck 0
|
#define cpu_has_mcheck 0
|
||||||
|
|||||||
@ -11,7 +11,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_counter 0
|
#define cpu_has_counter 0
|
||||||
#define cpu_has_watch 1
|
#define cpu_has_watch 1
|
||||||
#define cpu_has_divec 1
|
#define cpu_has_divec 1
|
||||||
|
|||||||
@ -25,7 +25,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_fpu 1
|
#define cpu_has_fpu 1
|
||||||
#define cpu_has_nofpuex 0
|
#define cpu_has_nofpuex 0
|
||||||
#define cpu_has_32fpr 1
|
#define cpu_has_32fpr 1
|
||||||
|
|||||||
@ -28,7 +28,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_fpu 1
|
#define cpu_has_fpu 1
|
||||||
#define cpu_has_nofpuex 0
|
#define cpu_has_nofpuex 0
|
||||||
#define cpu_has_32fpr 1
|
#define cpu_has_32fpr 1
|
||||||
|
|||||||
@ -15,7 +15,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_sb1_cache 0
|
#define cpu_has_sb1_cache 0
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
|
|||||||
@ -34,7 +34,6 @@
|
|||||||
#define cpu_has_mipsmt 0
|
#define cpu_has_mipsmt 0
|
||||||
#define cpu_has_smartmips 0
|
#define cpu_has_smartmips 0
|
||||||
#define cpu_has_tlb 1
|
#define cpu_has_tlb 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_vce 0
|
#define cpu_has_vce 0
|
||||||
#define cpu_has_veic 0
|
#define cpu_has_veic 0
|
||||||
#define cpu_has_vint 0
|
#define cpu_has_vint 0
|
||||||
|
|||||||
@ -36,7 +36,6 @@
|
|||||||
#define cpu_has_mipsmt 0
|
#define cpu_has_mipsmt 0
|
||||||
#define cpu_has_smartmips 0
|
#define cpu_has_smartmips 0
|
||||||
#define cpu_has_tlb 1
|
#define cpu_has_tlb 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_vce 0
|
#define cpu_has_vce 0
|
||||||
#define cpu_has_veic 0
|
#define cpu_has_veic 0
|
||||||
#define cpu_has_vint 0
|
#define cpu_has_vint 0
|
||||||
|
|||||||
@ -16,7 +16,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_sb1_cache 0
|
#define cpu_has_sb1_cache 0
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
|
|||||||
@ -17,7 +17,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_sb1_cache 0
|
#define cpu_has_sb1_cache 0
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
|
|||||||
@ -16,7 +16,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_sb1_cache 0
|
#define cpu_has_sb1_cache 0
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
|
|||||||
@ -16,7 +16,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_sb1_cache 0
|
#define cpu_has_sb1_cache 0
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
|
|||||||
@ -15,7 +15,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_sb1_cache 0
|
#define cpu_has_sb1_cache 0
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
|
|||||||
@ -18,7 +18,6 @@
|
|||||||
#define cpu_has_4kex 1
|
#define cpu_has_4kex 1
|
||||||
#define cpu_has_3k_cache 0
|
#define cpu_has_3k_cache 0
|
||||||
#define cpu_has_4k_cache 1
|
#define cpu_has_4k_cache 1
|
||||||
#define cpu_has_tx39_cache 0
|
|
||||||
#define cpu_has_sb1_cache 0
|
#define cpu_has_sb1_cache 0
|
||||||
#define cpu_has_fpu 0
|
#define cpu_has_fpu 0
|
||||||
#define cpu_has_32fpr 0
|
#define cpu_has_32fpr 0
|
||||||
|
|||||||
@ -1,25 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
|
||||||
/*
|
|
||||||
* include/asm-mips/mach-tx39xx/ioremap.h
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_MACH_TX39XX_IOREMAP_H
|
|
||||||
#define __ASM_MACH_TX39XX_IOREMAP_H
|
|
||||||
|
|
||||||
#include <linux/types.h>
|
|
||||||
|
|
||||||
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
|
|
||||||
unsigned long flags)
|
|
||||||
{
|
|
||||||
#define TXX9_DIRECTMAP_BASE 0xff000000ul
|
|
||||||
if (offset >= TXX9_DIRECTMAP_BASE &&
|
|
||||||
offset < TXX9_DIRECTMAP_BASE + 0xff0000)
|
|
||||||
return (void __iomem *)offset;
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int plat_iounmap(const volatile void __iomem *addr)
|
|
||||||
{
|
|
||||||
return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* __ASM_MACH_TX39XX_IOREMAP_H */
|
|
||||||
@ -1,24 +0,0 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0 */
|
|
||||||
#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H
|
|
||||||
#define __ASM_MACH_TX39XX_MANGLE_PORT_H
|
|
||||||
|
|
||||||
#if defined(CONFIG_TOSHIBA_JMR3927)
|
|
||||||
extern unsigned long (*__swizzle_addr_b)(unsigned long port);
|
|
||||||
#define NEEDS_TXX9_SWIZZLE_ADDR_B
|
|
||||||
#else
|
|
||||||
#define __swizzle_addr_b(port) (port)
|
|
||||||
#endif
|
|
||||||
#define __swizzle_addr_w(port) (port)
|
|
||||||
#define __swizzle_addr_l(port) (port)
|
|
||||||
#define __swizzle_addr_q(port) (port)
|
|
||||||
|
|
||||||
#define ioswabb(a, x) (x)
|
|
||||||
#define __mem_ioswabb(a, x) (x)
|
|
||||||
#define ioswabw(a, x) le16_to_cpu((__force __le16)(x))
|
|
||||||
#define __mem_ioswabw(a, x) (x)
|
|
||||||
#define ioswabl(a, x) le32_to_cpu((__force __le32)(x))
|
|
||||||
#define __mem_ioswabl(a, x) (x)
|
|
||||||
#define ioswabq(a, x) le64_to_cpu((__force __le64)(x))
|
|
||||||
#define __mem_ioswabq(a, x) (x)
|
|
||||||
|
|
||||||
#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
|
|
||||||
@ -1,17 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is subject to the terms and conditions of the GNU General Public
|
|
||||||
* License. See the file "COPYING" in the main directory of this archive
|
|
||||||
* for more details.
|
|
||||||
*
|
|
||||||
* Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
|
|
||||||
* Copyright (C) 2000, 2002 Maciej W. Rozycki
|
|
||||||
* Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
|
|
||||||
*/
|
|
||||||
#ifndef _ASM_TX39XX_SPACES_H
|
|
||||||
#define _ASM_TX39XX_SPACES_H
|
|
||||||
|
|
||||||
#define FIXADDR_TOP ((unsigned long)(long)(int)0xfefe0000)
|
|
||||||
|
|
||||||
#include <asm/mach-generic/spaces.h>
|
|
||||||
|
|
||||||
#endif /* __ASM_TX39XX_SPACES_H */
|
|
||||||
@ -9,7 +9,6 @@
|
|||||||
#define _ASM_MIPSMTREGS_H
|
#define _ASM_MIPSMTREGS_H
|
||||||
|
|
||||||
#include <asm/mipsregs.h>
|
#include <asm/mipsregs.h>
|
||||||
#include <asm/war.h>
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
|||||||
@ -17,7 +17,6 @@
|
|||||||
#include <linux/types.h>
|
#include <linux/types.h>
|
||||||
#include <asm/hazards.h>
|
#include <asm/hazards.h>
|
||||||
#include <asm/isa-rev.h>
|
#include <asm/isa-rev.h>
|
||||||
#include <asm/war.h>
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The following macros are especially useful for __asm__
|
* The following macros are especially useful for __asm__
|
||||||
|
|||||||
@ -15,6 +15,7 @@
|
|||||||
|
|
||||||
#define __HAVE_ARCH_PMD_ALLOC_ONE
|
#define __HAVE_ARCH_PMD_ALLOC_ONE
|
||||||
#define __HAVE_ARCH_PUD_ALLOC_ONE
|
#define __HAVE_ARCH_PUD_ALLOC_ONE
|
||||||
|
#define __HAVE_ARCH_PGD_FREE
|
||||||
#include <asm-generic/pgalloc.h>
|
#include <asm-generic/pgalloc.h>
|
||||||
|
|
||||||
static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
|
static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
|
||||||
@ -48,6 +49,11 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
|
|||||||
extern void pgd_init(unsigned long page);
|
extern void pgd_init(unsigned long page);
|
||||||
extern pgd_t *pgd_alloc(struct mm_struct *mm);
|
extern pgd_t *pgd_alloc(struct mm_struct *mm);
|
||||||
|
|
||||||
|
static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
|
||||||
|
{
|
||||||
|
free_pages((unsigned long)pgd, PGD_ORDER);
|
||||||
|
}
|
||||||
|
|
||||||
#define __pte_free_tlb(tlb,pte,address) \
|
#define __pte_free_tlb(tlb,pte,address) \
|
||||||
do { \
|
do { \
|
||||||
pgtable_pte_page_dtor(pte); \
|
pgtable_pte_page_dtor(pte); \
|
||||||
|
|||||||
@ -20,9 +20,9 @@ struct boot_param_header;
|
|||||||
extern void __dt_setup_arch(void *bph);
|
extern void __dt_setup_arch(void *bph);
|
||||||
extern int __dt_register_buses(const char *bus0, const char *bus1);
|
extern int __dt_register_buses(const char *bus0, const char *bus1);
|
||||||
|
|
||||||
#else /* CONFIG_OF */
|
#else /* !CONFIG_USE_OF */
|
||||||
static inline void device_tree_init(void) { }
|
static inline void device_tree_init(void) { }
|
||||||
#endif /* CONFIG_OF */
|
#endif /* !CONFIG_USE_OF */
|
||||||
|
|
||||||
extern char *mips_get_machine_name(void);
|
extern char *mips_get_machine_name(void);
|
||||||
extern void mips_set_machine_name(const char *name);
|
extern void mips_set_machine_name(const char *name);
|
||||||
|
|||||||
@ -16,7 +16,7 @@ static inline void setup_8250_early_printk_port(unsigned long base,
|
|||||||
unsigned int reg_shift, unsigned int timeout) {}
|
unsigned int reg_shift, unsigned int timeout) {}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
extern void set_handler(unsigned long offset, void *addr, unsigned long len);
|
void set_handler(unsigned long offset, const void *addr, unsigned long len);
|
||||||
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
|
extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
|
||||||
|
|
||||||
typedef void (*vi_handler_t)(void);
|
typedef void (*vi_handler_t)(void);
|
||||||
|
|||||||
@ -42,7 +42,7 @@
|
|||||||
cfi_restore \reg \offset \docfi
|
cfi_restore \reg \offset \docfi
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
#if defined(CONFIG_CPU_R3000)
|
||||||
#define STATMASK 0x3f
|
#define STATMASK 0x3f
|
||||||
#else
|
#else
|
||||||
#define STATMASK 0x1f
|
#define STATMASK 0x1f
|
||||||
@ -349,7 +349,7 @@
|
|||||||
cfi_ld sp, PT_R29, \docfi
|
cfi_ld sp, PT_R29, \docfi
|
||||||
.endm
|
.endm
|
||||||
|
|
||||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
#if defined(CONFIG_CPU_R3000)
|
||||||
|
|
||||||
.macro RESTORE_SOME docfi=0
|
.macro RESTORE_SOME docfi=0
|
||||||
.set push
|
.set push
|
||||||
@ -478,7 +478,7 @@
|
|||||||
.macro KMODE
|
.macro KMODE
|
||||||
mfc0 t0, CP0_STATUS
|
mfc0 t0, CP0_STATUS
|
||||||
li t1, ST0_KERNEL_CUMASK | (STATMASK & ~1)
|
li t1, ST0_KERNEL_CUMASK | (STATMASK & ~1)
|
||||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
#if defined(CONFIG_CPU_R3000)
|
||||||
andi t2, t0, ST0_IEP
|
andi t2, t0, ST0_IEP
|
||||||
srl t2, 2
|
srl t2, 2
|
||||||
or t0, t2
|
or t0, t2
|
||||||
|
|||||||
@ -69,6 +69,10 @@ static inline struct thread_info *current_thread_info(void)
|
|||||||
return __current_thread_info;
|
return __current_thread_info;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_ARCH_HAS_CURRENT_STACK_POINTER
|
||||||
|
register unsigned long current_stack_pointer __asm__("sp");
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* !__ASSEMBLY__ */
|
#endif /* !__ASSEMBLY__ */
|
||||||
|
|
||||||
/* thread information allocation */
|
/* thread information allocation */
|
||||||
|
|||||||
@ -1,7 +1,4 @@
|
|||||||
/* SPDX-License-Identifier: GPL-2.0 */
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
#ifdef CONFIG_TOSHIBA_JMR3927
|
|
||||||
BOARD_VEC(jmr3927_vec)
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_TOSHIBA_RBTX4927
|
#ifdef CONFIG_TOSHIBA_RBTX4927
|
||||||
BOARD_VEC(rbtx4927_vec)
|
BOARD_VEC(rbtx4927_vec)
|
||||||
BOARD_VEC(rbtx4937_vec)
|
BOARD_VEC(rbtx4937_vec)
|
||||||
|
|||||||
@ -1,179 +0,0 @@
|
|||||||
/*
|
|
||||||
* Defines for the TJSYS JMR-TX3927
|
|
||||||
*
|
|
||||||
* This file is subject to the terms and conditions of the GNU General Public
|
|
||||||
* License. See the file "COPYING" in the main directory of this archive
|
|
||||||
* for more details.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_TXX9_JMR3927_H
|
|
||||||
#define __ASM_TXX9_JMR3927_H
|
|
||||||
|
|
||||||
#include <asm/txx9/tx3927.h>
|
|
||||||
#include <asm/addrspace.h>
|
|
||||||
#include <asm/txx9irq.h>
|
|
||||||
|
|
||||||
/* CS */
|
|
||||||
#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
|
|
||||||
#define JMR3927_ROMCE1 0x1e000000 /* 4M */
|
|
||||||
#define JMR3927_ROMCE2 0x14000000 /* 16M */
|
|
||||||
#define JMR3927_ROMCE3 0x10000000 /* 64M */
|
|
||||||
#define JMR3927_ROMCE5 0x1d000000 /* 4M */
|
|
||||||
#define JMR3927_SDCS0 0x00000000 /* 32M */
|
|
||||||
#define JMR3927_SDCS1 0x02000000 /* 32M */
|
|
||||||
/* PCI Direct Mappings */
|
|
||||||
|
|
||||||
#define JMR3927_PCIMEM 0x08000000
|
|
||||||
#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
|
|
||||||
#define JMR3927_PCIIO 0x15000000
|
|
||||||
#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */
|
|
||||||
|
|
||||||
#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
|
|
||||||
#define JMR3927_PORT_BASE KSEG1
|
|
||||||
|
|
||||||
/* Address map (virtual address) */
|
|
||||||
#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
|
|
||||||
#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
|
|
||||||
#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
|
|
||||||
#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
|
|
||||||
#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
|
|
||||||
|
|
||||||
#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
|
|
||||||
#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
|
|
||||||
#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
|
|
||||||
#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
|
|
||||||
#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
|
|
||||||
#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000)
|
|
||||||
#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000)
|
|
||||||
#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000)
|
|
||||||
#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000)
|
|
||||||
#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
|
|
||||||
#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
|
|
||||||
|
|
||||||
/* Flash ROM */
|
|
||||||
#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
|
|
||||||
#define JMR3927_FLASH_SIZE 0x00400000
|
|
||||||
|
|
||||||
/* bits for IOC_REV/IOC_BREV (high byte) */
|
|
||||||
#define JMR3927_IDT_MASK 0xfc
|
|
||||||
#define JMR3927_REV_MASK 0x03
|
|
||||||
#define JMR3927_IOC_IDT 0xe0
|
|
||||||
|
|
||||||
/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
|
|
||||||
#define JMR3927_IOC_INTB_PCIA 0
|
|
||||||
#define JMR3927_IOC_INTB_PCIB 1
|
|
||||||
#define JMR3927_IOC_INTB_PCIC 2
|
|
||||||
#define JMR3927_IOC_INTB_PCID 3
|
|
||||||
#define JMR3927_IOC_INTB_MODEM 4
|
|
||||||
#define JMR3927_IOC_INTB_INT6 5
|
|
||||||
#define JMR3927_IOC_INTB_INT7 6
|
|
||||||
#define JMR3927_IOC_INTB_SOFT 7
|
|
||||||
#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA)
|
|
||||||
#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB)
|
|
||||||
#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC)
|
|
||||||
#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID)
|
|
||||||
#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM)
|
|
||||||
#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6)
|
|
||||||
#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7)
|
|
||||||
#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT)
|
|
||||||
|
|
||||||
/* bits for IOC_RESET (high byte) */
|
|
||||||
#define JMR3927_IOC_RESET_CPU 1
|
|
||||||
#define JMR3927_IOC_RESET_PCI 2
|
|
||||||
|
|
||||||
#if defined(__BIG_ENDIAN)
|
|
||||||
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
|
|
||||||
#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
|
|
||||||
#elif defined(__LITTLE_ENDIAN)
|
|
||||||
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d))
|
|
||||||
#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1))
|
|
||||||
#else
|
|
||||||
#error "No Endian"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* LED macro */
|
|
||||||
#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
|
|
||||||
|
|
||||||
#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
|
|
||||||
|
|
||||||
/* DIPSW4 macro */
|
|
||||||
#define jmr3927_dipsw1() (gpio_get_value(11) == 0)
|
|
||||||
#define jmr3927_dipsw2() (gpio_get_value(10) == 0)
|
|
||||||
#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
|
|
||||||
#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IRQ mappings
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* These are the virtual IRQ numbers, we divide all IRQ's into
|
|
||||||
* 'spaces', the 'space' determines where and how to enable/disable
|
|
||||||
* that particular IRQ on an JMR machine. Add new 'spaces' as new
|
|
||||||
* IRQ hardware is supported.
|
|
||||||
*/
|
|
||||||
#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
|
|
||||||
#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
|
|
||||||
|
|
||||||
#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
|
|
||||||
#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
|
|
||||||
#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
|
|
||||||
|
|
||||||
#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
|
|
||||||
#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
|
|
||||||
#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2)
|
|
||||||
#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3)
|
|
||||||
#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4)
|
|
||||||
#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
|
|
||||||
#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
|
|
||||||
#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
|
|
||||||
#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
|
|
||||||
#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
|
|
||||||
#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
|
|
||||||
#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
|
|
||||||
#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
|
|
||||||
#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
|
|
||||||
#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
|
|
||||||
#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
|
|
||||||
#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
|
|
||||||
#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
|
|
||||||
#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
|
|
||||||
#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
|
|
||||||
#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
|
|
||||||
|
|
||||||
/* IOC (PCI, MODEM) */
|
|
||||||
#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
|
|
||||||
/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
|
|
||||||
#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
|
|
||||||
|
|
||||||
/* Clocks */
|
|
||||||
#define JMR3927_CORECLK 132710400 /* 132.7MHz */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* TX3927 Pin Configuration:
|
|
||||||
*
|
|
||||||
* PCFG bits Avail Dead
|
|
||||||
* SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3]
|
|
||||||
* SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4]
|
|
||||||
* SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF,
|
|
||||||
* GDBGE* PIO[2:1]
|
|
||||||
* SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12]
|
|
||||||
* SELTMR[2:0]:000 TIMER[1:0]
|
|
||||||
* SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6],
|
|
||||||
* DMAREQ[1],DMAACK[1]
|
|
||||||
* SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8]
|
|
||||||
* SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14]
|
|
||||||
* SELDONE:1 DMADONE PIO[7]
|
|
||||||
*
|
|
||||||
* Usable pins are:
|
|
||||||
* RXD[1;0],TXD[1:0],CTS[0],RTS[0],
|
|
||||||
* DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
|
|
||||||
* INT[3:0]
|
|
||||||
*/
|
|
||||||
|
|
||||||
void jmr3927_prom_init(void);
|
|
||||||
void jmr3927_irq_setup(void);
|
|
||||||
struct pci_dev;
|
|
||||||
int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
|
|
||||||
|
|
||||||
#endif /* __ASM_TXX9_JMR3927_H */
|
|
||||||
@ -1,341 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is subject to the terms and conditions of the GNU General Public
|
|
||||||
* License. See the file "COPYING" in the main directory of this archive
|
|
||||||
* for more details.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2000 Toshiba Corporation
|
|
||||||
*/
|
|
||||||
#ifndef __ASM_TXX9_TX3927_H
|
|
||||||
#define __ASM_TXX9_TX3927_H
|
|
||||||
|
|
||||||
#define TX3927_REG_BASE 0xfffe0000UL
|
|
||||||
#define TX3927_REG_SIZE 0x00010000
|
|
||||||
#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
|
|
||||||
#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
|
|
||||||
#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
|
|
||||||
#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000)
|
|
||||||
#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000)
|
|
||||||
#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000)
|
|
||||||
#define TX3927_NR_TMR 3
|
|
||||||
#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
|
|
||||||
#define TX3927_NR_SIO 2
|
|
||||||
#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
|
|
||||||
#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500)
|
|
||||||
|
|
||||||
struct tx3927_sdramc_reg {
|
|
||||||
volatile unsigned long cr[8];
|
|
||||||
volatile unsigned long tr[3];
|
|
||||||
volatile unsigned long cmd;
|
|
||||||
volatile unsigned long smrs[2];
|
|
||||||
};
|
|
||||||
|
|
||||||
struct tx3927_romc_reg {
|
|
||||||
volatile unsigned long cr[8];
|
|
||||||
};
|
|
||||||
|
|
||||||
struct tx3927_dma_reg {
|
|
||||||
struct tx3927_dma_ch_reg {
|
|
||||||
volatile unsigned long cha;
|
|
||||||
volatile unsigned long sar;
|
|
||||||
volatile unsigned long dar;
|
|
||||||
volatile unsigned long cntr;
|
|
||||||
volatile unsigned long sair;
|
|
||||||
volatile unsigned long dair;
|
|
||||||
volatile unsigned long ccr;
|
|
||||||
volatile unsigned long csr;
|
|
||||||
} ch[4];
|
|
||||||
volatile unsigned long dbr[8];
|
|
||||||
volatile unsigned long tdhr;
|
|
||||||
volatile unsigned long mcr;
|
|
||||||
volatile unsigned long unused0;
|
|
||||||
};
|
|
||||||
|
|
||||||
#include <asm/byteorder.h>
|
|
||||||
|
|
||||||
#ifdef __BIG_ENDIAN
|
|
||||||
#define endian_def_s2(e1, e2) \
|
|
||||||
volatile unsigned short e1, e2
|
|
||||||
#define endian_def_sb2(e1, e2, e3) \
|
|
||||||
volatile unsigned short e1;volatile unsigned char e2, e3
|
|
||||||
#define endian_def_b2s(e1, e2, e3) \
|
|
||||||
volatile unsigned char e1, e2;volatile unsigned short e3
|
|
||||||
#define endian_def_b4(e1, e2, e3, e4) \
|
|
||||||
volatile unsigned char e1, e2, e3, e4
|
|
||||||
#else
|
|
||||||
#define endian_def_s2(e1, e2) \
|
|
||||||
volatile unsigned short e2, e1
|
|
||||||
#define endian_def_sb2(e1, e2, e3) \
|
|
||||||
volatile unsigned char e3, e2;volatile unsigned short e1
|
|
||||||
#define endian_def_b2s(e1, e2, e3) \
|
|
||||||
volatile unsigned short e3;volatile unsigned char e2, e1
|
|
||||||
#define endian_def_b4(e1, e2, e3, e4) \
|
|
||||||
volatile unsigned char e4, e3, e2, e1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
struct tx3927_pcic_reg {
|
|
||||||
endian_def_s2(did, vid);
|
|
||||||
endian_def_s2(pcistat, pcicmd);
|
|
||||||
endian_def_b4(cc, scc, rpli, rid);
|
|
||||||
endian_def_b4(unused0, ht, mlt, cls);
|
|
||||||
volatile unsigned long ioba; /* +10 */
|
|
||||||
volatile unsigned long mba;
|
|
||||||
volatile unsigned long unused1[5];
|
|
||||||
endian_def_s2(svid, ssvid);
|
|
||||||
volatile unsigned long unused2; /* +30 */
|
|
||||||
endian_def_sb2(unused3, unused4, capptr);
|
|
||||||
volatile unsigned long unused5;
|
|
||||||
endian_def_b4(ml, mg, ip, il);
|
|
||||||
volatile unsigned long unused6; /* +40 */
|
|
||||||
volatile unsigned long istat;
|
|
||||||
volatile unsigned long iim;
|
|
||||||
volatile unsigned long rrt;
|
|
||||||
volatile unsigned long unused7[3]; /* +50 */
|
|
||||||
volatile unsigned long ipbmma;
|
|
||||||
volatile unsigned long ipbioma; /* +60 */
|
|
||||||
volatile unsigned long ilbmma;
|
|
||||||
volatile unsigned long ilbioma;
|
|
||||||
volatile unsigned long unused8[9];
|
|
||||||
volatile unsigned long tc; /* +90 */
|
|
||||||
volatile unsigned long tstat;
|
|
||||||
volatile unsigned long tim;
|
|
||||||
volatile unsigned long tccmd;
|
|
||||||
volatile unsigned long pcirrt; /* +a0 */
|
|
||||||
volatile unsigned long pcirrt_cmd;
|
|
||||||
volatile unsigned long pcirrdt;
|
|
||||||
volatile unsigned long unused9[3];
|
|
||||||
volatile unsigned long tlboap;
|
|
||||||
volatile unsigned long tlbiap;
|
|
||||||
volatile unsigned long tlbmma; /* +c0 */
|
|
||||||
volatile unsigned long tlbioma;
|
|
||||||
volatile unsigned long sc_msg;
|
|
||||||
volatile unsigned long sc_be;
|
|
||||||
volatile unsigned long tbl; /* +d0 */
|
|
||||||
volatile unsigned long unused10[3];
|
|
||||||
volatile unsigned long pwmng; /* +e0 */
|
|
||||||
volatile unsigned long pwmngs;
|
|
||||||
volatile unsigned long unused11[6];
|
|
||||||
volatile unsigned long req_trace; /* +100 */
|
|
||||||
volatile unsigned long pbapmc;
|
|
||||||
volatile unsigned long pbapms;
|
|
||||||
volatile unsigned long pbapmim;
|
|
||||||
volatile unsigned long bm; /* +110 */
|
|
||||||
volatile unsigned long cpcibrs;
|
|
||||||
volatile unsigned long cpcibgs;
|
|
||||||
volatile unsigned long pbacs;
|
|
||||||
volatile unsigned long iobas; /* +120 */
|
|
||||||
volatile unsigned long mbas;
|
|
||||||
volatile unsigned long lbc;
|
|
||||||
volatile unsigned long lbstat;
|
|
||||||
volatile unsigned long lbim; /* +130 */
|
|
||||||
volatile unsigned long pcistatim;
|
|
||||||
volatile unsigned long ica;
|
|
||||||
volatile unsigned long icd;
|
|
||||||
volatile unsigned long iiadp; /* +140 */
|
|
||||||
volatile unsigned long iscdp;
|
|
||||||
volatile unsigned long mmas;
|
|
||||||
volatile unsigned long iomas;
|
|
||||||
volatile unsigned long ipciaddr; /* +150 */
|
|
||||||
volatile unsigned long ipcidata;
|
|
||||||
volatile unsigned long ipcibe;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct tx3927_ccfg_reg {
|
|
||||||
volatile unsigned long ccfg;
|
|
||||||
volatile unsigned long crir;
|
|
||||||
volatile unsigned long pcfg;
|
|
||||||
volatile unsigned long tear;
|
|
||||||
volatile unsigned long pdcr;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SDRAMC
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* ROMC
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DMA
|
|
||||||
*/
|
|
||||||
/* bits for MCR */
|
|
||||||
#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
|
|
||||||
#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
|
|
||||||
#define TX3927_DMA_MCR_RSFIF 0x00000080
|
|
||||||
#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
|
|
||||||
#define TX3927_DMA_MCR_LE 0x00000004
|
|
||||||
#define TX3927_DMA_MCR_RPRT 0x00000002
|
|
||||||
#define TX3927_DMA_MCR_MSTEN 0x00000001
|
|
||||||
|
|
||||||
/* bits for CCRn */
|
|
||||||
#define TX3927_DMA_CCR_DBINH 0x04000000
|
|
||||||
#define TX3927_DMA_CCR_SBINH 0x02000000
|
|
||||||
#define TX3927_DMA_CCR_CHRST 0x01000000
|
|
||||||
#define TX3927_DMA_CCR_RVBYTE 0x00800000
|
|
||||||
#define TX3927_DMA_CCR_ACKPOL 0x00400000
|
|
||||||
#define TX3927_DMA_CCR_REQPL 0x00200000
|
|
||||||
#define TX3927_DMA_CCR_EGREQ 0x00100000
|
|
||||||
#define TX3927_DMA_CCR_CHDN 0x00080000
|
|
||||||
#define TX3927_DMA_CCR_DNCTL 0x00060000
|
|
||||||
#define TX3927_DMA_CCR_EXTRQ 0x00010000
|
|
||||||
#define TX3927_DMA_CCR_INTRQD 0x0000e000
|
|
||||||
#define TX3927_DMA_CCR_INTENE 0x00001000
|
|
||||||
#define TX3927_DMA_CCR_INTENC 0x00000800
|
|
||||||
#define TX3927_DMA_CCR_INTENT 0x00000400
|
|
||||||
#define TX3927_DMA_CCR_CHNEN 0x00000200
|
|
||||||
#define TX3927_DMA_CCR_XFACT 0x00000100
|
|
||||||
#define TX3927_DMA_CCR_SNOP 0x00000080
|
|
||||||
#define TX3927_DMA_CCR_DSTINC 0x00000040
|
|
||||||
#define TX3927_DMA_CCR_SRCINC 0x00000020
|
|
||||||
#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
|
|
||||||
#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
|
|
||||||
#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
|
|
||||||
#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
|
|
||||||
#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
|
|
||||||
#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
|
|
||||||
#define TX3927_DMA_CCR_MEMIO 0x00000002
|
|
||||||
#define TX3927_DMA_CCR_ONEAD 0x00000001
|
|
||||||
|
|
||||||
/* bits for CSRn */
|
|
||||||
#define TX3927_DMA_CSR_CHNACT 0x00000100
|
|
||||||
#define TX3927_DMA_CSR_ABCHC 0x00000080
|
|
||||||
#define TX3927_DMA_CSR_NCHNC 0x00000040
|
|
||||||
#define TX3927_DMA_CSR_NTRNFC 0x00000020
|
|
||||||
#define TX3927_DMA_CSR_EXTDN 0x00000010
|
|
||||||
#define TX3927_DMA_CSR_CFERR 0x00000008
|
|
||||||
#define TX3927_DMA_CSR_CHERR 0x00000004
|
|
||||||
#define TX3927_DMA_CSR_DESERR 0x00000002
|
|
||||||
#define TX3927_DMA_CSR_SORERR 0x00000001
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IRC
|
|
||||||
*/
|
|
||||||
#define TX3927_IR_INT0 0
|
|
||||||
#define TX3927_IR_INT1 1
|
|
||||||
#define TX3927_IR_INT2 2
|
|
||||||
#define TX3927_IR_INT3 3
|
|
||||||
#define TX3927_IR_INT4 4
|
|
||||||
#define TX3927_IR_INT5 5
|
|
||||||
#define TX3927_IR_SIO0 6
|
|
||||||
#define TX3927_IR_SIO1 7
|
|
||||||
#define TX3927_IR_SIO(ch) (6 + (ch))
|
|
||||||
#define TX3927_IR_DMA 8
|
|
||||||
#define TX3927_IR_PIO 9
|
|
||||||
#define TX3927_IR_PCI 10
|
|
||||||
#define TX3927_IR_TMR(ch) (13 + (ch))
|
|
||||||
#define TX3927_NUM_IR 16
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PCIC
|
|
||||||
*/
|
|
||||||
/* bits for PCICMD */
|
|
||||||
/* see PCI_COMMAND_XXX in linux/pci.h */
|
|
||||||
|
|
||||||
/* bits for PCISTAT */
|
|
||||||
/* see PCI_STATUS_XXX in linux/pci.h */
|
|
||||||
#define PCI_STATUS_NEW_CAP 0x0010
|
|
||||||
|
|
||||||
/* bits for ISTAT/IIM */
|
|
||||||
#define TX3927_PCIC_IIM_ALL 0x00001600
|
|
||||||
|
|
||||||
/* bits for TC */
|
|
||||||
#define TX3927_PCIC_TC_OF16E 0x00000020
|
|
||||||
#define TX3927_PCIC_TC_IF8E 0x00000010
|
|
||||||
#define TX3927_PCIC_TC_OF8E 0x00000008
|
|
||||||
|
|
||||||
/* bits for TSTAT/TIM */
|
|
||||||
#define TX3927_PCIC_TIM_ALL 0x0003ffff
|
|
||||||
|
|
||||||
/* bits for IOBA/MBA */
|
|
||||||
/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
|
|
||||||
|
|
||||||
/* bits for PBAPMC */
|
|
||||||
#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
|
|
||||||
#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
|
|
||||||
#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
|
|
||||||
|
|
||||||
/* bits for LBSTAT/LBIM */
|
|
||||||
#define TX3927_PCIC_LBIM_ALL 0x0000003e
|
|
||||||
|
|
||||||
/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
|
|
||||||
#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
|
|
||||||
|
|
||||||
/* bits for LBC */
|
|
||||||
#define TX3927_PCIC_LBC_IBSE 0x00004000
|
|
||||||
#define TX3927_PCIC_LBC_TIBSE 0x00002000
|
|
||||||
#define TX3927_PCIC_LBC_TMFBSE 0x00001000
|
|
||||||
#define TX3927_PCIC_LBC_HRST 0x00000800
|
|
||||||
#define TX3927_PCIC_LBC_SRST 0x00000400
|
|
||||||
#define TX3927_PCIC_LBC_EPCAD 0x00000200
|
|
||||||
#define TX3927_PCIC_LBC_MSDSE 0x00000100
|
|
||||||
#define TX3927_PCIC_LBC_CRR 0x00000080
|
|
||||||
#define TX3927_PCIC_LBC_ILMDE 0x00000040
|
|
||||||
#define TX3927_PCIC_LBC_ILIDE 0x00000020
|
|
||||||
|
|
||||||
#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
|
|
||||||
#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* CCFG
|
|
||||||
*/
|
|
||||||
/* CCFG : Chip Configuration */
|
|
||||||
#define TX3927_CCFG_TLBOFF 0x00020000
|
|
||||||
#define TX3927_CCFG_BEOW 0x00010000
|
|
||||||
#define TX3927_CCFG_WR 0x00008000
|
|
||||||
#define TX3927_CCFG_TOE 0x00004000
|
|
||||||
#define TX3927_CCFG_PCIXARB 0x00002000
|
|
||||||
#define TX3927_CCFG_PCI3 0x00001000
|
|
||||||
#define TX3927_CCFG_PSNP 0x00000800
|
|
||||||
#define TX3927_CCFG_PPRI 0x00000400
|
|
||||||
#define TX3927_CCFG_PLLM 0x00000030
|
|
||||||
#define TX3927_CCFG_ENDIAN 0x00000004
|
|
||||||
#define TX3927_CCFG_HALT 0x00000002
|
|
||||||
#define TX3927_CCFG_ACEHOLD 0x00000001
|
|
||||||
|
|
||||||
/* PCFG : Pin Configuration */
|
|
||||||
#define TX3927_PCFG_SYSCLKEN 0x08000000
|
|
||||||
#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
|
|
||||||
#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
|
|
||||||
#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
|
|
||||||
#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
|
|
||||||
#define TX3927_PCFG_SELALL 0x0003ffff
|
|
||||||
#define TX3927_PCFG_SELCS 0x00020000
|
|
||||||
#define TX3927_PCFG_SELDSF 0x00010000
|
|
||||||
#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
|
|
||||||
#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
|
|
||||||
#define TX3927_PCFG_SELSIO_ALL 0x00003000
|
|
||||||
#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
|
|
||||||
#define TX3927_PCFG_SELTMR_ALL 0x00000e00
|
|
||||||
#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
|
|
||||||
#define TX3927_PCFG_SELDONE 0x00000100
|
|
||||||
#define TX3927_PCFG_INTDMA_ALL 0x000000f0
|
|
||||||
#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
|
|
||||||
#define TX3927_PCFG_SELDMA_ALL 0x0000000f
|
|
||||||
#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
|
|
||||||
|
|
||||||
#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
|
|
||||||
#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
|
|
||||||
#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
|
|
||||||
#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
|
|
||||||
#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
|
|
||||||
#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
|
|
||||||
#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
|
|
||||||
|
|
||||||
#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16)
|
|
||||||
#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
|
|
||||||
#define TX3927_ROMC_SIZE(ch) \
|
|
||||||
(0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
|
|
||||||
#define TX3927_ROMC_WIDTH(ch) (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1))
|
|
||||||
|
|
||||||
void tx3927_wdt_init(void);
|
|
||||||
void tx3927_setup(void);
|
|
||||||
void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
|
|
||||||
void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
|
|
||||||
struct pci_controller;
|
|
||||||
void tx3927_pcic_setup(struct pci_controller *channel,
|
|
||||||
unsigned long sdram_size, int extarb);
|
|
||||||
void tx3927_setup_pcierr_irq(void);
|
|
||||||
void tx3927_irq_init(void);
|
|
||||||
void tx3927_mtd_init(int ch);
|
|
||||||
|
|
||||||
#endif /* __ASM_TXX9_TX3927_H */
|
|
||||||
@ -21,11 +21,7 @@
|
|||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_CPU_TX39XX
|
|
||||||
#define TXx9_MAX_IR 16
|
|
||||||
#else
|
|
||||||
#define TXx9_MAX_IR 32
|
#define TXx9_MAX_IR 32
|
||||||
#endif
|
|
||||||
|
|
||||||
void txx9_irq_init(unsigned long baseaddr);
|
void txx9_irq_init(unsigned long baseaddr);
|
||||||
int txx9_irq(void);
|
int txx9_irq(void);
|
||||||
|
|||||||
@ -58,10 +58,6 @@ void txx9_clockevent_init(unsigned long baseaddr, int irq,
|
|||||||
unsigned int imbusclk);
|
unsigned int imbusclk);
|
||||||
void txx9_tmr_init(unsigned long baseaddr);
|
void txx9_tmr_init(unsigned long baseaddr);
|
||||||
|
|
||||||
#ifdef CONFIG_CPU_TX39XX
|
|
||||||
#define TXX9_TIMER_BITS 24
|
|
||||||
#else
|
|
||||||
#define TXX9_TIMER_BITS 32
|
#define TXX9_TIMER_BITS 32
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __ASM_TXX9TMR_H */
|
#endif /* __ASM_TXX9TMR_H */
|
||||||
|
|||||||
@ -22,8 +22,6 @@
|
|||||||
#define MODULE_PROC_FAMILY "MIPS64_R6 "
|
#define MODULE_PROC_FAMILY "MIPS64_R6 "
|
||||||
#elif defined CONFIG_CPU_R3000
|
#elif defined CONFIG_CPU_R3000
|
||||||
#define MODULE_PROC_FAMILY "R3000 "
|
#define MODULE_PROC_FAMILY "R3000 "
|
||||||
#elif defined CONFIG_CPU_TX39XX
|
|
||||||
#define MODULE_PROC_FAMILY "TX39XX "
|
|
||||||
#elif defined CONFIG_CPU_VR41XX
|
#elif defined CONFIG_CPU_VR41XX
|
||||||
#define MODULE_PROC_FAMILY "VR41XX "
|
#define MODULE_PROC_FAMILY "VR41XX "
|
||||||
#elif defined CONFIG_CPU_R4300
|
#elif defined CONFIG_CPU_R4300
|
||||||
|
|||||||
@ -1,73 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is subject to the terms and conditions of the GNU General Public
|
|
||||||
* License. See the file "COPYING" in the main directory of this archive
|
|
||||||
* for more details.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle
|
|
||||||
* Copyright (C) 2007 Maciej W. Rozycki
|
|
||||||
*/
|
|
||||||
#ifndef _ASM_WAR_H
|
|
||||||
#define _ASM_WAR_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Work around certain R4000 CPU errata (as implemented by GCC):
|
|
||||||
*
|
|
||||||
* - A double-word or a variable shift may give an incorrect result
|
|
||||||
* if executed immediately after starting an integer division:
|
|
||||||
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
|
|
||||||
* erratum #28
|
|
||||||
* "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
|
|
||||||
* #19
|
|
||||||
*
|
|
||||||
* - A double-word or a variable shift may give an incorrect result
|
|
||||||
* if executed while an integer multiplication is in progress:
|
|
||||||
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
|
|
||||||
* errata #16 & #28
|
|
||||||
*
|
|
||||||
* - An integer division may give an incorrect result if started in
|
|
||||||
* a delay slot of a taken branch or a jump:
|
|
||||||
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
|
|
||||||
* erratum #52
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_CPU_R4000_WORKAROUNDS
|
|
||||||
#define R4000_WAR 1
|
|
||||||
#else
|
|
||||||
#define R4000_WAR 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Work around certain R4400 CPU errata (as implemented by GCC):
|
|
||||||
*
|
|
||||||
* - A double-word or a variable shift may give an incorrect result
|
|
||||||
* if executed immediately after starting an integer division:
|
|
||||||
* "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
|
|
||||||
* "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_CPU_R4400_WORKAROUNDS
|
|
||||||
#define R4400_WAR 1
|
|
||||||
#else
|
|
||||||
#define R4400_WAR 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Work around the "daddi" and "daddiu" CPU errata:
|
|
||||||
*
|
|
||||||
* - The `daddi' instruction fails to trap on overflow.
|
|
||||||
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
|
|
||||||
* erratum #23
|
|
||||||
*
|
|
||||||
* - The `daddiu' instruction can produce an incorrect result.
|
|
||||||
* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
|
|
||||||
* erratum #41
|
|
||||||
* "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
|
|
||||||
* #15
|
|
||||||
* "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
|
|
||||||
* "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
|
|
||||||
*/
|
|
||||||
#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
|
|
||||||
#define DADDI_WAR 1
|
|
||||||
#else
|
|
||||||
#define DADDI_WAR 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* _ASM_WAR_H */
|
|
||||||
@ -44,7 +44,6 @@ obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
|
|||||||
|
|
||||||
sw-y := r4k_switch.o
|
sw-y := r4k_switch.o
|
||||||
sw-$(CONFIG_CPU_R3000) := r2300_switch.o
|
sw-$(CONFIG_CPU_R3000) := r2300_switch.o
|
||||||
sw-$(CONFIG_CPU_TX39XX) := r2300_switch.o
|
|
||||||
sw-$(CONFIG_CPU_CAVIUM_OCTEON) := octeon_switch.o
|
sw-$(CONFIG_CPU_CAVIUM_OCTEON) := octeon_switch.o
|
||||||
obj-y += $(sw-y)
|
obj-y += $(sw-y)
|
||||||
|
|
||||||
|
|||||||
@ -1189,29 +1189,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
|
|||||||
c->tlbsize = 48;
|
c->tlbsize = 48;
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
case PRID_IMP_TX39:
|
|
||||||
c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
|
|
||||||
c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
|
|
||||||
|
|
||||||
if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
|
|
||||||
c->cputype = CPU_TX3927;
|
|
||||||
__cpu_name[cpu] = "TX3927";
|
|
||||||
c->tlbsize = 64;
|
|
||||||
} else {
|
|
||||||
switch (c->processor_id & PRID_REV_MASK) {
|
|
||||||
case PRID_REV_TX3912:
|
|
||||||
c->cputype = CPU_TX3912;
|
|
||||||
__cpu_name[cpu] = "TX3912";
|
|
||||||
c->tlbsize = 32;
|
|
||||||
break;
|
|
||||||
case PRID_REV_TX3922:
|
|
||||||
c->cputype = CPU_TX3922;
|
|
||||||
__cpu_name[cpu] = "TX3922";
|
|
||||||
c->tlbsize = 64;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case PRID_IMP_R4700:
|
case PRID_IMP_R4700:
|
||||||
c->cputype = CPU_R4700;
|
c->cputype = CPU_R4700;
|
||||||
__cpu_name[cpu] = "R4700";
|
__cpu_name[cpu] = "R4700";
|
||||||
|
|||||||
@ -118,28 +118,6 @@ void cpu_probe(void)
|
|||||||
c->options |= MIPS_CPU_FPU;
|
c->options |= MIPS_CPU_FPU;
|
||||||
c->tlbsize = 64;
|
c->tlbsize = 64;
|
||||||
break;
|
break;
|
||||||
case PRID_COMP_LEGACY | PRID_IMP_TX39:
|
|
||||||
c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
|
|
||||||
|
|
||||||
if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
|
|
||||||
c->cputype = CPU_TX3927;
|
|
||||||
__cpu_name[cpu] = "TX3927";
|
|
||||||
c->tlbsize = 64;
|
|
||||||
} else {
|
|
||||||
switch (c->processor_id & PRID_REV_MASK) {
|
|
||||||
case PRID_REV_TX3912:
|
|
||||||
c->cputype = CPU_TX3912;
|
|
||||||
__cpu_name[cpu] = "TX3912";
|
|
||||||
c->tlbsize = 32;
|
|
||||||
break;
|
|
||||||
case PRID_REV_TX3922:
|
|
||||||
c->cputype = CPU_TX3922;
|
|
||||||
__cpu_name[cpu] = "TX3922";
|
|
||||||
c->tlbsize = 64;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
BUG_ON(!__cpu_name[cpu]);
|
BUG_ON(!__cpu_name[cpu]);
|
||||||
|
|||||||
@ -328,16 +328,10 @@ void mips_set_personality_nan(struct arch_elf_state *state)
|
|||||||
|
|
||||||
int mips_elf_read_implies_exec(void *elf_ex, int exstack)
|
int mips_elf_read_implies_exec(void *elf_ex, int exstack)
|
||||||
{
|
{
|
||||||
if (exstack != EXSTACK_DISABLE_X) {
|
/*
|
||||||
/* The binary doesn't request a non-executable stack */
|
* Set READ_IMPLIES_EXEC only on non-NX systems that
|
||||||
return 1;
|
* do not request a specific state via PT_GNU_STACK.
|
||||||
}
|
*/
|
||||||
|
return (!cpu_has_rixi && exstack == EXSTACK_DEFAULT);
|
||||||
if (!cpu_has_rixi) {
|
|
||||||
/* The CPU doesn't support non-executable memory */
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(mips_elf_read_implies_exec);
|
EXPORT_SYMBOL(mips_elf_read_implies_exec);
|
||||||
|
|||||||
@ -17,7 +17,6 @@
|
|||||||
#include <asm/stackframe.h>
|
#include <asm/stackframe.h>
|
||||||
#include <asm/isadep.h>
|
#include <asm/isadep.h>
|
||||||
#include <asm/thread_info.h>
|
#include <asm/thread_info.h>
|
||||||
#include <asm/war.h>
|
|
||||||
|
|
||||||
#ifndef CONFIG_PREEMPTION
|
#ifndef CONFIG_PREEMPTION
|
||||||
#define resume_kernel restore_all
|
#define resume_kernel restore_all
|
||||||
@ -101,7 +100,7 @@ restore_partial: # restore partial frame
|
|||||||
SAVE_AT
|
SAVE_AT
|
||||||
SAVE_TEMP
|
SAVE_TEMP
|
||||||
LONG_L v0, PT_STATUS(sp)
|
LONG_L v0, PT_STATUS(sp)
|
||||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
#if defined(CONFIG_CPU_R3000)
|
||||||
and v0, ST0_IEP
|
and v0, ST0_IEP
|
||||||
#else
|
#else
|
||||||
and v0, ST0_IE
|
and v0, ST0_IE
|
||||||
|
|||||||
@ -19,7 +19,6 @@
|
|||||||
#include <asm/mipsregs.h>
|
#include <asm/mipsregs.h>
|
||||||
#include <asm/stackframe.h>
|
#include <asm/stackframe.h>
|
||||||
#include <asm/sync.h>
|
#include <asm/sync.h>
|
||||||
#include <asm/war.h>
|
|
||||||
#include <asm/thread_info.h>
|
#include <asm/thread_info.h>
|
||||||
|
|
||||||
__INIT
|
__INIT
|
||||||
@ -163,7 +162,7 @@ NESTED(handle_int, PT_SIZE, sp)
|
|||||||
.set push
|
.set push
|
||||||
.set noat
|
.set noat
|
||||||
mfc0 k0, CP0_STATUS
|
mfc0 k0, CP0_STATUS
|
||||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
#if defined(CONFIG_CPU_R3000)
|
||||||
and k0, ST0_IEP
|
and k0, ST0_IEP
|
||||||
bnez k0, 1f
|
bnez k0, 1f
|
||||||
|
|
||||||
@ -645,7 +644,7 @@ isrdhwr:
|
|||||||
get_saved_sp /* k1 := current_thread_info */
|
get_saved_sp /* k1 := current_thread_info */
|
||||||
.set noreorder
|
.set noreorder
|
||||||
MFC0 k0, CP0_EPC
|
MFC0 k0, CP0_EPC
|
||||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
#if defined(CONFIG_CPU_R3000)
|
||||||
ori k1, _THREAD_MASK
|
ori k1, _THREAD_MASK
|
||||||
xori k1, _THREAD_MASK
|
xori k1, _THREAD_MASK
|
||||||
LONG_L v1, TI_TP_VALUE(k1)
|
LONG_L v1, TI_TP_VALUE(k1)
|
||||||
|
|||||||
@ -36,13 +36,6 @@ static void __cpuidle r3081_wait(void)
|
|||||||
raw_local_irq_enable();
|
raw_local_irq_enable();
|
||||||
}
|
}
|
||||||
|
|
||||||
static void __cpuidle r39xx_wait(void)
|
|
||||||
{
|
|
||||||
if (!need_resched())
|
|
||||||
write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
|
|
||||||
raw_local_irq_enable();
|
|
||||||
}
|
|
||||||
|
|
||||||
void __cpuidle r4k_wait(void)
|
void __cpuidle r4k_wait(void)
|
||||||
{
|
{
|
||||||
raw_local_irq_enable();
|
raw_local_irq_enable();
|
||||||
@ -147,9 +140,6 @@ void __init check_wait(void)
|
|||||||
case CPU_R3081E:
|
case CPU_R3081E:
|
||||||
cpu_wait = r3081_wait;
|
cpu_wait = r3081_wait;
|
||||||
break;
|
break;
|
||||||
case CPU_TX3927:
|
|
||||||
cpu_wait = r39xx_wait;
|
|
||||||
break;
|
|
||||||
case CPU_R4200:
|
case CPU_R4200:
|
||||||
/* case CPU_R4300: */
|
/* case CPU_R4300: */
|
||||||
case CPU_R4600:
|
case CPU_R4600:
|
||||||
|
|||||||
@ -72,11 +72,6 @@ static void txx9_irq_unmask(struct irq_data *d)
|
|||||||
__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
|
__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
|
||||||
| (txx9irq[irq_nr].level << ofs),
|
| (txx9irq[irq_nr].level << ofs),
|
||||||
ilrp);
|
ilrp);
|
||||||
#ifdef CONFIG_CPU_TX39XX
|
|
||||||
/* update IRCSR */
|
|
||||||
__raw_writel(0, &txx9_ircptr->imr);
|
|
||||||
__raw_writel(irc_elevel, &txx9_ircptr->imr);
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void txx9_irq_mask(struct irq_data *d)
|
static inline void txx9_irq_mask(struct irq_data *d)
|
||||||
@ -88,15 +83,7 @@ static inline void txx9_irq_mask(struct irq_data *d)
|
|||||||
__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
|
__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))
|
||||||
| (irc_dlevel << ofs),
|
| (irc_dlevel << ofs),
|
||||||
ilrp);
|
ilrp);
|
||||||
#ifdef CONFIG_CPU_TX39XX
|
|
||||||
/* update IRCSR */
|
|
||||||
__raw_writel(0, &txx9_ircptr->imr);
|
|
||||||
__raw_writel(irc_elevel, &txx9_ircptr->imr);
|
|
||||||
/* flush write buffer */
|
|
||||||
__raw_readl(&txx9_ircptr->ssr);
|
|
||||||
#else
|
|
||||||
mmiowb();
|
mmiowb();
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void txx9_irq_mask_ack(struct irq_data *d)
|
static void txx9_irq_mask_ack(struct irq_data *d)
|
||||||
|
|||||||
@ -181,8 +181,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|||||||
seq_puts(m, " 3k_cache");
|
seq_puts(m, " 3k_cache");
|
||||||
if (cpu_has_4k_cache)
|
if (cpu_has_4k_cache)
|
||||||
seq_puts(m, " 4k_cache");
|
seq_puts(m, " 4k_cache");
|
||||||
if (cpu_has_tx39_cache)
|
|
||||||
seq_puts(m, " tx39_cache");
|
|
||||||
if (cpu_has_octeon_cache)
|
if (cpu_has_octeon_cache)
|
||||||
seq_puts(m, " octeon_cache");
|
seq_puts(m, " octeon_cache");
|
||||||
if (raw_cpu_has_fpu)
|
if (raw_cpu_has_fpu)
|
||||||
|
|||||||
@ -128,7 +128,7 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
|
|||||||
p->thread.reg17 = kthread_arg;
|
p->thread.reg17 = kthread_arg;
|
||||||
p->thread.reg29 = childksp;
|
p->thread.reg29 = childksp;
|
||||||
p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
|
p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
|
||||||
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
|
#if defined(CONFIG_CPU_R3000)
|
||||||
status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
|
status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
|
||||||
((status & (ST0_KUC | ST0_IEC)) << 2);
|
((status & (ST0_KUC | ST0_IEC)) << 2);
|
||||||
#else
|
#else
|
||||||
|
|||||||
@ -64,4 +64,9 @@ int __init __dt_register_buses(const char *bus0, const char *bus1)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void __weak __init device_tree_init(void)
|
||||||
|
{
|
||||||
|
unflatten_and_copy_device_tree();
|
||||||
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -163,7 +163,8 @@ static __always_inline __init void check_mult_sh(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
pr_cont("no.\n");
|
pr_cont("no.\n");
|
||||||
panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
|
panic(bug64hit,
|
||||||
|
IS_ENABLED(CONFIG_CPU_R4000_WORKAROUNDS) ? nowar : r4kwar);
|
||||||
}
|
}
|
||||||
|
|
||||||
static volatile int daddi_ov;
|
static volatile int daddi_ov;
|
||||||
@ -239,7 +240,8 @@ static __init void check_daddi(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
pr_cont("no.\n");
|
pr_cont("no.\n");
|
||||||
panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
|
panic(bug64hit,
|
||||||
|
IS_ENABLED(CONFIG_CPU_DADDI_WORKAROUNDS) ? nowar : daddiwar);
|
||||||
}
|
}
|
||||||
|
|
||||||
int daddiu_bug = -1;
|
int daddiu_bug = -1;
|
||||||
@ -307,7 +309,8 @@ static __init void check_daddiu(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
pr_cont("no.\n");
|
pr_cont("no.\n");
|
||||||
panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
|
panic(bug64hit,
|
||||||
|
IS_ENABLED(CONFIG_CPU_DADDI_WORKAROUNDS) ? nowar : daddiwar);
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init check_bugs64_early(void)
|
void __init check_bugs64_early(void)
|
||||||
|
|||||||
@ -19,7 +19,6 @@
|
|||||||
#include <asm/sysmips.h>
|
#include <asm/sysmips.h>
|
||||||
#include <asm/thread_info.h>
|
#include <asm/thread_info.h>
|
||||||
#include <asm/unistd.h>
|
#include <asm/unistd.h>
|
||||||
#include <asm/war.h>
|
|
||||||
#include <asm/asm-offsets.h>
|
#include <asm/asm-offsets.h>
|
||||||
|
|
||||||
.align 5
|
.align 5
|
||||||
|
|||||||
@ -18,7 +18,6 @@
|
|||||||
#include <asm/sysmips.h>
|
#include <asm/sysmips.h>
|
||||||
#include <asm/thread_info.h>
|
#include <asm/thread_info.h>
|
||||||
#include <asm/unistd.h>
|
#include <asm/unistd.h>
|
||||||
#include <asm/war.h>
|
|
||||||
|
|
||||||
#ifndef CONFIG_MIPS32_COMPAT
|
#ifndef CONFIG_MIPS32_COMPAT
|
||||||
/* Neither O32 nor N32, so define handle_sys here */
|
/* Neither O32 nor N32, so define handle_sys here */
|
||||||
|
|||||||
@ -35,7 +35,6 @@
|
|||||||
#include <asm/sim.h>
|
#include <asm/sim.h>
|
||||||
#include <asm/ucontext.h>
|
#include <asm/ucontext.h>
|
||||||
#include <asm/cpu-features.h>
|
#include <asm/cpu-features.h>
|
||||||
#include <asm/war.h>
|
|
||||||
#include <asm/dsp.h>
|
#include <asm/dsp.h>
|
||||||
#include <asm/inst.h>
|
#include <asm/inst.h>
|
||||||
#include <asm/msa.h>
|
#include <asm/msa.h>
|
||||||
|
|||||||
@ -24,7 +24,6 @@
|
|||||||
#include <asm/ucontext.h>
|
#include <asm/ucontext.h>
|
||||||
#include <asm/fpu.h>
|
#include <asm/fpu.h>
|
||||||
#include <asm/cpu-features.h>
|
#include <asm/cpu-features.h>
|
||||||
#include <asm/war.h>
|
|
||||||
|
|
||||||
#include "signal-common.h"
|
#include "signal-common.h"
|
||||||
|
|
||||||
|
|||||||
@ -2091,19 +2091,19 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
|
|||||||
* If no shadow set is selected then use the default handler
|
* If no shadow set is selected then use the default handler
|
||||||
* that does normal register saving and standard interrupt exit
|
* that does normal register saving and standard interrupt exit
|
||||||
*/
|
*/
|
||||||
extern char except_vec_vi, except_vec_vi_lui;
|
extern const u8 except_vec_vi[], except_vec_vi_lui[];
|
||||||
extern char except_vec_vi_ori, except_vec_vi_end;
|
extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
|
||||||
extern char rollback_except_vec_vi;
|
extern const u8 rollback_except_vec_vi[];
|
||||||
char *vec_start = using_rollback_handler() ?
|
const u8 *vec_start = using_rollback_handler() ?
|
||||||
&rollback_except_vec_vi : &except_vec_vi;
|
rollback_except_vec_vi : except_vec_vi;
|
||||||
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
|
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
|
||||||
const int lui_offset = &except_vec_vi_lui - vec_start + 2;
|
const int lui_offset = except_vec_vi_lui - vec_start + 2;
|
||||||
const int ori_offset = &except_vec_vi_ori - vec_start + 2;
|
const int ori_offset = except_vec_vi_ori - vec_start + 2;
|
||||||
#else
|
#else
|
||||||
const int lui_offset = &except_vec_vi_lui - vec_start;
|
const int lui_offset = except_vec_vi_lui - vec_start;
|
||||||
const int ori_offset = &except_vec_vi_ori - vec_start;
|
const int ori_offset = except_vec_vi_ori - vec_start;
|
||||||
#endif
|
#endif
|
||||||
const int handler_len = &except_vec_vi_end - vec_start;
|
const int handler_len = except_vec_vi_end - vec_start;
|
||||||
|
|
||||||
if (handler_len > VECTORSPACING) {
|
if (handler_len > VECTORSPACING) {
|
||||||
/*
|
/*
|
||||||
@ -2311,7 +2311,7 @@ void per_cpu_trap_init(bool is_boot_cpu)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Install CPU exception handler */
|
/* Install CPU exception handler */
|
||||||
void set_handler(unsigned long offset, void *addr, unsigned long size)
|
void set_handler(unsigned long offset, const void *addr, unsigned long size)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_CPU_MICROMIPS
|
#ifdef CONFIG_CPU_MICROMIPS
|
||||||
memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
|
memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
|
||||||
|
|||||||
@ -84,11 +84,6 @@ void __init plat_mem_setup(void)
|
|||||||
__dt_setup_arch(dtb);
|
__dt_setup_arch(dtb);
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init device_tree_init(void)
|
|
||||||
{
|
|
||||||
unflatten_and_copy_device_tree();
|
|
||||||
}
|
|
||||||
|
|
||||||
void __init prom_init(void)
|
void __init prom_init(void)
|
||||||
{
|
{
|
||||||
/* call the soc specific detetcion code and get it to fill soc_info */
|
/* call the soc specific detetcion code and get it to fill soc_info */
|
||||||
|
|||||||
@ -13,7 +13,6 @@ lib-$(CONFIG_GENERIC_CSUM) := $(filter-out csum_partial.o, $(lib-y))
|
|||||||
|
|
||||||
obj-$(CONFIG_CPU_GENERIC_DUMP_TLB) += dump_tlb.o
|
obj-$(CONFIG_CPU_GENERIC_DUMP_TLB) += dump_tlb.o
|
||||||
obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
|
obj-$(CONFIG_CPU_R3000) += r3k_dump_tlb.o
|
||||||
obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o
|
|
||||||
|
|
||||||
# libgcc-style stuff needed in the kernel
|
# libgcc-style stuff needed in the kernel
|
||||||
obj-y += bswapsi.o bswapdi.o multi3.o
|
obj-y += bswapsi.o bswapdi.o multi3.o
|
||||||
|
|||||||
@ -16,7 +16,6 @@
|
|||||||
|
|
||||||
#include <asm/asm.h>
|
#include <asm/asm.h>
|
||||||
#include <asm/compiler.h>
|
#include <asm/compiler.h>
|
||||||
#include <asm/war.h>
|
|
||||||
|
|
||||||
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
|
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
|
||||||
#define GCC_DADDI_IMM_ASM() "I"
|
#define GCC_DADDI_IMM_ASM() "I"
|
||||||
|
|||||||
@ -14,15 +14,11 @@
|
|||||||
#include <asm/page.h>
|
#include <asm/page.h>
|
||||||
#include <asm/tlbdebug.h>
|
#include <asm/tlbdebug.h>
|
||||||
|
|
||||||
extern int r3k_have_wired_reg;
|
|
||||||
|
|
||||||
void dump_tlb_regs(void)
|
void dump_tlb_regs(void)
|
||||||
{
|
{
|
||||||
pr_info("Index : %0x\n", read_c0_index());
|
pr_info("Index : %0x\n", read_c0_index());
|
||||||
pr_info("EntryHi : %0lx\n", read_c0_entryhi());
|
pr_info("EntryHi : %0lx\n", read_c0_entryhi());
|
||||||
pr_info("EntryLo : %0lx\n", read_c0_entrylo0());
|
pr_info("EntryLo : %0lx\n", read_c0_entrylo0());
|
||||||
if (r3k_have_wired_reg)
|
|
||||||
pr_info("Wired : %0x\n", read_c0_wired());
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dump_tlb(int first, int last)
|
static void dump_tlb(int first, int last)
|
||||||
|
|||||||
@ -41,6 +41,7 @@ cflags-y += $(call cc-option,-mno-loongson-mmi)
|
|||||||
# Loongson Machines' Support
|
# Loongson Machines' Support
|
||||||
#
|
#
|
||||||
|
|
||||||
cflags-$(CONFIG_MACH_LOONGSON2EF) += -I$(srctree)/arch/mips/include/asm/mach-loongson2ef -mno-branch-likely
|
cflags-$(CONFIG_MACH_LOONGSON2EF) += -I$(srctree)/arch/mips/include/asm/mach-loongson2ef
|
||||||
|
cflags-$(CONFIG_CC_HAS_MNO_BRANCH_LIKELY) += -mno-branch-likely
|
||||||
load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
|
load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
|
||||||
load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
|
load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
|
||||||
|
|||||||
@ -5,24 +5,9 @@
|
|||||||
|
|
||||||
cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
|
cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
|
||||||
|
|
||||||
#
|
ifdef CONFIG_CPU_LOONGSON64
|
||||||
# binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
|
cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a
|
||||||
# as MIPS64 R2; older versions as just R1. This leaves the possibility open
|
cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2
|
||||||
# that GCC might generate R2 code for -march=loongson3a which then is rejected
|
|
||||||
# by GAS. The cc-option can't probe for this behaviour so -march=loongson3a
|
|
||||||
# can't easily be used safely within the kbuild framework.
|
|
||||||
#
|
|
||||||
ifeq ($(call cc-ifversion, -ge, 0409, y), y)
|
|
||||||
ifeq ($(call ld-ifversion, -ge, 22500, y), y)
|
|
||||||
cflags-$(CONFIG_CPU_LOONGSON64) += \
|
|
||||||
$(call cc-option,-march=loongson3a -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
|
|
||||||
else
|
|
||||||
cflags-$(CONFIG_CPU_LOONGSON64) += \
|
|
||||||
$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
|
|
||||||
endif
|
|
||||||
else
|
|
||||||
cflags-$(CONFIG_CPU_LOONGSON64) += \
|
|
||||||
$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
# Some -march= flags enable MMI instructions, and GCC complains about that
|
# Some -march= flags enable MMI instructions, and GCC complains about that
|
||||||
@ -33,5 +18,6 @@ cflags-y += $(call cc-option,-mno-loongson-mmi)
|
|||||||
# Loongson Machines' Support
|
# Loongson Machines' Support
|
||||||
#
|
#
|
||||||
|
|
||||||
cflags-$(CONFIG_MACH_LOONGSON64) += -I$(srctree)/arch/mips/include/asm/mach-loongson64 -mno-branch-likely
|
cflags-$(CONFIG_MACH_LOONGSON64) += -I$(srctree)/arch/mips/include/asm/mach-loongson64
|
||||||
|
cflags-$(CONFIG_CC_HAS_MNO_BRANCH_LIKELY) += -mno-branch-likely
|
||||||
load-$(CONFIG_CPU_LOONGSON64) += 0xffffffff80200000
|
load-$(CONFIG_CPU_LOONGSON64) += 0xffffffff80200000
|
||||||
|
|||||||
@ -197,3 +197,13 @@ void __init prom_init_numa_memory(void)
|
|||||||
prom_meminit();
|
prom_meminit();
|
||||||
}
|
}
|
||||||
EXPORT_SYMBOL(prom_init_numa_memory);
|
EXPORT_SYMBOL(prom_init_numa_memory);
|
||||||
|
|
||||||
|
pg_data_t * __init arch_alloc_nodedata(int nid)
|
||||||
|
{
|
||||||
|
return memblock_alloc(sizeof(pg_data_t), SMP_CACHE_BYTES);
|
||||||
|
}
|
||||||
|
|
||||||
|
void arch_refresh_nodedata(int nid, pg_data_t *pgdat)
|
||||||
|
{
|
||||||
|
__node_data[nid] = pgdat;
|
||||||
|
}
|
||||||
|
|||||||
@ -36,11 +36,3 @@ void __init plat_mem_setup(void)
|
|||||||
if (loongson_fdt_blob)
|
if (loongson_fdt_blob)
|
||||||
__dt_setup_arch(loongson_fdt_blob);
|
__dt_setup_arch(loongson_fdt_blob);
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init device_tree_init(void)
|
|
||||||
{
|
|
||||||
if (!initial_boot_params)
|
|
||||||
return;
|
|
||||||
|
|
||||||
unflatten_and_copy_device_tree();
|
|
||||||
}
|
|
||||||
|
|||||||
@ -36,7 +36,6 @@ obj-$(CONFIG_CPU_R3K_TLB) += tlb-r3k.o
|
|||||||
obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
|
obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
|
||||||
obj-$(CONFIG_CPU_R3000) += c-r3k.o
|
obj-$(CONFIG_CPU_R3000) += c-r3k.o
|
||||||
obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
|
obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
|
||||||
obj-$(CONFIG_CPU_TX39XX) += c-tx39.o
|
|
||||||
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
|
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
|
||||||
|
|
||||||
obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
|
obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
|
||||||
|
|||||||
@ -23,7 +23,6 @@
|
|||||||
#include <asm/r4kcache.h>
|
#include <asm/r4kcache.h>
|
||||||
#include <asm/traps.h>
|
#include <asm/traps.h>
|
||||||
#include <asm/mmu_context.h>
|
#include <asm/mmu_context.h>
|
||||||
#include <asm/war.h>
|
|
||||||
|
|
||||||
#include <asm/octeon/octeon.h>
|
#include <asm/octeon/octeon.h>
|
||||||
|
|
||||||
|
|||||||
@ -33,7 +33,6 @@
|
|||||||
#include <asm/r4kcache.h>
|
#include <asm/r4kcache.h>
|
||||||
#include <asm/sections.h>
|
#include <asm/sections.h>
|
||||||
#include <asm/mmu_context.h>
|
#include <asm/mmu_context.h>
|
||||||
#include <asm/war.h>
|
|
||||||
#include <asm/cacheflush.h> /* for run_uncached() */
|
#include <asm/cacheflush.h> /* for run_uncached() */
|
||||||
#include <asm/traps.h>
|
#include <asm/traps.h>
|
||||||
#include <asm/mips-cps.h>
|
#include <asm/mips-cps.h>
|
||||||
|
|||||||
@ -1,414 +0,0 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0
|
|
||||||
/*
|
|
||||||
* r2300.c: R2000 and R3000 specific mmu/cache code.
|
|
||||||
*
|
|
||||||
* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
|
|
||||||
*
|
|
||||||
* with a lot of changes to make this thing work for R3000s
|
|
||||||
* Tx39XX R4k style caches added. HK
|
|
||||||
* Copyright (C) 1998, 1999, 2000 Harald Koerfgen
|
|
||||||
* Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
|
|
||||||
*/
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/sched.h>
|
|
||||||
#include <linux/smp.h>
|
|
||||||
#include <linux/mm.h>
|
|
||||||
|
|
||||||
#include <asm/cacheops.h>
|
|
||||||
#include <asm/page.h>
|
|
||||||
#include <asm/mmu_context.h>
|
|
||||||
#include <asm/isadep.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/bootinfo.h>
|
|
||||||
#include <asm/cpu.h>
|
|
||||||
|
|
||||||
/* For R3000 cores with R4000 style caches */
|
|
||||||
static unsigned long icache_size, dcache_size; /* Size in bytes */
|
|
||||||
|
|
||||||
#include <asm/r4kcache.h>
|
|
||||||
|
|
||||||
/* This sequence is required to ensure icache is disabled immediately */
|
|
||||||
#define TX39_STOP_STREAMING() \
|
|
||||||
__asm__ __volatile__( \
|
|
||||||
".set push\n\t" \
|
|
||||||
".set noreorder\n\t" \
|
|
||||||
"b 1f\n\t" \
|
|
||||||
"nop\n\t" \
|
|
||||||
"1:\n\t" \
|
|
||||||
".set pop" \
|
|
||||||
)
|
|
||||||
|
|
||||||
/* TX39H-style cache flush routines. */
|
|
||||||
static void tx39h_flush_icache_all(void)
|
|
||||||
{
|
|
||||||
unsigned long flags, config;
|
|
||||||
|
|
||||||
/* disable icache (set ICE#) */
|
|
||||||
local_irq_save(flags);
|
|
||||||
config = read_c0_conf();
|
|
||||||
write_c0_conf(config & ~TX39_CONF_ICE);
|
|
||||||
TX39_STOP_STREAMING();
|
|
||||||
blast_icache16();
|
|
||||||
write_c0_conf(config);
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
|
|
||||||
{
|
|
||||||
/* Catch bad driver code */
|
|
||||||
BUG_ON(size == 0);
|
|
||||||
|
|
||||||
iob();
|
|
||||||
blast_inv_dcache_range(addr, addr + size);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/* TX39H2,TX39H3 */
|
|
||||||
static inline void tx39_blast_dcache_page(unsigned long addr)
|
|
||||||
{
|
|
||||||
if (current_cpu_type() != CPU_TX3912)
|
|
||||||
blast_dcache16_page(addr);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void tx39_blast_dcache_page_indexed(unsigned long addr)
|
|
||||||
{
|
|
||||||
blast_dcache16_page_indexed(addr);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void tx39_blast_dcache(void)
|
|
||||||
{
|
|
||||||
blast_dcache16();
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void tx39_blast_icache_page(unsigned long addr)
|
|
||||||
{
|
|
||||||
unsigned long flags, config;
|
|
||||||
/* disable icache (set ICE#) */
|
|
||||||
local_irq_save(flags);
|
|
||||||
config = read_c0_conf();
|
|
||||||
write_c0_conf(config & ~TX39_CONF_ICE);
|
|
||||||
TX39_STOP_STREAMING();
|
|
||||||
blast_icache16_page(addr);
|
|
||||||
write_c0_conf(config);
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void tx39_blast_icache_page_indexed(unsigned long addr)
|
|
||||||
{
|
|
||||||
unsigned long flags, config;
|
|
||||||
/* disable icache (set ICE#) */
|
|
||||||
local_irq_save(flags);
|
|
||||||
config = read_c0_conf();
|
|
||||||
write_c0_conf(config & ~TX39_CONF_ICE);
|
|
||||||
TX39_STOP_STREAMING();
|
|
||||||
blast_icache16_page_indexed(addr);
|
|
||||||
write_c0_conf(config);
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void tx39_blast_icache(void)
|
|
||||||
{
|
|
||||||
unsigned long flags, config;
|
|
||||||
/* disable icache (set ICE#) */
|
|
||||||
local_irq_save(flags);
|
|
||||||
config = read_c0_conf();
|
|
||||||
write_c0_conf(config & ~TX39_CONF_ICE);
|
|
||||||
TX39_STOP_STREAMING();
|
|
||||||
blast_icache16();
|
|
||||||
write_c0_conf(config);
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39__flush_cache_vmap(void)
|
|
||||||
{
|
|
||||||
tx39_blast_dcache();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39__flush_cache_vunmap(void)
|
|
||||||
{
|
|
||||||
tx39_blast_dcache();
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void tx39_flush_cache_all(void)
|
|
||||||
{
|
|
||||||
if (!cpu_has_dc_aliases)
|
|
||||||
return;
|
|
||||||
|
|
||||||
tx39_blast_dcache();
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void tx39___flush_cache_all(void)
|
|
||||||
{
|
|
||||||
tx39_blast_dcache();
|
|
||||||
tx39_blast_icache();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39_flush_cache_mm(struct mm_struct *mm)
|
|
||||||
{
|
|
||||||
if (!cpu_has_dc_aliases)
|
|
||||||
return;
|
|
||||||
|
|
||||||
if (cpu_context(smp_processor_id(), mm) != 0)
|
|
||||||
tx39_blast_dcache();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39_flush_cache_range(struct vm_area_struct *vma,
|
|
||||||
unsigned long start, unsigned long end)
|
|
||||||
{
|
|
||||||
if (!cpu_has_dc_aliases)
|
|
||||||
return;
|
|
||||||
if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
|
|
||||||
return;
|
|
||||||
|
|
||||||
tx39_blast_dcache();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page, unsigned long pfn)
|
|
||||||
{
|
|
||||||
int exec = vma->vm_flags & VM_EXEC;
|
|
||||||
struct mm_struct *mm = vma->vm_mm;
|
|
||||||
pmd_t *pmdp;
|
|
||||||
pte_t *ptep;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* If ownes no valid ASID yet, cannot possibly have gotten
|
|
||||||
* this page into the cache.
|
|
||||||
*/
|
|
||||||
if (cpu_context(smp_processor_id(), mm) == 0)
|
|
||||||
return;
|
|
||||||
|
|
||||||
page &= PAGE_MASK;
|
|
||||||
pmdp = pmd_off(mm, page);
|
|
||||||
ptep = pte_offset_kernel(pmdp, page);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* If the page isn't marked valid, the page cannot possibly be
|
|
||||||
* in the cache.
|
|
||||||
*/
|
|
||||||
if (!(pte_val(*ptep) & _PAGE_PRESENT))
|
|
||||||
return;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Doing flushes for another ASID than the current one is
|
|
||||||
* too difficult since stupid R4k caches do a TLB translation
|
|
||||||
* for every cache flush operation. So we do indexed flushes
|
|
||||||
* in that case, which doesn't overly flush the cache too much.
|
|
||||||
*/
|
|
||||||
if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
|
|
||||||
if (cpu_has_dc_aliases || exec)
|
|
||||||
tx39_blast_dcache_page(page);
|
|
||||||
if (exec)
|
|
||||||
tx39_blast_icache_page(page);
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Do indexed flush, too much work to get the (possible) TLB refills
|
|
||||||
* to work correctly.
|
|
||||||
*/
|
|
||||||
if (cpu_has_dc_aliases || exec)
|
|
||||||
tx39_blast_dcache_page_indexed(page);
|
|
||||||
if (exec)
|
|
||||||
tx39_blast_icache_page_indexed(page);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void local_tx39_flush_data_cache_page(void * addr)
|
|
||||||
{
|
|
||||||
tx39_blast_dcache_page((unsigned long)addr);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39_flush_data_cache_page(unsigned long addr)
|
|
||||||
{
|
|
||||||
tx39_blast_dcache_page(addr);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39_flush_icache_range(unsigned long start, unsigned long end)
|
|
||||||
{
|
|
||||||
if (end - start > dcache_size)
|
|
||||||
tx39_blast_dcache();
|
|
||||||
else
|
|
||||||
protected_blast_dcache_range(start, end);
|
|
||||||
|
|
||||||
if (end - start > icache_size)
|
|
||||||
tx39_blast_icache();
|
|
||||||
else {
|
|
||||||
unsigned long flags, config;
|
|
||||||
/* disable icache (set ICE#) */
|
|
||||||
local_irq_save(flags);
|
|
||||||
config = read_c0_conf();
|
|
||||||
write_c0_conf(config & ~TX39_CONF_ICE);
|
|
||||||
TX39_STOP_STREAMING();
|
|
||||||
protected_blast_icache_range(start, end);
|
|
||||||
write_c0_conf(config);
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39_flush_kernel_vmap_range(unsigned long vaddr, int size)
|
|
||||||
{
|
|
||||||
BUG();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39_dma_cache_wback_inv(unsigned long addr, unsigned long size)
|
|
||||||
{
|
|
||||||
unsigned long end;
|
|
||||||
|
|
||||||
if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
|
|
||||||
end = addr + size;
|
|
||||||
do {
|
|
||||||
tx39_blast_dcache_page(addr);
|
|
||||||
addr += PAGE_SIZE;
|
|
||||||
} while(addr != end);
|
|
||||||
} else if (size > dcache_size) {
|
|
||||||
tx39_blast_dcache();
|
|
||||||
} else {
|
|
||||||
blast_dcache_range(addr, addr + size);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tx39_dma_cache_inv(unsigned long addr, unsigned long size)
|
|
||||||
{
|
|
||||||
unsigned long end;
|
|
||||||
|
|
||||||
if (((size | addr) & (PAGE_SIZE - 1)) == 0) {
|
|
||||||
end = addr + size;
|
|
||||||
do {
|
|
||||||
tx39_blast_dcache_page(addr);
|
|
||||||
addr += PAGE_SIZE;
|
|
||||||
} while(addr != end);
|
|
||||||
} else if (size > dcache_size) {
|
|
||||||
tx39_blast_dcache();
|
|
||||||
} else {
|
|
||||||
blast_inv_dcache_range(addr, addr + size);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static __init void tx39_probe_cache(void)
|
|
||||||
{
|
|
||||||
unsigned long config;
|
|
||||||
|
|
||||||
config = read_c0_conf();
|
|
||||||
|
|
||||||
icache_size = 1 << (10 + ((config & TX39_CONF_ICS_MASK) >>
|
|
||||||
TX39_CONF_ICS_SHIFT));
|
|
||||||
dcache_size = 1 << (10 + ((config & TX39_CONF_DCS_MASK) >>
|
|
||||||
TX39_CONF_DCS_SHIFT));
|
|
||||||
|
|
||||||
current_cpu_data.icache.linesz = 16;
|
|
||||||
switch (current_cpu_type()) {
|
|
||||||
case CPU_TX3912:
|
|
||||||
current_cpu_data.icache.ways = 1;
|
|
||||||
current_cpu_data.dcache.ways = 1;
|
|
||||||
current_cpu_data.dcache.linesz = 4;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case CPU_TX3927:
|
|
||||||
current_cpu_data.icache.ways = 2;
|
|
||||||
current_cpu_data.dcache.ways = 2;
|
|
||||||
current_cpu_data.dcache.linesz = 16;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case CPU_TX3922:
|
|
||||||
default:
|
|
||||||
current_cpu_data.icache.ways = 1;
|
|
||||||
current_cpu_data.dcache.ways = 1;
|
|
||||||
current_cpu_data.dcache.linesz = 16;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void tx39_cache_init(void)
|
|
||||||
{
|
|
||||||
extern void build_clear_page(void);
|
|
||||||
extern void build_copy_page(void);
|
|
||||||
unsigned long config;
|
|
||||||
|
|
||||||
config = read_c0_conf();
|
|
||||||
config &= ~TX39_CONF_WBON;
|
|
||||||
write_c0_conf(config);
|
|
||||||
|
|
||||||
tx39_probe_cache();
|
|
||||||
|
|
||||||
switch (current_cpu_type()) {
|
|
||||||
case CPU_TX3912:
|
|
||||||
/* TX39/H core (writethru direct-map cache) */
|
|
||||||
__flush_cache_vmap = tx39__flush_cache_vmap;
|
|
||||||
__flush_cache_vunmap = tx39__flush_cache_vunmap;
|
|
||||||
flush_cache_all = tx39h_flush_icache_all;
|
|
||||||
__flush_cache_all = tx39h_flush_icache_all;
|
|
||||||
flush_cache_mm = (void *) tx39h_flush_icache_all;
|
|
||||||
flush_cache_range = (void *) tx39h_flush_icache_all;
|
|
||||||
flush_cache_page = (void *) tx39h_flush_icache_all;
|
|
||||||
flush_icache_range = (void *) tx39h_flush_icache_all;
|
|
||||||
local_flush_icache_range = (void *) tx39h_flush_icache_all;
|
|
||||||
|
|
||||||
local_flush_data_cache_page = (void *) tx39h_flush_icache_all;
|
|
||||||
flush_data_cache_page = (void *) tx39h_flush_icache_all;
|
|
||||||
|
|
||||||
_dma_cache_wback_inv = tx39h_dma_cache_wback_inv;
|
|
||||||
|
|
||||||
shm_align_mask = PAGE_SIZE - 1;
|
|
||||||
|
|
||||||
break;
|
|
||||||
|
|
||||||
case CPU_TX3922:
|
|
||||||
case CPU_TX3927:
|
|
||||||
default:
|
|
||||||
/* TX39/H2,H3 core (writeback 2way-set-associative cache) */
|
|
||||||
/* board-dependent init code may set WBON */
|
|
||||||
|
|
||||||
__flush_cache_vmap = tx39__flush_cache_vmap;
|
|
||||||
__flush_cache_vunmap = tx39__flush_cache_vunmap;
|
|
||||||
|
|
||||||
flush_cache_all = tx39_flush_cache_all;
|
|
||||||
__flush_cache_all = tx39___flush_cache_all;
|
|
||||||
flush_cache_mm = tx39_flush_cache_mm;
|
|
||||||
flush_cache_range = tx39_flush_cache_range;
|
|
||||||
flush_cache_page = tx39_flush_cache_page;
|
|
||||||
flush_icache_range = tx39_flush_icache_range;
|
|
||||||
local_flush_icache_range = tx39_flush_icache_range;
|
|
||||||
|
|
||||||
__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
|
|
||||||
|
|
||||||
local_flush_data_cache_page = local_tx39_flush_data_cache_page;
|
|
||||||
flush_data_cache_page = tx39_flush_data_cache_page;
|
|
||||||
|
|
||||||
_dma_cache_wback_inv = tx39_dma_cache_wback_inv;
|
|
||||||
_dma_cache_wback = tx39_dma_cache_wback_inv;
|
|
||||||
_dma_cache_inv = tx39_dma_cache_inv;
|
|
||||||
|
|
||||||
shm_align_mask = max_t(unsigned long,
|
|
||||||
(dcache_size / current_cpu_data.dcache.ways) - 1,
|
|
||||||
PAGE_SIZE - 1);
|
|
||||||
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
__flush_icache_user_range = flush_icache_range;
|
|
||||||
__local_flush_icache_user_range = local_flush_icache_range;
|
|
||||||
|
|
||||||
current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways;
|
|
||||||
current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways;
|
|
||||||
|
|
||||||
current_cpu_data.icache.sets =
|
|
||||||
current_cpu_data.icache.waysize / current_cpu_data.icache.linesz;
|
|
||||||
current_cpu_data.dcache.sets =
|
|
||||||
current_cpu_data.dcache.waysize / current_cpu_data.dcache.linesz;
|
|
||||||
|
|
||||||
if (current_cpu_data.dcache.waysize > PAGE_SIZE)
|
|
||||||
current_cpu_data.dcache.flags |= MIPS_CACHE_ALIASES;
|
|
||||||
|
|
||||||
current_cpu_data.icache.waybit = 0;
|
|
||||||
current_cpu_data.dcache.waybit = 0;
|
|
||||||
|
|
||||||
pr_info("Primary instruction cache %ldkB, linesize %d bytes\n",
|
|
||||||
icache_size >> 10, current_cpu_data.icache.linesz);
|
|
||||||
pr_info("Primary data cache %ldkB, linesize %d bytes\n",
|
|
||||||
dcache_size >> 10, current_cpu_data.dcache.linesz);
|
|
||||||
|
|
||||||
build_clear_page();
|
|
||||||
build_copy_page();
|
|
||||||
tx39h_flush_icache_all();
|
|
||||||
}
|
|
||||||
@ -195,11 +195,6 @@ void cpu_cache_init(void)
|
|||||||
|
|
||||||
r4k_cache_init();
|
r4k_cache_init();
|
||||||
}
|
}
|
||||||
if (cpu_has_tx39_cache) {
|
|
||||||
extern void __weak tx39_cache_init(void);
|
|
||||||
|
|
||||||
tx39_cache_init();
|
|
||||||
}
|
|
||||||
|
|
||||||
if (cpu_has_octeon_cache) {
|
if (cpu_has_octeon_cache) {
|
||||||
extern void __weak octeon_cache_init(void);
|
extern void __weak octeon_cache_init(void);
|
||||||
|
|||||||
@ -25,7 +25,6 @@
|
|||||||
#include <asm/mipsregs.h>
|
#include <asm/mipsregs.h>
|
||||||
#include <asm/mmu_context.h>
|
#include <asm/mmu_context.h>
|
||||||
#include <asm/cpu.h>
|
#include <asm/cpu.h>
|
||||||
#include <asm/war.h>
|
|
||||||
|
|
||||||
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
|
#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
|
||||||
#include <asm/sibyte/sb1250.h>
|
#include <asm/sibyte/sb1250.h>
|
||||||
@ -103,7 +102,9 @@ static int cache_line_size;
|
|||||||
static inline void
|
static inline void
|
||||||
pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
|
pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off)
|
||||||
{
|
{
|
||||||
if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
|
if (cpu_has_64bit_gp_regs &&
|
||||||
|
IS_ENABLED(CONFIG_CPU_DADDI_WORKAROUNDS) &&
|
||||||
|
r4k_daddiu_bug()) {
|
||||||
if (off > 0x7fff) {
|
if (off > 0x7fff) {
|
||||||
uasm_i_lui(buf, T9, uasm_rel_hi(off));
|
uasm_i_lui(buf, T9, uasm_rel_hi(off));
|
||||||
uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
|
uasm_i_addiu(buf, T9, T9, uasm_rel_lo(off));
|
||||||
|
|||||||
@ -36,8 +36,6 @@ extern void build_tlb_refill_handler(void);
|
|||||||
"nop\n\t" \
|
"nop\n\t" \
|
||||||
".set pop\n\t")
|
".set pop\n\t")
|
||||||
|
|
||||||
int r3k_have_wired_reg; /* Should be in cpu_data? */
|
|
||||||
|
|
||||||
/* TLB operations. */
|
/* TLB operations. */
|
||||||
static void local_flush_tlb_from(int entry)
|
static void local_flush_tlb_from(int entry)
|
||||||
{
|
{
|
||||||
@ -62,7 +60,7 @@ void local_flush_tlb_all(void)
|
|||||||
printk("[tlball]");
|
printk("[tlball]");
|
||||||
#endif
|
#endif
|
||||||
local_irq_save(flags);
|
local_irq_save(flags);
|
||||||
local_flush_tlb_from(r3k_have_wired_reg ? read_c0_wired() : 8);
|
local_flush_tlb_from(8);
|
||||||
local_irq_restore(flags);
|
local_irq_restore(flags);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -224,34 +222,7 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|||||||
unsigned long old_ctx;
|
unsigned long old_ctx;
|
||||||
static unsigned long wired = 0;
|
static unsigned long wired = 0;
|
||||||
|
|
||||||
if (r3k_have_wired_reg) { /* TX39XX */
|
if (wired < 8) {
|
||||||
unsigned long old_pagemask;
|
|
||||||
unsigned long w;
|
|
||||||
|
|
||||||
#ifdef DEBUG_TLB
|
|
||||||
printk("[tlbwired<entry lo0 %8x, hi %8x\n, pagemask %8x>]\n",
|
|
||||||
entrylo0, entryhi, pagemask);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
/* Save old context and create impossible VPN2 value */
|
|
||||||
old_ctx = read_c0_entryhi() & asid_mask;
|
|
||||||
old_pagemask = read_c0_pagemask();
|
|
||||||
w = read_c0_wired();
|
|
||||||
write_c0_wired(w + 1);
|
|
||||||
write_c0_index(w << 8);
|
|
||||||
write_c0_pagemask(pagemask);
|
|
||||||
write_c0_entryhi(entryhi);
|
|
||||||
write_c0_entrylo0(entrylo0);
|
|
||||||
BARRIER;
|
|
||||||
tlb_write_indexed();
|
|
||||||
|
|
||||||
write_c0_entryhi(old_ctx);
|
|
||||||
write_c0_pagemask(old_pagemask);
|
|
||||||
local_flush_tlb_all();
|
|
||||||
local_irq_restore(flags);
|
|
||||||
|
|
||||||
} else if (wired < 8) {
|
|
||||||
#ifdef DEBUG_TLB
|
#ifdef DEBUG_TLB
|
||||||
printk("[tlbwired<entry lo0 %8x, hi %8x\n>]\n",
|
printk("[tlbwired<entry lo0 %8x, hi %8x\n>]\n",
|
||||||
entrylo0, entryhi);
|
entrylo0, entryhi);
|
||||||
@ -272,13 +243,6 @@ void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
|
|||||||
|
|
||||||
void tlb_init(void)
|
void tlb_init(void)
|
||||||
{
|
{
|
||||||
switch (current_cpu_type()) {
|
|
||||||
case CPU_TX3922:
|
|
||||||
case CPU_TX3927:
|
|
||||||
r3k_have_wired_reg = 1;
|
|
||||||
write_c0_wired(0); /* Set to 8 on reset... */
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
local_flush_tlb_from(0);
|
local_flush_tlb_from(0);
|
||||||
build_tlb_refill_handler();
|
build_tlb_refill_handler();
|
||||||
}
|
}
|
||||||
|
|||||||
@ -33,7 +33,6 @@
|
|||||||
#include <asm/cacheflush.h>
|
#include <asm/cacheflush.h>
|
||||||
#include <asm/cpu-type.h>
|
#include <asm/cpu-type.h>
|
||||||
#include <asm/mmu_context.h>
|
#include <asm/mmu_context.h>
|
||||||
#include <asm/war.h>
|
|
||||||
#include <asm/uasm.h>
|
#include <asm/uasm.h>
|
||||||
#include <asm/setup.h>
|
#include <asm/setup.h>
|
||||||
#include <asm/tlbex.h>
|
#include <asm/tlbex.h>
|
||||||
@ -2160,16 +2159,14 @@ static void build_r4000_tlb_load_handler(void)
|
|||||||
uasm_i_tlbr(&p);
|
uasm_i_tlbr(&p);
|
||||||
|
|
||||||
switch (current_cpu_type()) {
|
switch (current_cpu_type()) {
|
||||||
default:
|
|
||||||
if (cpu_has_mips_r2_exec_hazard) {
|
|
||||||
uasm_i_ehb(&p);
|
|
||||||
fallthrough;
|
|
||||||
|
|
||||||
case CPU_CAVIUM_OCTEON:
|
case CPU_CAVIUM_OCTEON:
|
||||||
case CPU_CAVIUM_OCTEON_PLUS:
|
case CPU_CAVIUM_OCTEON_PLUS:
|
||||||
case CPU_CAVIUM_OCTEON2:
|
case CPU_CAVIUM_OCTEON2:
|
||||||
break;
|
break;
|
||||||
}
|
default:
|
||||||
|
if (cpu_has_mips_r2_exec_hazard)
|
||||||
|
uasm_i_ehb(&p);
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Examine entrylo 0 or 1 based on ptr. */
|
/* Examine entrylo 0 or 1 based on ptr. */
|
||||||
@ -2236,15 +2233,14 @@ static void build_r4000_tlb_load_handler(void)
|
|||||||
uasm_i_tlbr(&p);
|
uasm_i_tlbr(&p);
|
||||||
|
|
||||||
switch (current_cpu_type()) {
|
switch (current_cpu_type()) {
|
||||||
default:
|
|
||||||
if (cpu_has_mips_r2_exec_hazard) {
|
|
||||||
uasm_i_ehb(&p);
|
|
||||||
|
|
||||||
case CPU_CAVIUM_OCTEON:
|
case CPU_CAVIUM_OCTEON:
|
||||||
case CPU_CAVIUM_OCTEON_PLUS:
|
case CPU_CAVIUM_OCTEON_PLUS:
|
||||||
case CPU_CAVIUM_OCTEON2:
|
case CPU_CAVIUM_OCTEON2:
|
||||||
break;
|
break;
|
||||||
}
|
default:
|
||||||
|
if (cpu_has_mips_r2_exec_hazard)
|
||||||
|
uasm_i_ehb(&p);
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Examine entrylo 0 or 1 based on ptr. */
|
/* Examine entrylo 0 or 1 based on ptr. */
|
||||||
|
|||||||
@ -6,7 +6,6 @@
|
|||||||
# Copyright (C) 2008 Wind River Systems, Inc.
|
# Copyright (C) 2008 Wind River Systems, Inc.
|
||||||
# written by Ralf Baechle <ralf@linux-mips.org>
|
# written by Ralf Baechle <ralf@linux-mips.org>
|
||||||
#
|
#
|
||||||
obj-y += malta-dt.o
|
|
||||||
obj-y += malta-dtshim.o
|
obj-y += malta-dtshim.o
|
||||||
obj-y += malta-init.o
|
obj-y += malta-init.o
|
||||||
obj-y += malta-int.o
|
obj-y += malta-int.o
|
||||||
|
|||||||
@ -1,15 +0,0 @@
|
|||||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
||||||
/*
|
|
||||||
* Copyright (C) 2015 Imagination Technologies
|
|
||||||
* Author: Paul Burton <paul.burton@mips.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <linux/clk-provider.h>
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/of_fdt.h>
|
|
||||||
#include <linux/of_platform.h>
|
|
||||||
|
|
||||||
void __init device_tree_init(void)
|
|
||||||
{
|
|
||||||
unflatten_and_copy_device_tree();
|
|
||||||
}
|
|
||||||
@ -13,7 +13,6 @@ obj-$(CONFIG_PCI_DRIVERS_GENERIC)+= pci-generic.o
|
|||||||
obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
|
obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
|
||||||
obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
|
obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
|
||||||
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
|
obj-$(CONFIG_MIPS_MSC) += ops-msc.o
|
||||||
obj-$(CONFIG_SOC_TX3927) += ops-tx3927.o
|
|
||||||
obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
|
obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
|
||||||
obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
|
obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
|
||||||
obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
|
obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
|
||||||
@ -46,7 +45,6 @@ obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
|
|||||||
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
|
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
|
||||||
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
|
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
|
||||||
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
|
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
|
||||||
obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o
|
|
||||||
obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
|
obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
|
||||||
obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
|
obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
|
||||||
obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
|
obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
|
||||||
|
|||||||
@ -1,79 +0,0 @@
|
|||||||
/*
|
|
||||||
*
|
|
||||||
* BRIEF MODULE DESCRIPTION
|
|
||||||
* Board specific pci fixups.
|
|
||||||
*
|
|
||||||
* Copyright 2001 MontaVista Software Inc.
|
|
||||||
* Author: MontaVista Software, Inc.
|
|
||||||
* ppopov@mvista.com or source@mvista.com
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
|
||||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
||||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
||||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along
|
|
||||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
||||||
*/
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <asm/txx9/pci.h>
|
|
||||||
#include <asm/txx9/jmr3927.h>
|
|
||||||
|
|
||||||
int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
|
||||||
{
|
|
||||||
unsigned char irq = pin;
|
|
||||||
|
|
||||||
/* IRQ rotation (PICMG) */
|
|
||||||
irq--; /* 0-3 */
|
|
||||||
if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
|
|
||||||
/* PCI CardSlot (IDSEL=A23, DevNu=12) */
|
|
||||||
/* PCIA => PCIC (IDSEL=A23) */
|
|
||||||
/* NOTE: JMR3927 JP1 must be set to OPEN */
|
|
||||||
irq = (irq + 2) % 4;
|
|
||||||
} else if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
|
|
||||||
/* PCI CardSlot (IDSEL=A22, DevNu=11) */
|
|
||||||
/* PCIA => PCIA (IDSEL=A22) */
|
|
||||||
/* NOTE: JMR3927 JP1 must be set to OPEN */
|
|
||||||
irq = (irq + 0) % 4;
|
|
||||||
} else {
|
|
||||||
/* PCI Backplane */
|
|
||||||
if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
|
|
||||||
irq = (irq + 33 - slot) % 4;
|
|
||||||
else
|
|
||||||
irq = (irq + 3 + slot) % 4;
|
|
||||||
}
|
|
||||||
irq++; /* 1-4 */
|
|
||||||
|
|
||||||
switch (irq) {
|
|
||||||
case 1:
|
|
||||||
irq = JMR3927_IRQ_IOC_PCIA;
|
|
||||||
break;
|
|
||||||
case 2:
|
|
||||||
irq = JMR3927_IRQ_IOC_PCIB;
|
|
||||||
break;
|
|
||||||
case 3:
|
|
||||||
irq = JMR3927_IRQ_IOC_PCIC;
|
|
||||||
break;
|
|
||||||
case 4:
|
|
||||||
irq = JMR3927_IRQ_IOC_PCID;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Check OnBoard Ethernet (IDSEL=A24, DevNu=13) */
|
|
||||||
if (dev->bus->parent == NULL &&
|
|
||||||
slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(24))
|
|
||||||
irq = JMR3927_IRQ_ETHER0;
|
|
||||||
return irq;
|
|
||||||
}
|
|
||||||
@ -1,231 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright 2001 MontaVista Software Inc.
|
|
||||||
* Author: MontaVista Software, Inc.
|
|
||||||
* ahennessy@mvista.com
|
|
||||||
*
|
|
||||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
|
||||||
* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
|
|
||||||
*
|
|
||||||
* Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
|
|
||||||
*
|
|
||||||
* Define the pci_ops for TX3927.
|
|
||||||
*
|
|
||||||
* Much of the code is derived from the original DDB5074 port by
|
|
||||||
* Geert Uytterhoeven <geert@linux-m68k.org>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the
|
|
||||||
* Free Software Foundation; either version 2 of the License, or (at your
|
|
||||||
* option) any later version.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
|
||||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
|
||||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
|
||||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
|
||||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
|
||||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
|
||||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along
|
|
||||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
|
||||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
|
||||||
*/
|
|
||||||
#include <linux/types.h>
|
|
||||||
#include <linux/pci.h>
|
|
||||||
#include <linux/kernel.h>
|
|
||||||
#include <linux/init.h>
|
|
||||||
#include <linux/interrupt.h>
|
|
||||||
#include <linux/irq.h>
|
|
||||||
|
|
||||||
#include <asm/addrspace.h>
|
|
||||||
#include <asm/txx9irq.h>
|
|
||||||
#include <asm/txx9/pci.h>
|
|
||||||
#include <asm/txx9/tx3927.h>
|
|
||||||
|
|
||||||
static int mkaddr(struct pci_bus *bus, unsigned char devfn, unsigned char where)
|
|
||||||
{
|
|
||||||
if (bus->parent == NULL &&
|
|
||||||
devfn >= PCI_DEVFN(TX3927_PCIC_MAX_DEVNU, 0))
|
|
||||||
return -1;
|
|
||||||
tx3927_pcicptr->ica =
|
|
||||||
((bus->number & 0xff) << 0x10) |
|
|
||||||
((devfn & 0xff) << 0x08) |
|
|
||||||
(where & 0xfc) | (bus->parent ? 1 : 0);
|
|
||||||
|
|
||||||
/* clear M_ABORT and Disable M_ABORT Int. */
|
|
||||||
tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
|
|
||||||
tx3927_pcicptr->pcistatim &= ~PCI_STATUS_REC_MASTER_ABORT;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int check_abort(void)
|
|
||||||
{
|
|
||||||
if (tx3927_pcicptr->pcistat & PCI_STATUS_REC_MASTER_ABORT) {
|
|
||||||
tx3927_pcicptr->pcistat |= PCI_STATUS_REC_MASTER_ABORT;
|
|
||||||
tx3927_pcicptr->pcistatim |= PCI_STATUS_REC_MASTER_ABORT;
|
|
||||||
/* flush write buffer */
|
|
||||||
iob();
|
|
||||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
||||||
}
|
|
||||||
return PCIBIOS_SUCCESSFUL;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
|
|
||||||
int where, int size, u32 * val)
|
|
||||||
{
|
|
||||||
if (mkaddr(bus, devfn, where)) {
|
|
||||||
*val = 0xffffffff;
|
|
||||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (size) {
|
|
||||||
case 1:
|
|
||||||
*val = *(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3));
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 2:
|
|
||||||
*val = le16_to_cpu(*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)));
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 4:
|
|
||||||
*val = le32_to_cpu(tx3927_pcicptr->icd);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return check_abort();
|
|
||||||
}
|
|
||||||
|
|
||||||
static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
|
|
||||||
int where, int size, u32 val)
|
|
||||||
{
|
|
||||||
if (mkaddr(bus, devfn, where))
|
|
||||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
||||||
|
|
||||||
switch (size) {
|
|
||||||
case 1:
|
|
||||||
*(volatile u8 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 3)) = val;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 2:
|
|
||||||
*(volatile u16 *) ((unsigned long) & tx3927_pcicptr->icd | (where & 2)) =
|
|
||||||
cpu_to_le16(val);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case 4:
|
|
||||||
tx3927_pcicptr->icd = cpu_to_le32(val);
|
|
||||||
}
|
|
||||||
|
|
||||||
return check_abort();
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct pci_ops tx3927_pci_ops = {
|
|
||||||
.read = tx3927_pci_read_config,
|
|
||||||
.write = tx3927_pci_write_config,
|
|
||||||
};
|
|
||||||
|
|
||||||
void __init tx3927_pcic_setup(struct pci_controller *channel,
|
|
||||||
unsigned long sdram_size, int extarb)
|
|
||||||
{
|
|
||||||
unsigned long flags;
|
|
||||||
unsigned long io_base =
|
|
||||||
channel->io_resource->start + mips_io_port_base - IO_BASE;
|
|
||||||
unsigned long io_size =
|
|
||||||
channel->io_resource->end - channel->io_resource->start;
|
|
||||||
unsigned long io_pciaddr =
|
|
||||||
channel->io_resource->start - channel->io_offset;
|
|
||||||
unsigned long mem_base =
|
|
||||||
channel->mem_resource->start;
|
|
||||||
unsigned long mem_size =
|
|
||||||
channel->mem_resource->end - channel->mem_resource->start;
|
|
||||||
unsigned long mem_pciaddr =
|
|
||||||
channel->mem_resource->start - channel->mem_offset;
|
|
||||||
|
|
||||||
printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s",
|
|
||||||
tx3927_pcicptr->did, tx3927_pcicptr->vid,
|
|
||||||
tx3927_pcicptr->rid,
|
|
||||||
extarb ? "External" : "Internal");
|
|
||||||
channel->pci_ops = &tx3927_pci_ops;
|
|
||||||
|
|
||||||
local_irq_save(flags);
|
|
||||||
/* Disable External PCI Config. Access */
|
|
||||||
tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
|
|
||||||
#ifdef __BIG_ENDIAN
|
|
||||||
tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
|
|
||||||
TX3927_PCIC_LBC_TIBSE |
|
|
||||||
TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
|
|
||||||
#endif
|
|
||||||
/* LB->PCI mappings */
|
|
||||||
tx3927_pcicptr->iomas = ~(io_size - 1);
|
|
||||||
tx3927_pcicptr->ilbioma = io_base;
|
|
||||||
tx3927_pcicptr->ipbioma = io_pciaddr;
|
|
||||||
tx3927_pcicptr->mmas = ~(mem_size - 1);
|
|
||||||
tx3927_pcicptr->ilbmma = mem_base;
|
|
||||||
tx3927_pcicptr->ipbmma = mem_pciaddr;
|
|
||||||
/* PCI->LB mappings */
|
|
||||||
tx3927_pcicptr->iobas = 0xffffffff;
|
|
||||||
tx3927_pcicptr->ioba = 0;
|
|
||||||
tx3927_pcicptr->tlbioma = 0;
|
|
||||||
tx3927_pcicptr->mbas = ~(sdram_size - 1);
|
|
||||||
tx3927_pcicptr->mba = 0;
|
|
||||||
tx3927_pcicptr->tlbmma = 0;
|
|
||||||
/* Enable Direct mapping Address Space Decoder */
|
|
||||||
tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
|
|
||||||
|
|
||||||
/* Clear All Local Bus Status */
|
|
||||||
tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
|
|
||||||
/* Enable All Local Bus Interrupts */
|
|
||||||
tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
|
|
||||||
/* Clear All PCI Status Error */
|
|
||||||
tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
|
|
||||||
/* Enable All PCI Status Error Interrupts */
|
|
||||||
tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
|
|
||||||
|
|
||||||
/* PCIC Int => IRC IRQ10 */
|
|
||||||
tx3927_pcicptr->il = TX3927_IR_PCI;
|
|
||||||
/* Target Control (per errata) */
|
|
||||||
tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
|
|
||||||
|
|
||||||
/* Enable Bus Arbiter */
|
|
||||||
if (!extarb)
|
|
||||||
tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
|
|
||||||
|
|
||||||
tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
|
|
||||||
PCI_COMMAND_MEMORY |
|
|
||||||
PCI_COMMAND_IO |
|
|
||||||
PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
|
|
||||||
local_irq_restore(flags);
|
|
||||||
}
|
|
||||||
|
|
||||||
static irqreturn_t tx3927_pcierr_interrupt(int irq, void *dev_id)
|
|
||||||
{
|
|
||||||
struct pt_regs *regs = get_irq_regs();
|
|
||||||
|
|
||||||
if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
|
|
||||||
printk(KERN_WARNING "PCI error interrupt at 0x%08lx.\n",
|
|
||||||
regs->cp0_epc);
|
|
||||||
printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
|
|
||||||
tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
|
|
||||||
}
|
|
||||||
if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
|
|
||||||
/* clear all pci errors */
|
|
||||||
tx3927_pcicptr->pcistat |= TX3927_PCIC_PCISTATIM_ALL;
|
|
||||||
tx3927_pcicptr->istat = TX3927_PCIC_IIM_ALL;
|
|
||||||
tx3927_pcicptr->tstat = TX3927_PCIC_TIM_ALL;
|
|
||||||
tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
|
|
||||||
return IRQ_HANDLED;
|
|
||||||
}
|
|
||||||
console_verbose();
|
|
||||||
panic("PCI error.");
|
|
||||||
}
|
|
||||||
|
|
||||||
void __init tx3927_setup_pcierr_irq(void)
|
|
||||||
{
|
|
||||||
if (request_irq(TXX9_IRQ_BASE + TX3927_IR_PCI,
|
|
||||||
tx3927_pcierr_interrupt,
|
|
||||||
0, "PCI error",
|
|
||||||
(void *)TX3927_PCIC_REG))
|
|
||||||
printk(KERN_WARNING "Failed to request irq for PCIERR\n");
|
|
||||||
}
|
|
||||||
@ -384,7 +384,7 @@ static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_domain_ops ar2315_pci_irq_domain_ops = {
|
static const struct irq_domain_ops ar2315_pci_irq_domain_ops = {
|
||||||
.map = ar2315_pci_irq_map,
|
.map = ar2315_pci_irq_map,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -78,14 +78,6 @@ void __init prom_init(void)
|
|||||||
pic32_init_cmdline((int)fw_arg0, (char **)fw_arg1);
|
pic32_init_cmdline((int)fw_arg0, (char **)fw_arg1);
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init device_tree_init(void)
|
|
||||||
{
|
|
||||||
if (!initial_boot_params)
|
|
||||||
return;
|
|
||||||
|
|
||||||
unflatten_and_copy_device_tree();
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct pic32_sdhci_platform_data sdhci_data = {
|
static struct pic32_sdhci_platform_data sdhci_data = {
|
||||||
.setup_dma = pic32_set_sdhci_adma_fifo_threshold,
|
.setup_dma = pic32_set_sdhci_adma_fifo_threshold,
|
||||||
};
|
};
|
||||||
|
|||||||
@ -61,6 +61,7 @@ static int __init ill_acc_of_setup(void)
|
|||||||
pdev = of_find_device_by_node(np);
|
pdev = of_find_device_by_node(np);
|
||||||
if (!pdev) {
|
if (!pdev) {
|
||||||
pr_err("%pOFn: failed to lookup pdev\n", np);
|
pr_err("%pOFn: failed to lookup pdev\n", np);
|
||||||
|
of_node_put(np);
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
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Reference in New Issue
Block a user