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ARM: 9263/1: use .arch directives instead of assembler command line flags

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Similar to commit a6c30873ee ("ARM: 8989/1: use .fpu assembler
directives instead of assembler arguments").

GCC and GNU binutils support setting the "sub arch" via -march=,
-Wa,-march, target function attribute, and .arch assembler directive.

Clang was missing support for -Wa,-march=, but this was implemented in
clang-13.

The behavior of both GCC and Clang is to
prefer -Wa,-march= over -march= for assembler and assembler-with-cpp
sources, but Clang will warn about the -march= being unused.

clang: warning: argument unused during compilation: '-march=armv6k'
[-Wunused-command-line-argument]

Since most assembler is non-conditionally assembled with one sub arch
(modulo arch/arm/delay-loop.S which conditionally is assembled as armv4
based on CONFIG_ARCH_RPC, and arch/arm/mach-at91/pm-suspend.S which is
conditionally assembled as armv7-a based on CONFIG_CPU_V7), prefer the
.arch assembler directive.

Add a few more instances found in compile testing as found by Arnd and
Nathan.

Link: 1d51c699b9
Link: https://bugs.llvm.org/show_bug.cgi?id=48894
Link: https://github.com/ClangBuiltLinux/linux/issues/1195
Link: https://github.com/ClangBuiltLinux/linux/issues/1315

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Suggested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Nick Desaulniers 2022-10-24 20:44:41 +01:00 committed by Russell King (Oracle)
parent 5aa4860eb5
commit a2faac3986
41 changed files with 54 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/compressed/Makefile
View File

@ -164,4 +164,3 @@ $(obj)/piggy_data: $(obj)/../Image FORCE
$(obj)/piggy.o: $(obj)/piggy_data
CFLAGS_font.o := -Dstatic=
AFLAGS_hyp-stub.o := -Wa,-march=armv7-a

2
arch/arm/common/Makefile
View File

@ -13,7 +13,5 @@ obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_CPU_V7) += secure_cntvoff.o
obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
CFLAGS_REMOVE_mcpm_entry.o = -pg
AFLAGS_mcpm_head.o := -march=armv7-a
AFLAGS_vlock.o := -march=armv7-a
obj-$(CONFIG_BL_SWITCHER) += bL_switcher.o
obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) += bL_switcher_dummy_if.o

2
arch/arm/common/mcpm_head.S
View File

@ -15,6 +15,8 @@
#include "vlock.h"
.arch armv7-a
.if MCPM_SYNC_CLUSTER_CPUS
.error "cpus must be the first member of struct mcpm_sync_struct"
.endif

2
arch/arm/common/vlock.S
View File

@ -12,6 +12,8 @@
#include <linux/linkage.h>
#include "vlock.h"
.arch armv7-a
/* Select different code if voting flags can fit in a single word. */
#if VLOCK_VOTING_SIZE > 4
#define FEW(x...)

2
arch/arm/kernel/Makefile
View File

@ -71,7 +71,6 @@ obj-$(CONFIG_HAVE_TCM) += tcm.o
obj-$(CONFIG_OF) += devtree.o
obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_SWP_EMULATE) += swp_emulate.o
CFLAGS_swp_emulate.o := -Wa,-march=armv7-a
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
@ -100,7 +99,6 @@ CFLAGS_head-inflate-data.o := $(call cc-option,-Wframe-larger-than=10240)
obj-$(CONFIG_XIP_DEFLATED_DATA) += head-inflate-data.o
obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o
AFLAGS_hyp-stub.o :=-Wa,-march=armv7-a
ifeq ($(CONFIG_ARM_PSCI),y)
obj-$(CONFIG_SMP) += psci_smp.o
endif

2
arch/arm/kernel/hyp-stub.S
View File

@ -9,6 +9,8 @@
#include <asm/assembler.h>
#include <asm/virt.h>
.arch armv7-a
#ifndef ZIMAGE
/*
* For the kernel proper, we need to find out the CPU boot mode long after

1
arch/arm/kernel/swp_emulate.c
View File

@ -34,6 +34,7 @@
*/
#define __user_swpX_asm(data, addr, res, temp, B) \
__asm__ __volatile__( \
".arch armv7-a\n" \
"0: ldrex"B" %2, [%3]\n" \
"1: strex"B" %0, %1, [%3]\n" \
" cmp %0, #0\n" \

4
arch/arm/lib/Makefile
View File

@ -36,10 +36,6 @@ else
lib-y += io-readsw-armv4.o io-writesw-armv4.o
endif
ifeq ($(CONFIG_ARCH_RPC),y)
AFLAGS_delay-loop.o += -march=armv4
endif
$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S
$(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S

4
arch/arm/lib/delay-loop.S
View File

@ -8,6 +8,10 @@
#include <asm/assembler.h>
#include <asm/delay.h>
#ifdef CONFIG_ARCH_RPC
.arch armv4
#endif
.text
.LC0: .word loops_per_jiffy

3
arch/arm/mach-at91/Makefile
View File

@ -14,9 +14,6 @@ obj-$(CONFIG_SOC_SAMV7) += samv7.o
# Power Management
obj-$(CONFIG_ATMEL_PM) += pm.o pm_suspend.o
ifeq ($(CONFIG_CPU_V7),y)
AFLAGS_pm_suspend.o := -march=armv7-a
endif
ifeq ($(CONFIG_PM_DEBUG),y)
CFLAGS_pm.o += -DDEBUG
endif

4
arch/arm/mach-at91/pm_suspend.S
View File

@ -12,6 +12,10 @@
#include "pm.h"
#include "pm_data-offsets.h"
#ifdef CONFIG_CPU_V7
.arch armv7-a
#endif
#define SRAMC_SELF_FRESH_ACTIVE 0x01
#define SRAMC_SELF_FRESH_EXIT 0x00

3
arch/arm/mach-imx/Makefile
View File

@ -34,7 +34,6 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7D_CA7)$(CONFIG_SOC_LS1021A),)
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
endif
@ -48,12 +47,10 @@ obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
ifeq ($(CONFIG_SUSPEND),y)
AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
obj-$(CONFIG_SOC_IMX53) += suspend-imx53.o
endif
ifeq ($(CONFIG_ARM_CPU_SUSPEND),y)
AFLAGS_resume-imx6.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SOC_IMX6) += resume-imx6.o
endif
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o

2
arch/arm/mach-imx/headsmp.S
View File

@ -8,6 +8,8 @@
#include <linux/init.h>
#include <asm/assembler.h>
.arch armv7-a
diag_reg_offset:
.word g_diag_reg - .

2
arch/arm/mach-imx/resume-imx6.S
View File

@ -9,6 +9,8 @@
#include <asm/hardware/cache-l2x0.h>
#include "hardware.h"
.arch armv7-a
/*
* The following code must assume it is running from physical address
* where absolute virtual addresses to the data section have to be

2
arch/arm/mach-imx/suspend-imx6.S
View File

@ -9,6 +9,8 @@
#include <asm/hardware/cache-l2x0.h>
#include "hardware.h"
.arch armv7-a
/*
* ==================== low level suspend ====================
*

3
arch/arm/mach-mvebu/Makefile
View File

@ -1,9 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/plat-orion/include
AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
CFLAGS_pmsu.o := -march=armv7-a
obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o
ifeq ($(CONFIG_MACH_MVEBU_V7),y)

1
arch/arm/mach-mvebu/coherency_ll.S
View File

@ -20,6 +20,7 @@
#include <asm/assembler.h>
#include <asm/cp15.h>
.arch armv7-a
.text
/*
* Returns the coherency base address in r1 (r0 is untouched), or 0 if

1
arch/arm/mach-mvebu/pmsu.c
View File

@ -291,6 +291,7 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
/* Test the CR_C bit and set it if it was cleared */
asm volatile(
".arch armv7-a\n\t"
"mrc p15, 0, r0, c1, c0, 0 \n\t"
"tst r0, %0 \n\t"
"orreq r0, r0, #(1 << 2) \n\t"

2
arch/arm/mach-npcm/Makefile
View File

@ -1,6 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
AFLAGS_headsmp.o += -march=armv7-a
obj-$(CONFIG_ARCH_WPCM450) += wpcm450.o
obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o

2
arch/arm/mach-npcm/headsmp.S
View File

@ -6,6 +6,8 @@
#include <linux/init.h>
#include <asm/assembler.h>
.arch armv7-a
/*
* The boot ROM does not start secondary CPUs in SVC mode, so we need to do that
* here.

2
arch/arm/mach-tegra/Makefile
View File

@ -1,6 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
asflags-y += -march=armv7-a
obj-y += io.o
obj-y += irq.o
obj-y += pm.o

2
arch/arm/mach-tegra/reset-handler.S
View File

@ -19,6 +19,8 @@
#define PMC_SCRATCH41 0x140
.arch armv7-a
#ifdef CONFIG_PM_SLEEP
/*
* tegra_resume

2
arch/arm/mach-tegra/sleep-tegra20.S
View File

@ -47,6 +47,8 @@
#define PLLM_STORE_MASK (1 << 1)
#define PLLP_STORE_MASK (1 << 2)
.arch armv7-a
.macro test_pll_state, rd, test_mask
ldr \rd, tegra_pll_state
tst \rd, #\test_mask

2
arch/arm/mach-tegra/sleep-tegra30.S
View File

@ -78,6 +78,8 @@
#define PLLX_STORE_MASK (1 << 4)
#define PLLM_PMC_STORE_MASK (1 << 5)
.arch armv7-a
.macro emc_device_mask, rd, base
ldr \rd, [\base, #EMC_ADR_CFG]
tst \rd, #0x1

2
arch/arm/mach-tegra/sleep.S
View File

@ -22,6 +22,8 @@
#define CLK_RESET_CCLK_BURST 0x20
#define CLK_RESET_CCLK_DIVIDER 0x24
.arch armv7-a
#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
/*
* tegra_disable_clean_inv_dcache

15
arch/arm/mm/Makefile
View File

@ -33,9 +33,6 @@ obj-$(CONFIG_CPU_ABRT_EV5TJ) += abort-ev5tj.o
obj-$(CONFIG_CPU_ABRT_EV6) += abort-ev6.o
obj-$(CONFIG_CPU_ABRT_EV7) += abort-ev7.o
AFLAGS_abort-ev6.o :=-Wa,-march=armv6k
AFLAGS_abort-ev7.o :=-Wa,-march=armv7-a
obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o
obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o
obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o
@ -49,10 +46,6 @@ obj-$(CONFIG_CPU_CACHE_FA) += cache-fa.o
obj-$(CONFIG_CPU_CACHE_NOP) += cache-nop.o
obj-$(CONFIG_CPU_CACHE_V7M) += cache-v7m.o
AFLAGS_cache-v6.o :=-Wa,-march=armv6
AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
AFLAGS_cache-v7m.o :=-Wa,-march=armv7-m
obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o
obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o
obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o
@ -62,8 +55,6 @@ obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o
obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o
CFLAGS_copypage-feroceon.o := -march=armv5te
obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o
obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o
@ -72,9 +63,6 @@ obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o
obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o
obj-$(CONFIG_CPU_TLB_FA) += tlb-fa.o
AFLAGS_tlb-v6.o :=-Wa,-march=armv6
AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a
obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o
obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o
obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o
@ -101,9 +89,6 @@ obj-$(CONFIG_CPU_V6K) += proc-v6.o
obj-$(CONFIG_CPU_V7) += proc-v7.o proc-v7-bugs.o
obj-$(CONFIG_CPU_V7M) += proc-v7m.o
AFLAGS_proc-v6.o :=-Wa,-march=armv6
AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
obj-$(CONFIG_OUTER_CACHE) += l2c-common.o
obj-$(CONFIG_CACHE_B15_RAC) += cache-b15-rac.o
obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o

1
arch/arm/mm/abort-ev6.S
View File

@ -16,6 +16,7 @@
* abort here if the I-TLB and D-TLB aren't seeing the same
* picture. Unfortunately, this does happen. We live with it.
*/
.arch armv6k
.align 5
ENTRY(v6_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR

1
arch/arm/mm/abort-ev7.S
View File

@ -12,6 +12,7 @@
*
* Purpose : obtain information about current aborted instruction.
*/
.arch armv7-a
.align 5
ENTRY(v7_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR

2
arch/arm/mm/cache-v6.S
View File

@ -19,6 +19,8 @@
#define D_CACHE_LINE_SIZE 32
#define BTB_FLUSH_SIZE 8
.arch armv6
/*
* v6_flush_icache_all()
*

2
arch/arm/mm/cache-v7.S
View File

@ -16,6 +16,8 @@
#include "proc-macros.S"
.arch armv7-a
#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
.globl icache_size
.data

2
arch/arm/mm/cache-v7m.S
View File

@ -18,6 +18,8 @@
#include "proc-macros.S"
.arch armv7-m
/* Generic V7M read/write macros for memory mapped cache operations */
.macro v7m_cache_read, rt, reg
movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg

1
arch/arm/mm/copypage-feroceon.c
View File

@ -15,6 +15,7 @@ static void feroceon_copy_user_page(void *kto, const void *kfrom)
int tmp;
asm volatile ("\
.arch armv5te \n\
1: ldmia %1!, {r2 - r7, ip, lr} \n\
pld [%1, #0] \n\
pld [%1, #32] \n\

2
arch/arm/mm/proc-v6.S
View File

@ -32,6 +32,8 @@
#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
.arch armv6
ENTRY(cpu_v6_proc_init)
ret lr

2
arch/arm/mm/proc-v7-2level.S
View File

@ -24,6 +24,8 @@
#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
.arch armv7-a
/*
* cpu_v7_switch_mm(pgd_phys, tsk)
*

2
arch/arm/mm/proc-v7.S
View File

@ -24,6 +24,8 @@
#include "proc-v7-2level.S"
#endif
.arch armv7-a
ENTRY(cpu_v7_proc_init)
ret lr
ENDPROC(cpu_v7_proc_init)

2
arch/arm/mm/tlb-v6.S
View File

@ -17,6 +17,8 @@
#define HARVARD_TLB
.arch armv6
/*
* v6wbi_flush_user_tlb_range(start, end, vma)
*

2
arch/arm/mm/tlb-v7.S
View File

@ -16,6 +16,8 @@
#include <asm/tlbflush.h>
#include "proc-macros.S"
.arch armv7-a
/*
* v7wbi_flush_user_tlb_range(start, end, vma)
*

2
drivers/memory/Makefile
View File

@ -32,8 +32,6 @@ obj-$(CONFIG_FPGA_DFL_EMIF) += dfl-emif.o
ti-emif-sram-objs := ti-emif-pm.o ti-emif-sram-pm.o
AFLAGS_ti-emif-sram-pm.o :=-Wa,-march=armv7-a
$(obj)/ti-emif-sram-pm.o: $(obj)/ti-emif-asm-offsets.h
$(obj)/ti-emif-asm-offsets.h: $(obj)/emif-asm-offsets.s FORCE

1
drivers/memory/ti-emif-sram-pm.S
View File

@ -28,6 +28,7 @@
.arm
.align 3
.arch armv7-a
ENTRY(ti_emif_sram)

1
drivers/soc/bcm/brcmstb/pm/Makefile
View File

@ -1,4 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_ARM) += s2-arm.o pm-arm.o
AFLAGS_s2-arm.o := -march=armv7-a
obj-$(CONFIG_BMIPS_GENERIC) += s2-mips.o s3-mips.o pm-mips.o

1
drivers/soc/bcm/brcmstb/pm/s2-arm.S
View File

@ -8,6 +8,7 @@
#include "pm.h"
.arch armv7-a
.text
.align 3