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interconnect: qcom: sm8650: Use correct ACV enable_mask

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The ACV enable_mask is historically BIT(3), but it's BIT(0) on this
target. Fix it.

Fixes: c062bcab5924 ("interconnect: qcom: introduce RPMh Network-On-Chip Interconnect on SM8650 SoC")
Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240202014806.7876-2-quic_mdtipton@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Mike Tipton 2024-02-01 17:48:05 -08:00 committed by Georgi Djakov
parent 24406f6794
commit a40f93e928
1 changed files with 1 additions and 1 deletions
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2
drivers/interconnect/qcom/sm8650.c
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@ -1160,7 +1160,7 @@ static struct qcom_icc_node qns_gemnoc_sf = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.enable_mask = BIT(3),
.enable_mask = BIT(0),
.num_nodes = 1,
.nodes = { &ebi },
};