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media: chips-media: wave5: drop "sram-size" DT property

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Move the excessive "sram-size" device-tree property to the device match
data. Also change the SRAM memory allocation strategy, instead of
allocating exactly sram_size bytes, allocate all available SRAM memory
up to sram_size. Add the placeholders wave5_vpu_dec_validate_sec_axi()
and wave5_vpu_enc_validate_sec_axi() to validate that the allocated SRAM
memory is sufficient to decode/encode bitstream with a given resolution.

Signed-off-by: Ivan Bornyakov <brnkv.i1@gmail.com>
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
This commit is contained in:
Ivan Bornyakov 2024-04-15 13:07:22 +03:00 committed by Hans Verkuil
parent 749476d44d
commit a83d4a689e
3 changed files with 72 additions and 22 deletions
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62
drivers/media/platform/chips-media/wave5/wave5-hw.c
View File

@ -843,6 +843,36 @@ free_mv_buffers:
return ret;
}
static u32 wave5_vpu_dec_validate_sec_axi(struct vpu_instance *inst)
{
struct dec_info *p_dec_info = &inst->codec_info->dec_info;
u32 bit_size = 0, ip_size = 0, lf_size = 0, ret = 0;
u32 sram_size = inst->dev->sram_size;
if (!sram_size)
return 0;
/*
* TODO: calculate bit_size, ip_size, lf_size from inst->src_fmt.width
* and inst->codec_info->dec_info.initial_info.luma_bitdepth
*/
if (p_dec_info->sec_axi_info.use_bit_enable && sram_size >= bit_size) {
ret |= BIT(0);
sram_size -= bit_size;
}
if (p_dec_info->sec_axi_info.use_ip_enable && sram_size >= ip_size) {
ret |= BIT(9);
sram_size -= ip_size;
}
if (p_dec_info->sec_axi_info.use_lf_row_enable && sram_size >= lf_size)
ret |= BIT(15);
return ret;
}
int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res)
{
u32 reg_val;
@ -855,9 +885,7 @@ int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res)
vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info));
/* secondary AXI */
reg_val = p_dec_info->sec_axi_info.use_bit_enable |
(p_dec_info->sec_axi_info.use_ip_enable << 9) |
(p_dec_info->sec_axi_info.use_lf_row_enable << 15);
reg_val = wave5_vpu_dec_validate_sec_axi(inst);
vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val);
/* set attributes of user buffer */
@ -1938,6 +1966,31 @@ free_vb_fbc_y_tbl:
return ret;
}
static u32 wave5_vpu_enc_validate_sec_axi(struct vpu_instance *inst)
{
struct enc_info *p_enc_info = &inst->codec_info->enc_info;
u32 rdo_size = 0, lf_size = 0, ret = 0;
u32 sram_size = inst->dev->sram_size;
if (!sram_size)
return 0;
/*
* TODO: calculate rdo_size and lf_size from inst->src_fmt.width and
* inst->codec_info->enc_info.open_param.wave_param.internal_bit_depth
*/
if (p_enc_info->sec_axi_info.use_enc_rdo_enable && sram_size >= rdo_size) {
ret |= BIT(11);
sram_size -= rdo_size;
}
if (p_enc_info->sec_axi_info.use_enc_lf_enable && sram_size >= lf_size)
ret |= BIT(15);
return ret;
}
int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res)
{
u32 src_frame_format;
@ -1959,8 +2012,7 @@ int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *f
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI);
/* secondary AXI */
reg_val = (p_enc_info->sec_axi_info.use_enc_rdo_enable << 11) |
(p_enc_info->sec_axi_info.use_enc_lf_enable << 15);
reg_val = wave5_vpu_enc_validate_sec_axi(inst);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val);
vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0);

21
drivers/media/platform/chips-media/wave5/wave5-vdi.c
View File

@ -174,16 +174,19 @@ int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array,
void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev)
{
struct vpu_buf *vb = &vpu_dev->sram_buf;
dma_addr_t daddr;
void *vaddr;
size_t size;
if (!vpu_dev->sram_pool || !vpu_dev->sram_size)
if (!vpu_dev->sram_pool || vb->vaddr)
return;
if (!vb->vaddr) {
vb->size = vpu_dev->sram_size;
vb->vaddr = gen_pool_dma_alloc(vpu_dev->sram_pool, vb->size,
&vb->daddr);
if (!vb->vaddr)
vb->size = 0;
size = min_t(size_t, vpu_dev->sram_size, gen_pool_avail(vpu_dev->sram_pool));
vaddr = gen_pool_dma_alloc(vpu_dev->sram_pool, size, &daddr);
if (vaddr) {
vb->vaddr = vaddr;
vb->daddr = daddr;
vb->size = size;
}
dev_dbg(vpu_dev->dev, "%s: sram daddr: %pad, size: %zu, vaddr: 0x%p\n",
@ -197,9 +200,7 @@ void wave5_vdi_free_sram(struct vpu_device *vpu_dev)
if (!vb->size || !vb->vaddr)
return;
if (vb->vaddr)
gen_pool_free(vpu_dev->sram_pool, (unsigned long)vb->vaddr,
vb->size);
gen_pool_free(vpu_dev->sram_pool, (unsigned long)vb->vaddr, vb->size);
memset(vb, 0, sizeof(*vb));
}

11
drivers/media/platform/chips-media/wave5/wave5-vpu.c
View File

@ -25,6 +25,7 @@
struct wave5_match_data {
int flags;
const char *fw_name;
u32 sram_size;
};
static int vpu_poll_interval = 5;
@ -205,17 +206,12 @@ static int wave5_vpu_probe(struct platform_device *pdev)
goto err_reset_assert;
}
ret = of_property_read_u32(pdev->dev.of_node, "sram-size",
&dev->sram_size);
if (ret) {
dev_warn(&pdev->dev, "sram-size not found\n");
dev->sram_size = 0;
}
dev->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0);
if (!dev->sram_pool)
dev_warn(&pdev->dev, "sram node not found\n");
dev->sram_size = match_data->sram_size;
dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER);
ret = wave5_vdi_init(&pdev->dev);
if (ret < 0) {
@ -322,6 +318,7 @@ static void wave5_vpu_remove(struct platform_device *pdev)
static const struct wave5_match_data ti_wave521c_data = {
.flags = WAVE5_IS_ENC | WAVE5_IS_DEC,
.fw_name = "cnm/wave521c_k3_codec_fw.bin",
.sram_size = (64 * 1024),
};
static const struct of_device_id wave5_dt_ids[] = {