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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-01-13 00:29:50 +00:00
dmaengine: PL08x: move private data structures into amba-pl08x.c
Move the driver private data structures into the driver itself, rather than having them exposed to everyone in a header file. Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
a8fb688e1d
commit
b23f204c8d
@ -90,6 +90,7 @@
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#define DRIVER_NAME "pl08xdmac"
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static struct amba_driver pl08x_amba_driver;
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struct pl08x_driver_data;
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/**
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* struct vendor_data - vendor-specific config parameters for PL08x derivatives
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@ -118,6 +119,141 @@ struct pl08x_lli {
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u32 cctl;
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};
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/**
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* struct pl08x_bus_data - information of source or destination
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* busses for a transfer
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* @addr: current address
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* @maxwidth: the maximum width of a transfer on this bus
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* @buswidth: the width of this bus in bytes: 1, 2 or 4
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*/
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struct pl08x_bus_data {
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dma_addr_t addr;
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u8 maxwidth;
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u8 buswidth;
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};
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/**
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* struct pl08x_phy_chan - holder for the physical channels
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* @id: physical index to this channel
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* @lock: a lock to use when altering an instance of this struct
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* @signal: the physical signal (aka channel) serving this physical channel
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* right now
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* @serving: the virtual channel currently being served by this physical
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* channel
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*/
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struct pl08x_phy_chan {
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unsigned int id;
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void __iomem *base;
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spinlock_t lock;
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int signal;
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struct pl08x_dma_chan *serving;
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};
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/**
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* struct pl08x_sg - structure containing data per sg
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* @src_addr: src address of sg
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* @dst_addr: dst address of sg
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* @len: transfer len in bytes
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* @node: node for txd's dsg_list
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*/
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struct pl08x_sg {
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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size_t len;
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struct list_head node;
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};
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/**
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* struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
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* @tx: async tx descriptor
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* @node: node for txd list for channels
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* @dsg_list: list of children sg's
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* @direction: direction of transfer
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* @llis_bus: DMA memory address (physical) start for the LLIs
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* @llis_va: virtual memory address start for the LLIs
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* @cctl: control reg values for current txd
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* @ccfg: config reg values for current txd
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*/
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struct pl08x_txd {
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struct dma_async_tx_descriptor tx;
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struct list_head node;
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struct list_head dsg_list;
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enum dma_transfer_direction direction;
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dma_addr_t llis_bus;
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struct pl08x_lli *llis_va;
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/* Default cctl value for LLIs */
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u32 cctl;
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/*
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* Settings to be put into the physical channel when we
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* trigger this txd. Other registers are in llis_va[0].
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*/
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u32 ccfg;
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};
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/**
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* struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
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* states
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* @PL08X_CHAN_IDLE: the channel is idle
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* @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
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* channel and is running a transfer on it
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* @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
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* channel, but the transfer is currently paused
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* @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
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* channel to become available (only pertains to memcpy channels)
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*/
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enum pl08x_dma_chan_state {
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PL08X_CHAN_IDLE,
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PL08X_CHAN_RUNNING,
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PL08X_CHAN_PAUSED,
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PL08X_CHAN_WAITING,
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};
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/**
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* struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
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* @chan: wrappped abstract channel
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* @phychan: the physical channel utilized by this channel, if there is one
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* @phychan_hold: if non-zero, hold on to the physical channel even if we
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* have no pending entries
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* @tasklet: tasklet scheduled by the IRQ to handle actual work etc
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* @name: name of channel
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* @cd: channel platform data
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* @runtime_addr: address for RX/TX according to the runtime config
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* @runtime_direction: current direction of this channel according to
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* runtime config
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* @pend_list: queued transactions pending on this channel
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* @at: active transaction on this channel
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* @lock: a lock for this channel data
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* @host: a pointer to the host (internal use)
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* @state: whether the channel is idle, paused, running etc
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* @slave: whether this channel is a device (slave) or for memcpy
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* @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
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* channels. Fill with 'true' if peripheral should be flow controller. Direction
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* will be selected at Runtime.
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* @waiting: a TX descriptor on this channel which is waiting for a physical
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* channel to become available
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*/
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struct pl08x_dma_chan {
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struct dma_chan chan;
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struct pl08x_phy_chan *phychan;
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int phychan_hold;
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struct tasklet_struct tasklet;
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char *name;
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const struct pl08x_channel_data *cd;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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u32 src_cctl;
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u32 dst_cctl;
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enum dma_transfer_direction runtime_direction;
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struct list_head pend_list;
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struct pl08x_txd *at;
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spinlock_t lock;
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struct pl08x_driver_data *host;
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enum pl08x_dma_chan_state state;
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bool slave;
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bool device_fc;
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struct pl08x_txd *waiting;
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};
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/**
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* struct pl08x_driver_data - the local state holder for the PL08x
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* @slave: slave engine for this instance
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@ -21,8 +21,9 @@
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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struct pl08x_lli;
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struct pl08x_driver_data;
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struct pl08x_phy_chan;
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struct pl08x_txd;
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/* Bitmasks for selecting AHB ports for DMA transfers */
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enum {
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@ -67,144 +68,6 @@ struct pl08x_channel_data {
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u8 periph_buses;
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};
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/**
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* Struct pl08x_bus_data - information of source or destination
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* busses for a transfer
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* @addr: current address
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* @maxwidth: the maximum width of a transfer on this bus
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* @buswidth: the width of this bus in bytes: 1, 2 or 4
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*/
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struct pl08x_bus_data {
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dma_addr_t addr;
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u8 maxwidth;
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u8 buswidth;
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};
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/**
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* struct pl08x_phy_chan - holder for the physical channels
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* @id: physical index to this channel
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* @lock: a lock to use when altering an instance of this struct
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* @signal: the physical signal (aka channel) serving this physical channel
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* right now
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* @serving: the virtual channel currently being served by this physical
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* channel
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* @locked: channel unavailable for the system, e.g. dedicated to secure
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* world
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*/
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struct pl08x_phy_chan {
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unsigned int id;
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void __iomem *base;
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spinlock_t lock;
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int signal;
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struct pl08x_dma_chan *serving;
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bool locked;
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};
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/**
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* struct pl08x_sg - structure containing data per sg
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* @src_addr: src address of sg
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* @dst_addr: dst address of sg
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* @len: transfer len in bytes
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* @node: node for txd's dsg_list
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*/
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struct pl08x_sg {
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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size_t len;
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struct list_head node;
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};
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/**
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* struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
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* @tx: async tx descriptor
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* @node: node for txd list for channels
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* @dsg_list: list of children sg's
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* @direction: direction of transfer
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* @llis_bus: DMA memory address (physical) start for the LLIs
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* @llis_va: virtual memory address start for the LLIs
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* @cctl: control reg values for current txd
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* @ccfg: config reg values for current txd
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*/
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struct pl08x_txd {
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struct dma_async_tx_descriptor tx;
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struct list_head node;
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struct list_head dsg_list;
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enum dma_transfer_direction direction;
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dma_addr_t llis_bus;
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struct pl08x_lli *llis_va;
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/* Default cctl value for LLIs */
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u32 cctl;
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/*
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* Settings to be put into the physical channel when we
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* trigger this txd. Other registers are in llis_va[0].
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*/
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u32 ccfg;
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};
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/**
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* struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
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* states
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* @PL08X_CHAN_IDLE: the channel is idle
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* @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
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* channel and is running a transfer on it
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* @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
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* channel, but the transfer is currently paused
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* @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
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* channel to become available (only pertains to memcpy channels)
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*/
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enum pl08x_dma_chan_state {
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PL08X_CHAN_IDLE,
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PL08X_CHAN_RUNNING,
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PL08X_CHAN_PAUSED,
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PL08X_CHAN_WAITING,
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};
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/**
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* struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
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* @chan: wrappped abstract channel
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* @phychan: the physical channel utilized by this channel, if there is one
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* @phychan_hold: if non-zero, hold on to the physical channel even if we
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* have no pending entries
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* @tasklet: tasklet scheduled by the IRQ to handle actual work etc
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* @name: name of channel
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* @cd: channel platform data
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* @runtime_addr: address for RX/TX according to the runtime config
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* @runtime_direction: current direction of this channel according to
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* runtime config
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* @pend_list: queued transactions pending on this channel
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* @at: active transaction on this channel
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* @lock: a lock for this channel data
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* @host: a pointer to the host (internal use)
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* @state: whether the channel is idle, paused, running etc
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* @slave: whether this channel is a device (slave) or for memcpy
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* @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
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* channels. Fill with 'true' if peripheral should be flow controller. Direction
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* will be selected at Runtime.
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* @waiting: a TX descriptor on this channel which is waiting for a physical
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* channel to become available
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*/
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struct pl08x_dma_chan {
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struct dma_chan chan;
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struct pl08x_phy_chan *phychan;
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int phychan_hold;
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struct tasklet_struct tasklet;
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char *name;
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const struct pl08x_channel_data *cd;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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u32 src_cctl;
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u32 dst_cctl;
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enum dma_transfer_direction runtime_direction;
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struct list_head pend_list;
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struct pl08x_txd *at;
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spinlock_t lock;
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struct pl08x_driver_data *host;
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enum pl08x_dma_chan_state state;
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bool slave;
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bool device_fc;
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struct pl08x_txd *waiting;
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};
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/**
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* struct pl08x_platform_data - the platform configuration for the PL08x
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* PrimeCells.
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