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dt-bindings: clock: r9a07g043-cpg: Add power domain IDs

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Add power domain IDs for the RZ/G2UL (R9A07G043) SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20240422105355.1622177-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Claudiu Beznea 2024-04-22 13:53:48 +03:00 committed by Geert Uytterhoeven
parent d0d4585222
commit b6cc692ac6
1 changed files with 52 additions and 0 deletions
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52
include/dt-bindings/clock/r9a07g043-cpg.h
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@ -200,5 +200,57 @@
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
/* Power domain IDs. */
#define R9A07G043_PD_ALWAYS_ON 0
#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
#define R9A07G043_PD_DMAC 6
#define R9A07G043_PD_GTM0 7
#define R9A07G043_PD_GTM1 8
#define R9A07G043_PD_GTM2 9
#define R9A07G043_PD_MTU 10
#define R9A07G043_PD_POE3 11
#define R9A07G043_PD_WDT0 12
#define R9A07G043_PD_SPI 13
#define R9A07G043_PD_SDHI0 14
#define R9A07G043_PD_SDHI1 15
#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
#define R9A07G043_PD_SSI0 19
#define R9A07G043_PD_SSI1 20
#define R9A07G043_PD_SSI2 21
#define R9A07G043_PD_SSI3 22
#define R9A07G043_PD_SRC 23
#define R9A07G043_PD_USB0 24
#define R9A07G043_PD_USB1 25
#define R9A07G043_PD_USB_PHY 26
#define R9A07G043_PD_ETHER0 27
#define R9A07G043_PD_ETHER1 28
#define R9A07G043_PD_I2C0 29
#define R9A07G043_PD_I2C1 30
#define R9A07G043_PD_I2C2 31
#define R9A07G043_PD_I2C3 32
#define R9A07G043_PD_SCIF0 33
#define R9A07G043_PD_SCIF1 34
#define R9A07G043_PD_SCIF2 35
#define R9A07G043_PD_SCIF3 36
#define R9A07G043_PD_SCIF4 37
#define R9A07G043_PD_SCI0 38
#define R9A07G043_PD_SCI1 39
#define R9A07G043_PD_IRDA 40
#define R9A07G043_PD_RSPI0 41
#define R9A07G043_PD_RSPI1 42
#define R9A07G043_PD_RSPI2 43
#define R9A07G043_PD_CANFD 44
#define R9A07G043_PD_ADC 45
#define R9A07G043_PD_TSU 46
#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */