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clk: qcom: rpmh: Add support for RPMH clocks on SM6350
Add support for RPMH clocks on SM6350 SoCs. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210820203243.230157-3-konrad.dybcio@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -536,6 +536,26 @@ static const struct clk_rpmh_desc clk_rpmh_sc7280 = {
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.num_clks = ARRAY_SIZE(sc7280_rpmh_clocks),
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};
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DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk2, ln_bb_clk2_ao, "lnbclkg2", 4);
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DEFINE_CLK_RPMH_VRM(sm6350, ln_bb_clk3, ln_bb_clk3_ao, "lnbclkg3", 4);
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DEFINE_CLK_RPMH_ARC(sm6350, qlink, qlink_ao, "qphy.lvl", 0x1, 4);
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static struct clk_hw *sm6350_rpmh_clocks[] = {
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[RPMH_CXO_CLK] = &sc7280_bi_tcxo.hw,
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[RPMH_CXO_CLK_A] = &sc7280_bi_tcxo_ao.hw,
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[RPMH_LN_BB_CLK2] = &sm6350_ln_bb_clk2.hw,
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[RPMH_LN_BB_CLK2_A] = &sm6350_ln_bb_clk2_ao.hw,
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[RPMH_LN_BB_CLK3] = &sm6350_ln_bb_clk3.hw,
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[RPMH_LN_BB_CLK3_A] = &sm6350_ln_bb_clk3_ao.hw,
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[RPMH_QLINK_CLK] = &sm6350_qlink.hw,
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[RPMH_QLINK_CLK_A] = &sm6350_qlink_ao.hw,
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};
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static const struct clk_rpmh_desc clk_rpmh_sm6350 = {
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.clks = sm6350_rpmh_clocks,
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.num_clks = ARRAY_SIZE(sm6350_rpmh_clocks),
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};
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static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
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void *data)
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{
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@ -623,6 +643,7 @@ static const struct of_device_id clk_rpmh_match_table[] = {
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{ .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x},
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{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
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{ .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55},
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{ .compatible = "qcom,sm6350-rpmh-clk", .data = &clk_rpmh_sm6350},
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{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
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{ .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
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{ .compatible = "qcom,sm8350-rpmh-clk", .data = &clk_rpmh_sm8350},
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@ -31,5 +31,7 @@
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#define RPMH_RF_CLK5_A 22
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#define RPMH_PKA_CLK 23
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#define RPMH_HWKM_CLK 24
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#define RPMH_QLINK_CLK 25
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#define RPMH_QLINK_CLK_A 26
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#endif
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