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dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for SC7280. Update reg property min/max items in YAML schema.
Fixes: 4185b27b3b
("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-4-git-send-email-quic_c_skakit@quicinc.com
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@ -22,6 +22,8 @@ properties:
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clock-names: true
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reg: true
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compatible:
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enum:
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- qcom,sc7280-lpassaoncc
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@ -38,8 +40,8 @@ properties:
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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'#reset-cells':
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const: 1
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qcom,adsp-pil-mode:
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description:
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@ -75,6 +77,11 @@ allOf:
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items:
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- const: bi_tcxo
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- const: lpass_aon_cc_main_rcg_clk_src
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reg:
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items:
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- description: lpass core cc register
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- description: lpass audio csr register
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- if:
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properties:
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compatible:
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@ -96,6 +103,8 @@ allOf:
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- const: bi_tcxo_ao
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- const: iface
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reg:
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maxItems: 1
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- if:
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properties:
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compatible:
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@ -114,6 +123,8 @@ allOf:
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items:
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- const: bi_tcxo
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reg:
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maxItems: 1
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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@ -122,13 +133,15 @@ examples:
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#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
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lpass_audiocc: clock-controller@3300000 {
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compatible = "qcom,sc7280-lpassaudiocc";
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reg = <0x3300000 0x30000>;
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reg = <0x3300000 0x30000>,
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<0x32a9000 0x1000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
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clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
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power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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};
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- |
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@ -24,6 +24,11 @@
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#define LPASS_AUDIO_CC_RX_MCLK_CLK 14
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#define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15
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/* LPASS AUDIO CC CSR */
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#define LPASS_AUDIO_SWR_RX_CGCR 0
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#define LPASS_AUDIO_SWR_TX_CGCR 1
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#define LPASS_AUDIO_SWR_WSA_CGCR 2
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/* LPASS_AON_CC clocks */
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#define LPASS_AON_CC_PLL 0
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#define LPASS_AON_CC_PLL_OUT_EVEN 1
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