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pinctrl: qcom: Introduce SM4250 LPI pinctrl driver
Add support for the pin controller block on SM4250 Low Power Island. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/20240612-sm4250-lpi-v4-2-a0342e47e21b@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Srinivas Kandagatla
Linus Walleij
parent
2ffa7a3546
commit
c2e5a25e8d
@ -68,6 +68,15 @@ config PINCTRL_SC7280_LPASS_LPI
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Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
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(Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform.
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config PINCTRL_SM4250_LPASS_LPI
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tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver"
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depends on ARM64 || COMPILE_TEST
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depends on PINCTRL_LPASS_LPI
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help
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This is the pinctrl, pinmux, pinconf and gpiolib driver for the
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Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
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(Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform.
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config PINCTRL_SM6115_LPASS_LPI
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tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"
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depends on ARM64 || COMPILE_TEST
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@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
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obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
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obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
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obj-$(CONFIG_PINCTRL_SDX75) += pinctrl-sdx75.o
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obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o
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obj-$(CONFIG_PINCTRL_SM4450) += pinctrl-sm4450.o
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obj-$(CONFIG_PINCTRL_SM6115) += pinctrl-sm6115.o
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obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o
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236
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
Normal file
236
drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c
Normal file
@ -0,0 +1,236 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020, 2023 Linaro Ltd.
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*/
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#include <linux/gpio/driver.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "pinctrl-lpass-lpi.h"
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enum lpass_lpi_functions {
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LPI_MUX_dmic01_clk,
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LPI_MUX_dmic01_data,
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LPI_MUX_dmic23_clk,
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LPI_MUX_dmic23_data,
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LPI_MUX_dmic4_clk,
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LPI_MUX_dmic4_data,
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LPI_MUX_ext_mclk0_a,
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LPI_MUX_ext_mclk0_b,
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LPI_MUX_ext_mclk1_a,
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LPI_MUX_ext_mclk1_b,
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LPI_MUX_ext_mclk1_c,
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LPI_MUX_i2s1_clk,
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LPI_MUX_i2s1_data,
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LPI_MUX_i2s1_ws,
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LPI_MUX_i2s2_clk,
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LPI_MUX_i2s2_data,
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LPI_MUX_i2s2_ws,
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LPI_MUX_i2s3_clk,
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LPI_MUX_i2s3_data,
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LPI_MUX_i2s3_ws,
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LPI_MUX_qup_io_00,
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LPI_MUX_qup_io_01,
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LPI_MUX_qup_io_05,
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LPI_MUX_qup_io_10,
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LPI_MUX_qup_io_11,
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LPI_MUX_qup_io_25,
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LPI_MUX_qup_io_21,
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LPI_MUX_qup_io_26,
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LPI_MUX_qup_io_31,
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LPI_MUX_qup_io_36,
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LPI_MUX_qua_mi2s_data,
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LPI_MUX_qua_mi2s_sclk,
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LPI_MUX_qua_mi2s_ws,
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LPI_MUX_slim_clk,
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LPI_MUX_slim_data,
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LPI_MUX_sync_out,
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LPI_MUX_swr_rx_clk,
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LPI_MUX_swr_rx_data,
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LPI_MUX_swr_tx_clk,
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LPI_MUX_swr_tx_data,
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LPI_MUX_swr_wsa_clk,
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LPI_MUX_swr_wsa_data,
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LPI_MUX_gpio,
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LPI_MUX__,
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};
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static const struct pinctrl_pin_desc sm4250_lpi_pins[] = {
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PINCTRL_PIN(0, "gpio0"),
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PINCTRL_PIN(1, "gpio1"),
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PINCTRL_PIN(2, "gpio2"),
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PINCTRL_PIN(3, "gpio3"),
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PINCTRL_PIN(4, "gpio4"),
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PINCTRL_PIN(5, "gpio5"),
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PINCTRL_PIN(6, "gpio6"),
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PINCTRL_PIN(7, "gpio7"),
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PINCTRL_PIN(8, "gpio8"),
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PINCTRL_PIN(9, "gpio9"),
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PINCTRL_PIN(10, "gpio10"),
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PINCTRL_PIN(11, "gpio11"),
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PINCTRL_PIN(12, "gpio12"),
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PINCTRL_PIN(13, "gpio13"),
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PINCTRL_PIN(14, "gpio14"),
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PINCTRL_PIN(15, "gpio15"),
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PINCTRL_PIN(16, "gpio16"),
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PINCTRL_PIN(17, "gpio17"),
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PINCTRL_PIN(18, "gpio18"),
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PINCTRL_PIN(19, "gpio19"),
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PINCTRL_PIN(20, "gpio20"),
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PINCTRL_PIN(21, "gpio21"),
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PINCTRL_PIN(22, "gpio22"),
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PINCTRL_PIN(23, "gpio23"),
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PINCTRL_PIN(24, "gpio24"),
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PINCTRL_PIN(25, "gpio25"),
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PINCTRL_PIN(26, "gpio26"),
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};
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static const char * const dmic01_clk_groups[] = { "gpio6" };
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static const char * const dmic01_data_groups[] = { "gpio7" };
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static const char * const dmic23_clk_groups[] = { "gpio8" };
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static const char * const dmic23_data_groups[] = { "gpio9" };
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static const char * const dmic4_clk_groups[] = { "gpio10" };
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static const char * const dmic4_data_groups[] = { "gpio11" };
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static const char * const ext_mclk0_a_groups[] = { "gpio13" };
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static const char * const ext_mclk0_b_groups[] = { "gpio5" };
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static const char * const ext_mclk1_a_groups[] = { "gpio18" };
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static const char * const ext_mclk1_b_groups[] = { "gpio9" };
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static const char * const ext_mclk1_c_groups[] = { "gpio17" };
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static const char * const slim_clk_groups[] = { "gpio14" };
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static const char * const slim_data_groups[] = { "gpio15" };
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static const char * const i2s1_clk_groups[] = { "gpio6" };
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static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
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static const char * const i2s1_ws_groups[] = { "gpio7" };
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static const char * const i2s2_clk_groups[] = { "gpio10" };
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static const char * const i2s2_data_groups[] = { "gpio12", "gpio13" };
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static const char * const i2s2_ws_groups[] = { "gpio11" };
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static const char * const i2s3_clk_groups[] = { "gpio14" };
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static const char * const i2s3_data_groups[] = { "gpio16", "gpio17" };
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static const char * const i2s3_ws_groups[] = { "gpio15" };
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static const char * const qup_io_00_groups[] = { "gpio19" };
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static const char * const qup_io_01_groups[] = { "gpio21" };
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static const char * const qup_io_05_groups[] = { "gpio23" };
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static const char * const qup_io_10_groups[] = { "gpio20" };
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static const char * const qup_io_11_groups[] = { "gpio22" };
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static const char * const qup_io_25_groups[] = { "gpio23" };
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static const char * const qup_io_21_groups[] = { "gpio25" };
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static const char * const qup_io_26_groups[] = { "gpio25" };
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static const char * const qup_io_31_groups[] = { "gpio26" };
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static const char * const qup_io_36_groups[] = { "gpio26" };
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static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4", "gpio5" };
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static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
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static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
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static const char * const sync_out_groups[] = { "gpio19", "gpio20", "gpio21", "gpio22",
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"gpio23", "gpio24", "gpio25", "gpio26"};
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static const char * const swr_rx_clk_groups[] = { "gpio3" };
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static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
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static const char * const swr_tx_clk_groups[] = { "gpio0" };
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static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2" };
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static const char * const swr_wsa_clk_groups[] = { "gpio10" };
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static const char * const swr_wsa_data_groups[] = { "gpio11" };
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static const struct lpi_pingroup sm4250_groups[] = {
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LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
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LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
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LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
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LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
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LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
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LPI_PINGROUP(5, 12, swr_rx_data, ext_mclk0_b, qua_mi2s_data, _),
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LPI_PINGROUP(6, LPI_NO_SLEW, dmic01_clk, i2s1_clk, _, _),
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LPI_PINGROUP(7, LPI_NO_SLEW, dmic01_data, i2s1_ws, _, _),
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LPI_PINGROUP(8, LPI_NO_SLEW, dmic23_clk, i2s1_data, _, _),
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LPI_PINGROUP(9, LPI_NO_SLEW, dmic23_data, i2s1_data, ext_mclk1_b, _),
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LPI_PINGROUP(10, 16, i2s2_clk, swr_wsa_clk, dmic4_clk, _),
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LPI_PINGROUP(11, 18, i2s2_ws, swr_wsa_data, dmic4_data, _),
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LPI_PINGROUP(12, LPI_NO_SLEW, dmic23_clk, i2s2_data, _, _),
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LPI_PINGROUP(13, LPI_NO_SLEW, dmic23_data, i2s2_data, ext_mclk0_a, _),
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LPI_PINGROUP(14, LPI_NO_SLEW, i2s3_clk, slim_clk, _, _),
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LPI_PINGROUP(15, LPI_NO_SLEW, i2s3_ws, slim_data, _, _),
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LPI_PINGROUP(16, LPI_NO_SLEW, i2s3_data, _, _, _),
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LPI_PINGROUP(17, LPI_NO_SLEW, i2s3_data, ext_mclk1_c, _, _),
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LPI_PINGROUP(18, 20, ext_mclk1_a, swr_rx_data, _, _),
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LPI_PINGROUP(19, LPI_NO_SLEW, qup_io_00, sync_out, _, _),
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LPI_PINGROUP(20, LPI_NO_SLEW, qup_io_10, sync_out, _, _),
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LPI_PINGROUP(21, LPI_NO_SLEW, qup_io_01, sync_out, _, _),
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LPI_PINGROUP(22, LPI_NO_SLEW, qup_io_11, sync_out, _, _),
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LPI_PINGROUP(23, LPI_NO_SLEW, qup_io_25, qup_io_05, sync_out, _),
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LPI_PINGROUP(25, LPI_NO_SLEW, qup_io_26, qup_io_21, sync_out, _),
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LPI_PINGROUP(26, LPI_NO_SLEW, qup_io_36, qup_io_31, sync_out, _),
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};
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static const struct lpi_function sm4250_functions[] = {
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LPI_FUNCTION(dmic01_clk),
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LPI_FUNCTION(dmic01_data),
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LPI_FUNCTION(dmic23_clk),
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LPI_FUNCTION(dmic23_data),
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LPI_FUNCTION(dmic4_clk),
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LPI_FUNCTION(dmic4_data),
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LPI_FUNCTION(ext_mclk0_a),
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LPI_FUNCTION(ext_mclk0_b),
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LPI_FUNCTION(ext_mclk1_a),
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LPI_FUNCTION(ext_mclk1_b),
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LPI_FUNCTION(ext_mclk1_c),
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LPI_FUNCTION(i2s1_clk),
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LPI_FUNCTION(i2s1_data),
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LPI_FUNCTION(i2s1_ws),
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LPI_FUNCTION(i2s2_clk),
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LPI_FUNCTION(i2s2_data),
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LPI_FUNCTION(i2s2_ws),
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LPI_FUNCTION(i2s3_clk),
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LPI_FUNCTION(i2s3_data),
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LPI_FUNCTION(i2s3_ws),
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LPI_FUNCTION(qup_io_00),
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LPI_FUNCTION(qup_io_01),
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LPI_FUNCTION(qup_io_05),
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LPI_FUNCTION(qup_io_10),
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LPI_FUNCTION(qup_io_11),
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LPI_FUNCTION(qup_io_25),
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LPI_FUNCTION(qup_io_21),
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LPI_FUNCTION(qup_io_26),
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LPI_FUNCTION(qup_io_31),
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LPI_FUNCTION(qup_io_36),
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LPI_FUNCTION(qua_mi2s_data),
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LPI_FUNCTION(qua_mi2s_sclk),
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LPI_FUNCTION(qua_mi2s_ws),
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LPI_FUNCTION(slim_clk),
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LPI_FUNCTION(slim_data),
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LPI_FUNCTION(sync_out),
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LPI_FUNCTION(swr_rx_clk),
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LPI_FUNCTION(swr_rx_data),
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LPI_FUNCTION(swr_tx_clk),
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LPI_FUNCTION(swr_tx_data),
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LPI_FUNCTION(swr_wsa_clk),
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LPI_FUNCTION(swr_wsa_data),
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};
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static const struct lpi_pinctrl_variant_data sm4250_lpi_data = {
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.pins = sm4250_lpi_pins,
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.npins = ARRAY_SIZE(sm4250_lpi_pins),
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.groups = sm4250_groups,
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.ngroups = ARRAY_SIZE(sm4250_groups),
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.functions = sm4250_functions,
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.nfunctions = ARRAY_SIZE(sm4250_functions),
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};
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static const struct of_device_id lpi_pinctrl_of_match[] = {
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{ .compatible = "qcom,sm4250-lpass-lpi-pinctrl", .data = &sm4250_lpi_data },
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{ }
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};
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MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
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static struct platform_driver lpi_pinctrl_driver = {
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.driver = {
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.name = "qcom-sm4250-lpass-lpi-pinctrl",
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.of_match_table = lpi_pinctrl_of_match,
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},
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.probe = lpi_pinctrl_probe,
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.remove_new = lpi_pinctrl_remove,
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};
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module_platform_driver(lpi_pinctrl_driver);
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MODULE_DESCRIPTION("QTI SM4250 LPI GPIO pin control driver");
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MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>");
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MODULE_LICENSE("GPL");
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