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dt-bindings: clock: tegra: Remove PMC clock IDs
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so these clocks should be provided by the Tegra PMC. IDs for these clocks have been defined in dt-bindings/soc/tegra-pmc.h. This patch removes the IDs for these clocks from the Tegra clock device tree bindings. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -272,10 +272,10 @@
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#define TEGRA114_CLK_AUDIO3 242
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#define TEGRA114_CLK_AUDIO4 243
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#define TEGRA114_CLK_SPDIF 244
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#define TEGRA114_CLK_CLK_OUT_1 245
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#define TEGRA114_CLK_CLK_OUT_2 246
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#define TEGRA114_CLK_CLK_OUT_3 247
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#define TEGRA114_CLK_BLINK 248
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/* 245 */
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/* 246 */
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/* 247 */
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/* 248 */
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#define TEGRA114_CLK_OSC 249
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/* 250 */
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/* 251 */
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@ -335,9 +335,9 @@
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#define TEGRA114_CLK_AUDIO3_MUX 303
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#define TEGRA114_CLK_AUDIO4_MUX 304
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#define TEGRA114_CLK_SPDIF_MUX 305
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#define TEGRA114_CLK_CLK_OUT_1_MUX 306
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#define TEGRA114_CLK_CLK_OUT_2_MUX 307
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#define TEGRA114_CLK_CLK_OUT_3_MUX 308
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/* 306 */
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/* 307 */
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/* 308 */
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#define TEGRA114_CLK_DSIA_MUX 309
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#define TEGRA114_CLK_DSIB_MUX 310
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#define TEGRA114_CLK_XUSB_SS_DIV2 311
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@ -271,10 +271,10 @@
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#define TEGRA124_CLK_AUDIO3 242
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#define TEGRA124_CLK_AUDIO4 243
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#define TEGRA124_CLK_SPDIF 244
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#define TEGRA124_CLK_CLK_OUT_1 245
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#define TEGRA124_CLK_CLK_OUT_2 246
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#define TEGRA124_CLK_CLK_OUT_3 247
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#define TEGRA124_CLK_BLINK 248
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/* 245 */
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/* 246 */
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/* 247 */
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/* 248 */
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#define TEGRA124_CLK_OSC 249
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/* 250 */
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/* 251 */
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@ -334,9 +334,9 @@
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#define TEGRA124_CLK_AUDIO3_MUX 303
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#define TEGRA124_CLK_AUDIO4_MUX 304
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#define TEGRA124_CLK_SPDIF_MUX 305
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#define TEGRA124_CLK_CLK_OUT_1_MUX 306
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#define TEGRA124_CLK_CLK_OUT_2_MUX 307
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#define TEGRA124_CLK_CLK_OUT_3_MUX 308
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/* 306 */
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/* 307 */
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/* 308 */
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/* 309 */
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/* 310 */
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#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
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@ -131,7 +131,7 @@
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#define TEGRA20_CLK_CCLK 108
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#define TEGRA20_CLK_HCLK 109
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#define TEGRA20_CLK_PCLK 110
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#define TEGRA20_CLK_BLINK 111
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/* 111 */
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#define TEGRA20_CLK_PLL_A 112
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#define TEGRA20_CLK_PLL_A_OUT0 113
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#define TEGRA20_CLK_PLL_C 114
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@ -306,10 +306,10 @@
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#define TEGRA210_CLK_AUDIO3 274
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#define TEGRA210_CLK_AUDIO4 275
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#define TEGRA210_CLK_SPDIF 276
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#define TEGRA210_CLK_CLK_OUT_1 277
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#define TEGRA210_CLK_CLK_OUT_2 278
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#define TEGRA210_CLK_CLK_OUT_3 279
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#define TEGRA210_CLK_BLINK 280
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/* 277 */
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/* 278 */
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/* 279 */
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/* 280 */
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#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
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#define TEGRA210_CLK_SOR0_OUT 281
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#define TEGRA210_CLK_SOR1_OUT 282
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@ -388,9 +388,9 @@
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#define TEGRA210_CLK_AUDIO3_MUX 353
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#define TEGRA210_CLK_AUDIO4_MUX 354
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#define TEGRA210_CLK_SPDIF_MUX 355
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#define TEGRA210_CLK_CLK_OUT_1_MUX 356
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#define TEGRA210_CLK_CLK_OUT_2_MUX 357
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#define TEGRA210_CLK_CLK_OUT_3_MUX 358
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/* 356 */
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/* 357 */
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/* 358 */
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#define TEGRA210_CLK_DSIA_MUX 359
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#define TEGRA210_CLK_DSIB_MUX 360
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/* 361 */
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@ -232,11 +232,11 @@
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#define TEGRA30_CLK_AUDIO3 204
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#define TEGRA30_CLK_AUDIO4 205
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#define TEGRA30_CLK_SPDIF 206
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#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */
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#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */
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#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */
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/* 207 */
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/* 208 */
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/* 209 */
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#define TEGRA30_CLK_SCLK 210
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#define TEGRA30_CLK_BLINK 211
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/* 211 */
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#define TEGRA30_CLK_CCLK_G 212
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#define TEGRA30_CLK_CCLK_LP 213
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#define TEGRA30_CLK_TWD 214
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@ -262,9 +262,9 @@
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/* 297 */
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/* 298 */
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/* 299 */
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#define TEGRA30_CLK_CLK_OUT_1_MUX 300
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#define TEGRA30_CLK_CLK_OUT_2_MUX 301
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#define TEGRA30_CLK_CLK_OUT_3_MUX 302
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/* 300 */
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/* 301 */
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/* 302 */
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#define TEGRA30_CLK_AUDIO0_MUX 303
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#define TEGRA30_CLK_AUDIO1_MUX 304
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#define TEGRA30_CLK_AUDIO2_MUX 305
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