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ARM: fix cacheflush with PAN

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It seems that the cacheflush syscall got broken when PAN for LPAE was
implemented. User access was not enabled around the cache maintenance
instructions, causing them to fault.

Fixes: 7af5b901e8 ("ARM: 9358/2: Implement PAN for LPAE by TTBR0 page table walks disablement")
Reported-by: Michał Pecio <michal.pecio@gmail.com>
Tested-by: Michał Pecio <michal.pecio@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Russell King (Oracle) 2024-11-12 10:16:13 +00:00
parent fb5af7d540
commit ca29cfcc4a
1 changed files with 3 additions and 0 deletions
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3
arch/arm/kernel/traps.c
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@ -570,6 +570,7 @@ static int bad_syscall(int n, struct pt_regs *regs)
static inline int
__do_cache_op(unsigned long start, unsigned long end)
{
unsigned int ua_flags;
int ret;
do {
@ -578,7 +579,9 @@ __do_cache_op(unsigned long start, unsigned long end)
if (fatal_signal_pending(current))
return 0;
ua_flags = uaccess_save_and_enable();
ret = flush_icache_user_range(start, start + chunk);
uaccess_restore(ua_flags);
if (ret)
return ret;