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dt-bindings: riscv: Add Svvptc ISA extension description

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Add description for the Svvptc ISA extension which was ratified recently.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240717060125.139416-3-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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Alexandre Ghiti 2024-07-17 08:01:23 +02:00 committed by Palmer Dabbelt
parent a6efe33cc5
commit d25599b593
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Documentation/devicetree/bindings/riscv/extensions.yaml
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@ -171,6 +171,13 @@ properties:
memory types as ratified in the 20191213 version of the privileged
ISA specification.
- const: svvptc
description:
The standard Svvptc supervisor-level extension for
address-translation cache behaviour with respect to invalid entries
as ratified at commit 4a69197e5617 ("Update to ratified state") of
riscv-svvptc.
- const: zacas
description: |
The Zacas extension for Atomic Compare-and-Swap (CAS) instructions