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dt-bindings: pinctrl: renesas,rzn1-pinctrl: documentation
The Renesas RZ/N1 device family PINCTRL node description. Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Phil Edworthy
Geert Uytterhoeven
parent
a97f340c0a
commit
d6381fbbf2
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Renesas RZ/N1 SoC Pinctrl node description.
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Pin controller node
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-------------------
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Required properties:
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- compatible: SoC-specific compatible string "renesas,<soc-specific>-pinctrl"
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followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible
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strings must be one of:
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"renesas,r9a06g032-pinctrl" for RZ/N1D
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"renesas,r9a06g033-pinctrl" for RZ/N1S
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- reg: Address base and length of the memory area where the pin controller
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hardware is mapped to.
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- clocks: phandle for the clock, see the description of clock-names below.
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- clock-names: Contains the name of the clock:
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"bus", the bus clock, sometimes described as pclk, for register accesses.
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Example:
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pinctrl: pin-controller@40067000 {
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compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
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reg = <0x40067000 0x1000>, <0x51000000 0x480>;
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clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
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clock-names = "bus";
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};
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Sub-nodes
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---------
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The child nodes of the pin controller node describe a pin multiplexing
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function.
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- Pin multiplexing sub-nodes:
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A pin multiplexing sub-node describes how to configure a set of
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(or a single) pin in some desired alternate function mode.
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A single sub-node may define several pin configurations.
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Please refer to pinctrl-bindings.txt to get to know more on generic
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pin properties usage.
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The allowed generic formats for a pin multiplexing sub-node are the
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following ones:
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node-1 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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node-2 {
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sub-node-1 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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sub-node-2 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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...
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sub-node-n {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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};
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node-3 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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sub-node-1 {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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...
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sub-node-n {
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pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ;
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GENERIC_PINCONFIG;
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};
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};
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Use the latter two formats when pins part of the same logical group need to
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have different generic pin configuration flags applied. Note that the generic
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pinconfig in node-3 does not apply to the sub-nodes.
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Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle
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of the most external one.
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Eg.
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client-1 {
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...
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pinctrl-0 = <&node-1>;
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...
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};
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client-2 {
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...
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pinctrl-0 = <&node-2>;
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...
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};
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Required properties:
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- pinmux:
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integer array representing pin number and pin multiplexing configuration.
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When a pin has to be configured in alternate function mode, use this
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property to identify the pin by its global index, and provide its
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alternate function configuration number along with it.
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When multiple pins are required to be configured as part of the same
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alternate function they shall be specified as members of the same
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argument list of a single "pinmux" property.
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Integers values in the "pinmux" argument list are assembled as:
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(PIN | MUX_FUNC << 8)
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where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is
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one of the alternate function identifiers defined in:
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<include/dt-bindings/pinctrl/rzn1-pinctrl.h>
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These identifiers collapse the IO Multiplex Configuration Level 1 and
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Level 2 numbers that are detailed in the hardware reference manual into a
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single number. The identifiers for Level 2 are simply offset by 10.
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Additional identifiers are provided to specify the MDIO source peripheral.
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Optional generic pinconf properties:
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- bias-disable - disable any pin bias
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- bias-pull-up - pull up the pin with 50 KOhm
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- bias-pull-down - pull down the pin with 50 KOhm
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- bias-high-impedance - high impedance mode
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- drive-strength - sink or source at most 4, 6, 8 or 12 mA
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Example:
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A serial communication interface with a TX output pin and an RX input pin.
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&pinctrl {
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pins_uart0: pins_uart0 {
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pinmux = <
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RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */
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RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */
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>;
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};
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};
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Example 2:
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Here we set the pull up on the RXD pin of the UART.
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&pinctrl {
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pins_uart0: pins_uart0 {
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pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>; /* TXD */
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pins_uart6_rx {
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pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>; /* RXD */
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bias-pull-up;
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};
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};
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};
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141
include/dt-bindings/pinctrl/rzn1-pinctrl.h
Normal file
141
include/dt-bindings/pinctrl/rzn1-pinctrl.h
Normal file
@ -0,0 +1,141 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Defines macros and constants for Renesas RZ/N1 pin controller pin
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* muxing functions.
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*/
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#ifndef __DT_BINDINGS_RZN1_PINCTRL_H
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#define __DT_BINDINGS_RZN1_PINCTRL_H
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#define RZN1_PINMUX(_gpio, _func) \
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(((_func) << 8) | (_gpio))
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/*
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* Given the different levels of muxing on the SoC, it was decided to
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* 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO
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* muxes are all represented by one single value.
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*
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* You can derive the hardware value pretty easily too, as
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* 0...9 are Level 1
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* 10...71 are Level 2. The Level 2 mux will be set to this
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* value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be
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* set accordingly.
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* 72...103 are for the 2 MDIO muxes.
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*/
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#define RZN1_FUNC_HIGHZ 0
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#define RZN1_FUNC_0L 1
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#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2
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#define RZN1_FUNC_CLK_ETH_NAND 3
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#define RZN1_FUNC_QSPI 4
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#define RZN1_FUNC_SDIO 5
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#define RZN1_FUNC_LCD 6
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#define RZN1_FUNC_LCD_E 7
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#define RZN1_FUNC_MSEBIM 8
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#define RZN1_FUNC_MSEBIS 9
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#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */
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#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0)
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#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1)
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#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2)
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#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3)
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#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4)
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#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5)
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#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6)
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#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7)
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#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8)
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#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9)
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#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10)
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#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11)
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#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12)
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#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13)
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#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14)
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#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15)
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#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16)
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#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17)
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#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18)
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#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19)
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#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20)
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#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21)
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#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22)
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#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23)
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#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24)
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#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25)
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#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26)
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#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27)
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#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28)
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#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29)
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#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30)
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#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31)
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#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32)
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#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33)
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#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34)
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#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35)
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#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36)
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#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37)
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#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38)
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#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39)
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#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40)
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#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41)
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#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42)
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#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43)
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#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44)
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#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45)
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#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46)
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#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47)
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#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48)
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#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49)
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#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50)
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#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51)
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#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52)
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#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53)
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#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54)
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#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55)
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#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56)
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#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57)
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#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58)
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#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59)
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#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60)
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#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61)
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#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62)
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/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */
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#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0)
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#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1)
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#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2)
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#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3)
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#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4)
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#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5)
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#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6)
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#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7)
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/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
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#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8)
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#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9)
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#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10)
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#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11)
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#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12)
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#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13)
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#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14)
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#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15)
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/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */
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#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16)
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#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17)
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#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18)
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#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19)
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#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20)
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#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21)
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#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22)
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#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23)
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/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */
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#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24)
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#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25)
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#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26)
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#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27)
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#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28)
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#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29)
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#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30)
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#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31)
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#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32)
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#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */
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