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irqchip/armada-370-xp: Allow mapping only per-CPU interrupts

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On platforms where MPIC is not the top-level interrupt controller the
driver currently only supports handling of the per-CPU interrupts (the
first 29 interrupts). This is obvious from the code of
mpic_handle_cascade_irq(), which reads only one cause register.

Bound the number of available interrupts in the interrupt domain to 29 for
these platforms.

The corresponding device-trees refer only to per-CPU interrupts via MPIC,
the other interrupts are referred to via GIC.

Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Marek Behún 2024-08-07 18:41:03 +02:00 committed by Thomas Gleixner
parent 4042a965a5
commit d6ca3f4402
1 changed files with 13 additions and 6 deletions
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19
drivers/irqchip/irq-armada-370-xp.c
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@ -848,6 +848,19 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par
for (irq_hw_number_t i = 0; i < nr_irqs; i++)
writel(i, mpic->base + MPIC_INT_CLEAR_ENABLE);
/*
* Initialize mpic->parent_irq before calling any other functions, since
* it is used to distinguish between IPI and non-IPI platforms.
*/
mpic->parent_irq = irq_of_parse_and_map(node, 0);
/*
* On non-IPI platforms the driver currently supports only the per-CPU
* interrupts (the first 29 interrupts). See mpic_handle_cascade_irq().
*/
if (!mpic_is_ipi_available(mpic))
nr_irqs = MPIC_PER_CPU_IRQS_NR;
mpic->domain = irq_domain_add_linear(node, nr_irqs, &mpic_irq_ops, mpic);
if (!mpic->domain) {
pr_err("%pOF: Unable to add IRQ domain\n", node);
@ -856,12 +869,6 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par
irq_domain_update_bus_token(mpic->domain, DOMAIN_BUS_WIRED);
/*
* Initialize mpic->parent_irq before calling any other functions, since
* it is used to distinguish between IPI and non-IPI platforms.
*/
mpic->parent_irq = irq_of_parse_and_map(node, 0);
/* Setup for the boot CPU */
mpic_perf_init(mpic);
mpic_smp_cpu_init(mpic);