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clk: tegra: Fix sparse warning for pll_m
Sparse generates the following warning for the pll_m params structure: drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry defined twice drivers/clk/tegra/clk-tegra210.c:1570:10: also defined here Fix this by correcting the index for the MISC1 register. Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -1566,7 +1566,7 @@ static struct tegra_clk_pll_params pll_m_params = {
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.iddq_bit_idx = PLLM_IDDQ_BIT,
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.max_p = PLL_QLIN_PDIV_MAX,
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.ext_misc_reg[0] = PLLM_MISC2,
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.ext_misc_reg[0] = PLLM_MISC1,
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.ext_misc_reg[1] = PLLM_MISC1,
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.round_p_to_pdiv = pll_qlin_p_to_pdiv,
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.pdiv_tohw = pll_qlin_pdiv_to_hw,
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.div_nmp = &pllm_nmp,
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