mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Char/Misc driver fixes for 6.6-final
Here are some very small driver fixes for 6.6-final that have shown up in the past 2 weeks. Included in here are: - tiny fastrpc bugfixes for reported errors - nvmem register fixes - iio driver fixes for some reported problems - fpga test fix - MAINTAINERS file update for fpga All of these have been in linux-next this week with no reported problems. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCZTy13A8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+ykHzACdHeaGvszwWwcjHX0SmZBRNbHoj80AnRaM0RP0 SpAvYj7k79XtxOH0KTe0 =y5Zi -----END PGP SIGNATURE----- Merge tag 'char-misc-6.6-final' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver fixes from Greg KH: "Here are some very small driver fixes for 6.6-final that have shown up in the past two weeks. Included in here are: - tiny fastrpc bugfixes for reported errors - nvmem register fixes - iio driver fixes for some reported problems - fpga test fix - MAINTAINERS file update for fpga All of these have been in linux-next this week with no reported problems" * tag 'char-misc-6.6-final' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: fpga: Fix memory leak for fpga_region_test_class_find() fpga: m10bmc-sec: Change contact for secure update driver fpga: disable KUnit test suites when module support is enabled iio: afe: rescale: Accept only offset channels nvmem: imx: correct nregs for i.MX6ULL nvmem: imx: correct nregs for i.MX6UL nvmem: imx: correct nregs for i.MX6SLL misc: fastrpc: Unmap only if buffer is unmapped from DSP misc: fastrpc: Clean buffers on remote invocation failures misc: fastrpc: Free DMA handles for RPC calls with no arguments misc: fastrpc: Reset metadata buffer to avoid incorrect free iio: exynos-adc: request second interupt only when touchscreen mode is used iio: adc: xilinx-xadc: Correct temperature offset/scale for UltraScale iio: adc: xilinx-xadc: Don't clobber preset voltage/temperature thresholds dt-bindings: iio: add missing reset-gpios constrain
This commit is contained in:
commit
db5cda7fd4
@ -1,7 +1,7 @@
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_root_entry_hash
|
||||
Date: Sep 2022
|
||||
KernelVersion: 5.20
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||||
Contact: Russ Weight <russell.h.weight@intel.com>
|
||||
Contact: Peter Colberg <peter.colberg@intel.com>
|
||||
Description: Read only. Returns the root entry hash for the static
|
||||
region if one is programmed, else it returns the
|
||||
string: "hash not programmed". This file is only
|
||||
@ -11,7 +11,7 @@ Description: Read only. Returns the root entry hash for the static
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_root_entry_hash
|
||||
Date: Sep 2022
|
||||
KernelVersion: 5.20
|
||||
Contact: Russ Weight <russell.h.weight@intel.com>
|
||||
Contact: Peter Colberg <peter.colberg@intel.com>
|
||||
Description: Read only. Returns the root entry hash for the partial
|
||||
reconfiguration region if one is programmed, else it
|
||||
returns the string: "hash not programmed". This file
|
||||
@ -21,7 +21,7 @@ Description: Read only. Returns the root entry hash for the partial
|
||||
What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_root_entry_hash
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Date: Sep 2022
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KernelVersion: 5.20
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Contact: Russ Weight <russell.h.weight@intel.com>
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Contact: Peter Colberg <peter.colberg@intel.com>
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Description: Read only. Returns the root entry hash for the BMC image
|
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if one is programmed, else it returns the string:
|
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"hash not programmed". This file is only visible if the
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@ -31,7 +31,7 @@ Description: Read only. Returns the root entry hash for the BMC image
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What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/sr_canceled_csks
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Date: Sep 2022
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KernelVersion: 5.20
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Contact: Russ Weight <russell.h.weight@intel.com>
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Contact: Peter Colberg <peter.colberg@intel.com>
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Description: Read only. Returns a list of indices for canceled code
|
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signing keys for the static region. The standard bitmap
|
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list format is used (e.g. "1,2-6,9").
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@ -39,7 +39,7 @@ Description: Read only. Returns a list of indices for canceled code
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What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/pr_canceled_csks
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Date: Sep 2022
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KernelVersion: 5.20
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Contact: Russ Weight <russell.h.weight@intel.com>
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Contact: Peter Colberg <peter.colberg@intel.com>
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Description: Read only. Returns a list of indices for canceled code
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signing keys for the partial reconfiguration region. The
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standard bitmap list format is used (e.g. "1,2-6,9").
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@ -47,7 +47,7 @@ Description: Read only. Returns a list of indices for canceled code
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What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/bmc_canceled_csks
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Date: Sep 2022
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KernelVersion: 5.20
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Contact: Russ Weight <russell.h.weight@intel.com>
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Contact: Peter Colberg <peter.colberg@intel.com>
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Description: Read only. Returns a list of indices for canceled code
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signing keys for the BMC. The standard bitmap list format
|
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is used (e.g. "1,2-6,9").
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@ -55,7 +55,7 @@ Description: Read only. Returns a list of indices for canceled code
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What: /sys/bus/platform/drivers/intel-m10bmc-sec-update/.../security/flash_count
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Date: Sep 2022
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KernelVersion: 5.20
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Contact: Russ Weight <russell.h.weight@intel.com>
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Contact: Peter Colberg <peter.colberg@intel.com>
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Description: Read only. Returns number of times the secure update
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staging area has been flashed.
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Format: "%u".
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|
@ -32,7 +32,8 @@ properties:
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spi-cpol: true
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reset-gpios: true
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reset-gpios:
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maxItems: 1
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interrupts:
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minItems: 1
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|
@ -78,7 +78,8 @@ properties:
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- const: -1000
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- const: 22000
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reset-gpios: true
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reset-gpios:
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maxItems: 1
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adi,dc-dc-ilim-microamp:
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enum: [150000, 200000, 250000, 300000, 350000, 400000]
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|
@ -23,7 +23,8 @@ properties:
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maxItems: 1
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description: Connected to ADC_RDY pin.
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reset-gpios: true
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reset-gpios:
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maxItems: 1
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required:
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- compatible
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|
@ -23,7 +23,8 @@ properties:
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maxItems: 1
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description: Connected to ADC_RDY pin.
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reset-gpios: true
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reset-gpios:
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maxItems: 1
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additionalProperties: false
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|
@ -10701,7 +10701,7 @@ F: drivers/mfd/intel-m10-bmc*
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F: include/linux/mfd/intel-m10-bmc.h
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INTEL MAX10 BMC SECURE UPDATES
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M: Russ Weight <russell.h.weight@intel.com>
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M: Peter Colberg <peter.colberg@intel.com>
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L: linux-fpga@vger.kernel.org
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S: Maintained
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F: Documentation/ABI/testing/sysfs-driver-intel-m10-bmc-sec-update
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|
@ -1,6 +1,6 @@
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config FPGA_KUNIT_TESTS
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tristate "KUnit test for the FPGA subsystem" if !KUNIT_ALL_TESTS
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depends on FPGA && FPGA_REGION && FPGA_BRIDGE && KUNIT=y
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bool "KUnit test for the FPGA subsystem" if !KUNIT_ALL_TESTS
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depends on FPGA=y && FPGA_REGION=y && FPGA_BRIDGE=y && KUNIT=y && MODULES=n
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default KUNIT_ALL_TESTS
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help
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This builds unit tests for the FPGA subsystem
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|
@ -93,6 +93,8 @@ static void fpga_region_test_class_find(struct kunit *test)
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|
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region = fpga_region_class_find(NULL, &ctx->region_pdev->dev, fake_region_match);
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KUNIT_EXPECT_PTR_EQ(test, region, ctx->region);
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|
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put_device(®ion->dev);
|
||||
}
|
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|
||||
/*
|
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|
@ -826,16 +826,26 @@ static int exynos_adc_probe(struct platform_device *pdev)
|
||||
}
|
||||
}
|
||||
|
||||
/* leave out any TS related code if unreachable */
|
||||
if (IS_REACHABLE(CONFIG_INPUT)) {
|
||||
has_ts = of_property_read_bool(pdev->dev.of_node,
|
||||
"has-touchscreen") || pdata;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
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info->irq = irq;
|
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|
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irq = platform_get_irq(pdev, 1);
|
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if (irq == -EPROBE_DEFER)
|
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return irq;
|
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if (has_ts) {
|
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irq = platform_get_irq(pdev, 1);
|
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if (irq == -EPROBE_DEFER)
|
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return irq;
|
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|
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info->tsirq = irq;
|
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info->tsirq = irq;
|
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} else {
|
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info->tsirq = -1;
|
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}
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|
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info->dev = &pdev->dev;
|
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|
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@ -900,12 +910,6 @@ static int exynos_adc_probe(struct platform_device *pdev)
|
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if (info->data->init_hw)
|
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info->data->init_hw(info);
|
||||
|
||||
/* leave out any TS related code if unreachable */
|
||||
if (IS_REACHABLE(CONFIG_INPUT)) {
|
||||
has_ts = of_property_read_bool(pdev->dev.of_node,
|
||||
"has-touchscreen") || pdata;
|
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}
|
||||
|
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if (pdata)
|
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info->delay = pdata->delay;
|
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else
|
||||
|
@ -456,6 +456,9 @@ static const struct xadc_ops xadc_zynq_ops = {
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.interrupt_handler = xadc_zynq_interrupt_handler,
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.update_alarm = xadc_zynq_update_alarm,
|
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.type = XADC_TYPE_S7,
|
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/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
|
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.temp_scale = 503975,
|
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.temp_offset = 273150,
|
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};
|
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|
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static const unsigned int xadc_axi_reg_offsets[] = {
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@ -566,6 +569,9 @@ static const struct xadc_ops xadc_7s_axi_ops = {
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.interrupt_handler = xadc_axi_interrupt_handler,
|
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.flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
|
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.type = XADC_TYPE_S7,
|
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/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
|
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.temp_scale = 503975,
|
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.temp_offset = 273150,
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};
|
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|
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static const struct xadc_ops xadc_us_axi_ops = {
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@ -577,6 +583,12 @@ static const struct xadc_ops xadc_us_axi_ops = {
|
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.interrupt_handler = xadc_axi_interrupt_handler,
|
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.flags = XADC_FLAGS_BUFFERED | XADC_FLAGS_IRQ_OPTIONAL,
|
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.type = XADC_TYPE_US,
|
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/**
|
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* Values below are for UltraScale+ (SYSMONE4) using internal reference.
|
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* See https://docs.xilinx.com/v/u/en-US/ug580-ultrascale-sysmon
|
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*/
|
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.temp_scale = 509314,
|
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.temp_offset = 280231,
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};
|
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|
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static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
|
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@ -945,8 +957,7 @@ static int xadc_read_raw(struct iio_dev *indio_dev,
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*val2 = bits;
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return IIO_VAL_FRACTIONAL_LOG2;
|
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case IIO_TEMP:
|
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/* Temp in C = (val * 503.975) / 2**bits - 273.15 */
|
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*val = 503975;
|
||||
*val = xadc->ops->temp_scale;
|
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*val2 = bits;
|
||||
return IIO_VAL_FRACTIONAL_LOG2;
|
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default:
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@ -954,7 +965,7 @@ static int xadc_read_raw(struct iio_dev *indio_dev,
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}
|
||||
case IIO_CHAN_INFO_OFFSET:
|
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/* Only the temperature channel has an offset */
|
||||
*val = -((273150 << bits) / 503975);
|
||||
*val = -((xadc->ops->temp_offset << bits) / xadc->ops->temp_scale);
|
||||
return IIO_VAL_INT;
|
||||
case IIO_CHAN_INFO_SAMP_FREQ:
|
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ret = xadc_read_samplerate(xadc);
|
||||
@ -1423,28 +1434,6 @@ static int xadc_probe(struct platform_device *pdev)
|
||||
if (ret)
|
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return ret;
|
||||
|
||||
/* Disable all alarms */
|
||||
ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,
|
||||
XADC_CONF1_ALARM_MASK);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Set thresholds to min/max */
|
||||
for (i = 0; i < 16; i++) {
|
||||
/*
|
||||
* Set max voltage threshold and both temperature thresholds to
|
||||
* 0xffff, min voltage threshold to 0.
|
||||
*/
|
||||
if (i % 8 < 4 || i == 7)
|
||||
xadc->threshold[i] = 0xffff;
|
||||
else
|
||||
xadc->threshold[i] = 0;
|
||||
ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),
|
||||
xadc->threshold[i]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Go to non-buffered mode */
|
||||
xadc_postdisable(indio_dev);
|
||||
|
||||
|
@ -85,6 +85,8 @@ struct xadc_ops {
|
||||
|
||||
unsigned int flags;
|
||||
enum xadc_type type;
|
||||
int temp_scale;
|
||||
int temp_offset;
|
||||
};
|
||||
|
||||
static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
|
||||
|
@ -214,8 +214,18 @@ static int rescale_read_raw(struct iio_dev *indio_dev,
|
||||
return ret < 0 ? ret : -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
ret = iio_read_channel_scale(rescale->source, &scale, &scale2);
|
||||
return rescale_process_offset(rescale, ret, scale, scale2,
|
||||
if (iio_channel_has_info(rescale->source->channel,
|
||||
IIO_CHAN_INFO_SCALE)) {
|
||||
ret = iio_read_channel_scale(rescale->source, &scale, &scale2);
|
||||
return rescale_process_offset(rescale, ret, scale, scale2,
|
||||
schan_off, val, val2);
|
||||
}
|
||||
|
||||
/*
|
||||
* If we get here we have no scale so scale 1:1 but apply
|
||||
* rescaler and offset, if any.
|
||||
*/
|
||||
return rescale_process_offset(rescale, IIO_VAL_FRACTIONAL, 1, 1,
|
||||
schan_off, val, val2);
|
||||
default:
|
||||
return -EINVAL;
|
||||
@ -280,8 +290,9 @@ static int rescale_configure_channel(struct device *dev,
|
||||
chan->type = rescale->cfg->type;
|
||||
|
||||
if (iio_channel_has_info(schan, IIO_CHAN_INFO_RAW) &&
|
||||
iio_channel_has_info(schan, IIO_CHAN_INFO_SCALE)) {
|
||||
dev_info(dev, "using raw+scale source channel\n");
|
||||
(iio_channel_has_info(schan, IIO_CHAN_INFO_SCALE) ||
|
||||
iio_channel_has_info(schan, IIO_CHAN_INFO_OFFSET))) {
|
||||
dev_info(dev, "using raw+scale/offset source channel\n");
|
||||
} else if (iio_channel_has_info(schan, IIO_CHAN_INFO_PROCESSED)) {
|
||||
dev_info(dev, "using processed channel\n");
|
||||
rescale->chan_processed = true;
|
||||
|
@ -958,6 +958,7 @@ static int fastrpc_get_args(u32 kernel, struct fastrpc_invoke_ctx *ctx)
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
memset(ctx->buf->virt, 0, pkt_size);
|
||||
rpra = ctx->buf->virt;
|
||||
list = fastrpc_invoke_buf_start(rpra, ctx->nscalars);
|
||||
pages = fastrpc_phy_page_start(list, ctx->nscalars);
|
||||
@ -1090,6 +1091,7 @@ static int fastrpc_put_args(struct fastrpc_invoke_ctx *ctx,
|
||||
}
|
||||
}
|
||||
|
||||
/* Clean up fdlist which is updated by DSP */
|
||||
for (i = 0; i < FASTRPC_MAX_FDLIST; i++) {
|
||||
if (!fdlist[i])
|
||||
break;
|
||||
@ -1156,11 +1158,9 @@ static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel,
|
||||
if (IS_ERR(ctx))
|
||||
return PTR_ERR(ctx);
|
||||
|
||||
if (ctx->nscalars) {
|
||||
err = fastrpc_get_args(kernel, ctx);
|
||||
if (err)
|
||||
goto bail;
|
||||
}
|
||||
err = fastrpc_get_args(kernel, ctx);
|
||||
if (err)
|
||||
goto bail;
|
||||
|
||||
/* make sure that all CPU memory writes are seen by DSP */
|
||||
dma_wmb();
|
||||
@ -1176,6 +1176,13 @@ static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel,
|
||||
err = wait_for_completion_interruptible(&ctx->work);
|
||||
}
|
||||
|
||||
if (err)
|
||||
goto bail;
|
||||
|
||||
/* make sure that all memory writes by DSP are seen by CPU */
|
||||
dma_rmb();
|
||||
/* populate all the output buffers with results */
|
||||
err = fastrpc_put_args(ctx, kernel);
|
||||
if (err)
|
||||
goto bail;
|
||||
|
||||
@ -1184,15 +1191,6 @@ static int fastrpc_internal_invoke(struct fastrpc_user *fl, u32 kernel,
|
||||
if (err)
|
||||
goto bail;
|
||||
|
||||
if (ctx->nscalars) {
|
||||
/* make sure that all memory writes by DSP are seen by CPU */
|
||||
dma_rmb();
|
||||
/* populate all the output buffers with results */
|
||||
err = fastrpc_put_args(ctx, kernel);
|
||||
if (err)
|
||||
goto bail;
|
||||
}
|
||||
|
||||
bail:
|
||||
if (err != -ERESTARTSYS && err != -ETIMEDOUT) {
|
||||
/* We are done with this compute context */
|
||||
@ -1983,11 +1981,13 @@ static int fastrpc_req_mem_unmap_impl(struct fastrpc_user *fl, struct fastrpc_me
|
||||
sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_MEM_UNMAP, 1, 0);
|
||||
err = fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE, sc,
|
||||
&args[0]);
|
||||
fastrpc_map_put(map);
|
||||
if (err)
|
||||
if (err) {
|
||||
dev_err(dev, "unmmap\tpt fd = %d, 0x%09llx error\n", map->fd, map->raddr);
|
||||
return err;
|
||||
}
|
||||
fastrpc_map_put(map);
|
||||
|
||||
return err;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fastrpc_req_mem_unmap(struct fastrpc_user *fl, char __user *argp)
|
||||
|
@ -498,7 +498,7 @@ static const struct ocotp_params imx6sl_params = {
|
||||
};
|
||||
|
||||
static const struct ocotp_params imx6sll_params = {
|
||||
.nregs = 128,
|
||||
.nregs = 80,
|
||||
.bank_address_words = 0,
|
||||
.set_timing = imx_ocotp_set_imx6_timing,
|
||||
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
||||
@ -512,14 +512,14 @@ static const struct ocotp_params imx6sx_params = {
|
||||
};
|
||||
|
||||
static const struct ocotp_params imx6ul_params = {
|
||||
.nregs = 128,
|
||||
.nregs = 144,
|
||||
.bank_address_words = 0,
|
||||
.set_timing = imx_ocotp_set_imx6_timing,
|
||||
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
||||
};
|
||||
|
||||
static const struct ocotp_params imx6ull_params = {
|
||||
.nregs = 64,
|
||||
.nregs = 80,
|
||||
.bank_address_words = 0,
|
||||
.set_timing = imx_ocotp_set_imx6_timing,
|
||||
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
||||
|
Loading…
Reference in New Issue
Block a user