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i2c-nomadik: add code to retry on timeout failure
It is seen that i2c-nomadik controller randomly stops generating the interrupts leading to a i2c timeout. As a workaround to this problem, add retries to the on going transfer on failure. Signed-off-by: Virupax Sadashivpetimath <virupax.sadashivpetimath@stericsson.com> Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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b0e751a925
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ebd10e0783
@ -255,8 +255,6 @@ static int init_hw(struct nmk_i2c_dev *dev)
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{
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{
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int stat;
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int stat;
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clk_enable(dev->clk);
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stat = flush_i2c_fifo(dev);
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stat = flush_i2c_fifo(dev);
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if (stat)
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if (stat)
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goto exit;
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goto exit;
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@ -271,8 +269,6 @@ static int init_hw(struct nmk_i2c_dev *dev)
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dev->cli.operation = I2C_NO_OPERATION;
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dev->cli.operation = I2C_NO_OPERATION;
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exit:
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exit:
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/* TODO: Why disable clocks after init hw? */
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clk_disable(dev->clk);
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/*
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/*
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* TODO: What is this delay for?
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* TODO: What is this delay for?
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* Must be pretty pointless since the hw block
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* Must be pretty pointless since the hw block
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@ -572,6 +568,7 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
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u32 cause;
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u32 cause;
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struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
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struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
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u32 i2c_sr;
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u32 i2c_sr;
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int j;
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dev->busy = true;
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dev->busy = true;
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@ -579,63 +576,67 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
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regulator_enable(dev->regulator);
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regulator_enable(dev->regulator);
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pm_runtime_get_sync(&dev->pdev->dev);
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pm_runtime_get_sync(&dev->pdev->dev);
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status = init_hw(dev);
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if (status)
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goto out2;
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clk_enable(dev->clk);
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clk_enable(dev->clk);
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/* setup the i2c controller */
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status = init_hw(dev);
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setup_i2c_controller(dev);
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if (status)
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goto out;
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for (i = 0; i < num_msgs; i++) {
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for (j = 0; j < 3; j++) {
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if (unlikely(msgs[i].flags & I2C_M_TEN)) {
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/* setup the i2c controller */
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dev_err(&dev->pdev->dev, "10 bit addressing"
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setup_i2c_controller(dev);
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"not supported\n");
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status = -EINVAL;
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for (i = 0; i < num_msgs; i++) {
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goto out;
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if (unlikely(msgs[i].flags & I2C_M_TEN)) {
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}
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dev_err(&dev->pdev->dev, "10 bit addressing"
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dev->cli.slave_adr = msgs[i].addr;
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"not supported\n");
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dev->cli.buffer = msgs[i].buf;
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dev->cli.count = msgs[i].len;
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dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
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dev->result = 0;
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if (msgs[i].flags & I2C_M_RD) {
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status = -EINVAL;
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/* it is a read operation */
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goto out;
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dev->cli.operation = I2C_READ;
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}
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status = read_i2c(dev);
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dev->cli.slave_adr = msgs[i].addr;
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} else {
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dev->cli.buffer = msgs[i].buf;
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/* write operation */
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dev->cli.count = msgs[i].len;
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dev->cli.operation = I2C_WRITE;
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dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
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status = write_i2c(dev);
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dev->result = 0;
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}
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if (status || (dev->result)) {
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if (msgs[i].flags & I2C_M_RD) {
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i2c_sr = readl(dev->virtbase + I2C_SR);
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/* it is a read operation */
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/*
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dev->cli.operation = I2C_READ;
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* Check if the controller I2C operation status is set
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status = read_i2c(dev);
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* to ABORT(11b).
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} else {
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*/
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/* write operation */
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if (((i2c_sr >> 2) & 0x3) == 0x3) {
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dev->cli.operation = I2C_WRITE;
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/* get the abort cause */
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status = write_i2c(dev);
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cause = (i2c_sr >> 4)
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}
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& 0x7;
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if (status || (dev->result)) {
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dev_err(&dev->pdev->dev, "%s\n", cause >=
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i2c_sr = readl(dev->virtbase + I2C_SR);
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ARRAY_SIZE(abort_causes) ?
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/*
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* Check if the controller I2C operation status
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* is set to ABORT(11b).
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*/
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if (((i2c_sr >> 2) & 0x3) == 0x3) {
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/* get the abort cause */
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cause = (i2c_sr >> 4)
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& 0x7;
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dev_err(&dev->pdev->dev, "%s\n", cause
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>= ARRAY_SIZE(abort_causes) ?
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"unknown reason" :
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"unknown reason" :
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abort_causes[cause]);
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abort_causes[cause]);
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}
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}
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status = status ? status : dev->result;
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status = status ? status : dev->result;
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goto out;
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break;
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}
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udelay(I2C_DELAY);
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}
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}
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udelay(I2C_DELAY);
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if (status == 0)
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break;
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}
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}
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out:
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out:
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clk_disable(dev->clk);
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clk_disable(dev->clk);
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out2:
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pm_runtime_put_sync(&dev->pdev->dev);
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pm_runtime_put_sync(&dev->pdev->dev);
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if (dev->regulator)
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if (dev->regulator)
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regulator_disable(dev->regulator);
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regulator_disable(dev->regulator);
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