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ARM: dts: renesas: r8a73a4: Add TMU nodes

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Add device nodes for the Timer Units (TMU) on the R-Mobile APE6 SoC,
and the clocks serving them.

Note that TMU channels 1 and 2 are not added, as their interrupts are
not wired to the interrupt controller for the AP-System Core (INTC-SYS),
only to the interrupt controller for the AP-Realtime Core (INTC-RT).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/1a60832f3ba37afb4a5791f4e5db4610ab31beb3.1710864964.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2024-03-19 17:29:05 +01:00
parent 7db74b65a9
commit ecc79ab919
2 changed files with 41 additions and 0 deletions
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37
arch/arm/boot/dts/renesas/r8a73a4.dtsi
View File

@ -60,6 +60,32 @@ timer {
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a73a4", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp1_clks R8A73A4_CLK_TMU0>;
clock-names = "fck";
power-domains = <&pd_c5>;
status = "disabled";
};
tmu3: timer@fff80000 {
compatible = "renesas,tmu-r8a73a4", "renesas,tmu";
reg = <0 0xfff80000 0 0x30>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tuni0", "tuni1", "tuni2";
clocks = <&mstp1_clks R8A73A4_CLK_TMU3>;
clock-names = "fck";
power-domains = <&pd_a3r>;
status = "disabled";
};
dbsc1: memory-controller@e6790000 {
compatible = "renesas,dbsc-r8a73a4";
reg = <0 0xe6790000 0 0x10000>;
@ -654,6 +680,17 @@ extal1_div2_clk: extal1_div2 {
};
/* Gate clocks */
mstp1_clks: mstp1_clks@e6150134 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
clocks = <&cp_clk>, <&mp_clk>;
#clock-cells = <1>;
clock-indices = <
R8A73A4_CLK_TMU0 R8A73A4_CLK_TMU3
>;
clock-output-names =
"tmu0", "tmu3";
};
mstp2_clks: mstp2_clks@e6150138 {
compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;

4
include/dt-bindings/clock/r8a73a4-clock.h
View File

@ -24,6 +24,10 @@
#define R8A73A4_CLK_ZS 14
#define R8A73A4_CLK_HP 15
/* MSTP1 */
#define R8A73A4_CLK_TMU0 25
#define R8A73A4_CLK_TMU3 21
/* MSTP2 */
#define R8A73A4_CLK_DMAC 18
#define R8A73A4_CLK_SCIFB3 17