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- Disable the secure programming interface of the GIC500 chip in the RK3399
SoC to fix interrupt priority assignment and even make a dead machine boot again when the gic-v3 driver enables pseudo NMIs - Correct the declaration of a percpu variable to fix several sparse warnings -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmdexi0ACgkQEsHwGGHe VUoy2A/9EJkTmjoFL+AeDY1nGxjCiPJREZgxKmOgKX9uzjBF/airHs8m5RzYteYK bUBbnrc3LEXMX1sOPGAfAvXTyfrIlWYqv8hVWcaAUs80S7Mm/aSnydA33NP6mj3/ m/113+CnhtBsTThMb/D/Cz4mTq2BrbTFqiUpMSDIA624Zr+XwD4rP1vMUmKDiYGW 8EeW8ym6OnCNQYhd9CMBA/BeFyF4blSb+onwM4rMm3xXgGQJ5ywfp9Ry6wU1x0Q8 EC0Rwz4yHcMYRjlrT940ZVDN6u+i3HPPHrhipJyua9awnDBc3oBT5rmqEg1s99TO P5YemyDHEaTub91HHyHcXL3X6/Enk2mtwA/+RViUywVsiPti2m1k/hvUK5JECoyw MtOZ4Br4KnbKOH2qLyg9S4eWcNLNdlB8Q+At63yssqFpOCaF7LCXnTIzX9by+z4K qriS7UGVqzTFZNtf8oiM++7IkL0zP+P6IlNKiuZVbZilAgAT1KHFoqkVtWhpHdkj UZjmEPxjMQYVVG29OG9rdwAlPu7vyHJsZRaT07GhJIv+QwfufLk7hxMsvPB0Inm5 1rG+JARzBv1eU+91KWvA3LW5CySjASoEQtsrGlh0Ns/Mkduvc68txaperXRf9Fg5 j6kYriZNK85JyDUM6GQ561doxlpVZWMkC/GAKZRP8ZlaUCCokug= =SlQ1 -----END PGP SIGNATURE----- Merge tag 'irq_urgent_for_v6.13_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Borislav Petkov: - Disable the secure programming interface of the GIC500 chip in the RK3399 SoC to fix interrupt priority assignment and even make a dead machine boot again when the gic-v3 driver enables pseudo NMIs - Correct the declaration of a percpu variable to fix several sparse warnings * tag 'irq_urgent_for_v6.13_rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic-v3: Work around insecure GIC integrations irqchip/gic: Correct declaration of *percpu_base pointer in union gic_base
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commit
f7c7a1ba22
@ -161,7 +161,22 @@ static bool cpus_have_group0 __ro_after_init;
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static void __init gic_prio_init(void)
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{
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cpus_have_security_disabled = gic_dist_security_disabled();
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bool ds;
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ds = gic_dist_security_disabled();
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if (!ds) {
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u32 val;
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val = readl_relaxed(gic_data.dist_base + GICD_CTLR);
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val |= GICD_CTLR_DS;
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writel_relaxed(val, gic_data.dist_base + GICD_CTLR);
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ds = gic_dist_security_disabled();
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if (ds)
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pr_warn("Broken GIC integration, security disabled");
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}
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cpus_have_security_disabled = ds;
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cpus_have_group0 = gic_has_group0();
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/*
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@ -64,7 +64,7 @@ static void gic_check_cpu_features(void)
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union gic_base {
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void __iomem *common_base;
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void __percpu * __iomem *percpu_base;
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void __iomem * __percpu *percpu_base;
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};
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struct gic_chip_data {
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