Commit Graph

1981 Commits

Author SHA1 Message Date
Linus Torvalds
9f3a2ba62c The core framework gained a clk provider helper, a clk consumer helper, and
some unit tests for the assigned clk rates feature in DeviceTree. On the vendor
 driver side, we gained a whole pile of SoC driver support detailed below. The
 majority in the diffstat is Qualcomm, but there's also quite a few Samsung and
 Mediatek clk driver additions in here as well. The top vendors is quite common,
 but the sheer amount of new drivers is uncommon, so I'm anticipating a larger
 number of fixes for clk drivers this cycle.
 
 Core:
  - devm_clk_bulk_get_all_enabled() to return number of clks acquired
  - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers
  - KUnit tests for clk-assigned-rates{,-u64}
 
 New Drivers:
  - Marvell PXA1908 SoC clks
  - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver
  - TWL6030 clk driver
  - Nuvoton Arbel BMC NPCM8XX SoC clks
  - MediaTek MT6735 SoC clks
  - MediaTek MT7620, MT7628 and MT7688 MMC clks
  - Add a driver for gated fixed rate clocks
  - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs
  - Camera, display and video clock controllers for Qualcomm SA8775P SoCs
  - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P
  - Global, camera, display, GPU, and video clock controllers for Qualcomm
    SM8475 SoCs
  - RTC power domain and Battery Backup Function (VBATTB) clock support for the
    Renesas RZ/G3S SoC
  - Qualcomm IPQ9574 alpha PLLs
  - Support for i.MX91 CCM in the i.MX93 driver
  - Microchip LAN969X SoC clks
  - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and reset on
    Renesas RZ/V2H(P)
  - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1
  - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP
 
 Updates:
  - Convert more clk bindings to YAML
  - Various clk driver cleanups: NULL checks, add const, etc.
  - Remove END/NUM #defines that count number of clks in various binding headers
  - Continue moving reset drivers to drivers/reset via auxiliary bus
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The core framework gained a clk provider helper, a clk consumer
  helper, and some unit tests for the assigned clk rates feature in
  DeviceTree. On the vendor driver side, we gained a whole pile of SoC
  driver support detailed below. The majority in the diffstat is
  Qualcomm, but there's also quite a few Samsung and Mediatek clk driver
  additions in here as well. The top vendors is quite common, but the
  sheer amount of new drivers is uncommon, so I'm anticipating a larger
  number of fixes for clk drivers this cycle.

  Core:
   - devm_clk_bulk_get_all_enabled() to return number of clks acquired
   - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers
   - KUnit tests for clk-assigned-rates{,-u64}

  New Drivers:
   - Marvell PXA1908 SoC clks
   - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver
   - TWL6030 clk driver
   - Nuvoton Arbel BMC NPCM8XX SoC clks
   - MediaTek MT6735 SoC clks
   - MediaTek MT7620, MT7628 and MT7688 MMC clks
   - Add a driver for gated fixed rate clocks
   - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs
   - Camera, display and video clock controllers for Qualcomm SA8775P
     SoCs
   - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm
     SAR2130P
   - Global, camera, display, GPU, and video clock controllers for
     Qualcomm SM8475 SoCs
   - RTC power domain and Battery Backup Function (VBATTB) clock support
     for the Renesas RZ/G3S SoC
   - Qualcomm IPQ9574 alpha PLLs
   - Support for i.MX91 CCM in the i.MX93 driver
   - Microchip LAN969X SoC clks
   - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and
     reset on Renesas RZ/V2H(P)
   - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1
   - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP

  Updates:
   - Convert more clk bindings to YAML
   - Various clk driver cleanups: NULL checks, add const, etc.
   - Remove END/NUM #defines that count number of clks in various
     binding headers
   - Continue moving reset drivers to drivers/reset via auxiliary bus"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits)
  clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access
  clk: Fix invalid execution of clk_set_rate
  clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider
  clk: lan966x: make it selectable for ARCH_LAN969X
  clk: eyeq: add EyeQ6H west fixed factor clocks
  clk: eyeq: add EyeQ6H central fixed factor clocks
  clk: eyeq: add EyeQ5 fixed factor clocks
  clk: eyeq: add fixed factor clocks infrastructure
  clk: eyeq: require clock index with phandle in all cases
  clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
  dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
  dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
  clk: clk-axi-clkgen: make sure to enable the AXI bus clock
  dt-bindings: clock: axi-clkgen: include AXI clk
  clk: mmp: Add Marvell PXA1908 MPMU driver
  clk: mmp: Add Marvell PXA1908 APMU driver
  clk: mmp: Add Marvell PXA1908 APBCP driver
  clk: mmp: Add Marvell PXA1908 APBC driver
  dt-bindings: clock: Add Marvell PXA1908 clock bindings
  clk: mmp: Switch to use struct u32_fract instead of custom one
  ...
2024-11-22 17:02:25 -08:00
Linus Torvalds
80739fd00c - Several drivers, including atmel-flexcom/rk8xx-core, palmas, and
tps65010, have undergone minor code improvements to enhance consistency and
   fix race conditions.
 
 - The syscon driver now utilizes the regmap max_register_is_0 capability
   for consistent register map configuration across syscons of all sizes.
 
 - New device support has been added for QCS8300, qcs615, SA8255p, and
   samsung,s2dos05, expanding the range of compatible hardware.
 
 - The cros_ec driver now supports loading cros_ec_ucsi on supported ECs
   and avoids loading the charger with UCSI, streamlining functionality.
 
 - The bd96801 driver now utilizes the more modern maple tree register
   cache, improving performance.
 
 - The da9052-spi driver has undergone a fix to change the read-mask to
   write-mask, preventing potential issues.
 
 - Unused declarations in max77693 have been removed, and support for
   samsung,s2dos05 has been added, enhancing code clarity and device compatibility.
 
 - Error handling in cs42l43 has been fixed to avoid unbalanced regulator
   put and ensure proper synchronization during driver removal.
 
 - The wcd934x driver now uses MODULE_DEVICE_TABLE() instead of
   MODULE_ALIAS(), improving code consistency.
 
 - Documentation for qcom,tcsr, syscon, and atmel-smc has been updated
   and reorganized for better clarity and maintainability.
 
 - The intel_soc_pmic_bxtwc driver has undergone significant improvements,
   including the use of IRQ domains for various devices, fixing IRQ domain names
   duplication, and code refactoring for better consistency and maintainability.
 
 - The ipaq-micro driver has received a fix for a missing break statement in
   the default case, enhancing code robustness.
 
 - Support for the AXP323 PMIC has been added to the axp20x driver, along
   with ensuring a clear relationship between IDs and model names, and allowing
   multiple regulators, broadening hardware compatibility.
 
 - The cs42l43 driver now disables IRQs during suspend for improved power
   management.
 
 - The adp5585 driver has reduced its dependencies by dropping the obsolete
   dependency on COMPILE_TEST.
 
 - Initial support for the MT6328 PMIC has been added to the mt6397 driver,
   expanding the range of supported hardware.
 
 - The rtc-bd70528 driver has been simplified by dropping the IC name from
   IRQ, improving code readability.
 
 - Documentation for qcom,spmi-pmic, ti,twl, and zii,rave-sp has been
   updated to enhance clarity and incorporate new features.
 
 - The rt5033 driver has received a fix for a missing regmap_del_irq_chip()
   in the error handling path.
 
 - New device support has been added for MSM8917, and the
   intel_soc_pmic_crc driver now supports non-ACPI instantiated i2c_client.
 
 - The 88pm886 driver has added support for the RTC cell, and the tqmx86
   driver has improved its GPIO IRQ setup and added I2C IRQ support,
   increasing functionality.
 
 - The sprd,sc2731 DT schema has been updated and converted to YAML format
   for better readability and maintainability.
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Merge tag 'mfd-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:

 - Several drivers, including atmel-flexcom/rk8xx-core, palmas, and
   tps65010, have undergone minor code improvements to enhance
   consistency and fix race conditions.

 - The syscon driver now utilizes the regmap max_register_is_0
   capability for consistent register map configuration across syscons
   of all sizes.

 - New device support has been added for QCS8300, qcs615, SA8255p, and
   samsung,s2dos05, expanding the range of compatible hardware.

 - The cros_ec driver now supports loading cros_ec_ucsi on supported ECs
   and avoids loading the charger with UCSI, streamlining functionality.

 - The bd96801 driver now utilizes the more modern maple tree register
   cache, improving performance.

 - The da9052-spi driver has undergone a fix to change the read-mask to
   write-mask, preventing potential issues.

 - Unused declarations in max77693 have been removed, and support for
   samsung,s2dos05 has been added, enhancing code clarity and device
   compatibility.

 - Error handling in cs42l43 has been fixed to avoid unbalanced
   regulator put and ensure proper synchronization during driver
   removal.

 - The wcd934x driver now uses MODULE_DEVICE_TABLE() instead of
   MODULE_ALIAS(), improving code consistency.

 - Documentation for qcom,tcsr, syscon, and atmel-smc has been updated
   and reorganized for better clarity and maintainability.

 - The intel_soc_pmic_bxtwc driver has undergone significant
   improvements, including the use of IRQ domains for various devices,
   fixing IRQ domain names duplication, and code refactoring for better
   consistency and maintainability.

 - The ipaq-micro driver has received a fix for a missing break
   statement in the default case, enhancing code robustness.

 - Support for the AXP323 PMIC has been added to the axp20x driver,
   along with ensuring a clear relationship between IDs and model names,
   and allowing multiple regulators, broadening hardware compatibility.

 - The cs42l43 driver now disables IRQs during suspend for improved
   power management.

 - The adp5585 driver has reduced its dependencies by dropping the
   obsolete dependency on COMPILE_TEST.

 - Initial support for the MT6328 PMIC has been added to the mt6397
   driver, expanding the range of supported hardware.

 - The rtc-bd70528 driver has been simplified by dropping the IC name
   from IRQ, improving code readability.

 - Documentation for qcom,spmi-pmic, ti,twl, and zii,rave-sp has been
   updated to enhance clarity and incorporate new features.

 - The rt5033 driver has received a fix for a missing
   regmap_del_irq_chip() in the error handling path.

 - New device support has been added for MSM8917, and the
   intel_soc_pmic_crc driver now supports non-ACPI instantiated
   i2c_client.

 - The 88pm886 driver has added support for the RTC cell, and the tqmx86
   driver has improved its GPIO IRQ setup and added I2C IRQ support,
   increasing functionality.

 - The sprd,sc2731 DT schema has been updated and converted to YAML
   format for better readability and maintainability.

* tag 'mfd-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (62 commits)
  dt-bindings: mfd: bd71828: Use charger resistor in mOhm instead of MOhm
  dt-bindings: mfd: sprd,sc2731: Convert to YAML
  mfd: tqmx86: Add I2C IRQ support
  mfd: tqmx86: Make IRQ setup errors non-fatal
  mfd: tqmx86: Refactor GPIO IRQ setup
  mfd: tqmx86: Improve gpio_irq module parameter description
  mfd: tqmx86: Add board definitions for TQMx120UC, TQMx130UC and TQMxE41S
  mfd: 88pm886: Add the RTC cell
  dt-bindings: mfd: Add Realtek RTL9300 switch peripherals
  mfd: intel_soc_pmic_crc: Add support for non ACPI instantiated i2c_client
  mfd: intel_soc_pmic_*: Consistently use filename as driver name
  dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8917
  mfd: rt5033: Fix missing regmap_del_irq_chip()
  mfd: cgbc-core: Fix error handling paths in cgbc_init_device()
  dt-bindings: mfd: aspeed: Support for AST2700
  mfd: Switch back to struct platform_driver::remove()
  dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750
  mfd: rtc: bd7xxxx Drop IC name from IRQ
  mfd: mt6397: Add initial support for MT6328
  mfd: adp5585: Drop obsolete dependency on COMPILE_TEST
  ...
2024-11-22 16:19:47 -08:00
Stephen Boyd
21a5352dc7 Merge branches 'clk-marvell', 'clk-adi', 'clk-qcom' and 'clk-devm' into clk-next
- Add devm_clk_bulk_get_all_enabled() to return number of clks acquired
 - Marvell PXA1908 SoC clks

* clk-marvell:
  clk: mmp: Add Marvell PXA1908 MPMU driver
  clk: mmp: Add Marvell PXA1908 APMU driver
  clk: mmp: Add Marvell PXA1908 APBCP driver
  clk: mmp: Add Marvell PXA1908 APBC driver
  dt-bindings: clock: Add Marvell PXA1908 clock bindings
  clk: mmp: Switch to use struct u32_fract instead of custom one

* clk-adi:
  clk: clk-axi-clkgen: make sure to enable the AXI bus clock
  dt-bindings: clock: axi-clkgen: include AXI clk

* clk-qcom: (43 commits)
  clk: qcom: remove unused data from gcc-ipq5424.c
  clk: qcom: Add support for Global Clock Controller on QCS8300
  dt-bindings: clock: qcom: Add GCC clocks for QCS8300
  clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC
  clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
  dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding
  clk: qcom: add SAR2130P GPU Clock Controller support
  clk: qcom: dispcc-sm8550: enable support for SAR2130P
  clk: qcom: tcsrcc-sm8550: add SAR2130P support
  clk: qcom: add support for GCC on SAR2130P
  clk: qcom: rpmh: add support for SAR2130P
  clk: qcom: rcg2: add clk_rcg2_shared_floor_ops
  dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles
  dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible
  dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible
  dt-bindings: clock: qcom: document SAR2130P Global Clock Controller
  dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible
  clk: qcom: Make GCC_6125 depend on QCOM_GDSC
  dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros
  dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros
  ...

* clk-devm:
  clk: Provide devm_clk_bulk_get_all_enabled() helper
2024-11-18 20:01:35 -08:00
Stephen Boyd
0cf32b1f37 Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and 'clk-allwinner' into clk-next
* clk-samsung:
  clk: samsung: Introduce Exynos8895 clock driver
  clk: samsung: clk-pll: Add support for pll_{1051x,1052x}
  dt-bindings: clock: samsung: Add Exynos8895 SoC
  clk: samsung: gs101: make all ufs related clocks critical
  clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support
  dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
  clk: samsung: Fix out-of-bound access of of_match_node()
  dt-bindings: clock: samsung: remove define with number of clocks for FSD
  clk: samsung: fsd: do not define number of clocks in bindings
  clk: samsung: Fix errors reported by checkpatch
  clk: samsung: Fix block comment style warnings reported by checkpatch

* clk-microchip:
  clk: lan966x: add support for lan969x SoC clock driver
  clk: lan966x: prepare driver for lan969x support
  clk: lan966x: make clk_names const char * const
  dt-bindings: clock: add support for lan969x

* clk-imx:
  clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains()
  clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restore
  clk: imx: clk-scu: fix clk enable state save and restore
  clk: imx: fracn-gppll: fix pll power up
  clk: imx: fracn-gppll: correct PLL initialization flow
  clk: imx: lpcg-scu: SW workaround for errata (e10858)
  clk: imx: add i.MX91 clk
  dt-bindings: clock: Add i.MX91 clock support
  dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition
  clk: imx93: Move IMX93_CLK_END macro to clk driver
  clk: imx95-blk-ctl: Add one clock gate for HSIO block
  dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL

* clk-amlogic:
  clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX
  clk: amlogic: axg-audio: use the auxiliary reset driver
  reset: amlogic: Fix small whitespace issue
  reset: amlogic: add auxiliary reset driver support
  reset: amlogic: split the device core and platform probe
  reset: amlogic: move drivers to a dedicated directory
  reset: amlogic: add reset status support
  reset: amlogic: use reset number instead of register count
  reset: amlogic: add driver parameters
  reset: amlogic: make parameters unsigned
  reset: amlogic: use generic data matching function
  reset: amlogic: convert driver to regmap
  dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema
  clk: meson: meson8b: remove spinlock
  clk: meson: mpll: Delete a useless spinlock from the MPLL
  clk: meson: s4: pll: fix frac maximum value for hifi_pll
  clk: meson: c3: pll: fix frac maximum value for hifi_pll
  clk: meson: Support PLL with fixed fractional denominators
  clk: meson: s4: pll: hifi_pll support fractional multiplier

* clk-allwinner:
  clk: sunxi-ng: Use of_property_present() for non-boolean properties
  clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
  clk: sunxi-ng: Constify struct ccu_reset_map
  clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
2024-11-18 20:01:28 -08:00
Stephen Boyd
b2f8240153 Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and 'clk-bindings' into clk-next
- Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver
 - TWL6030 clk driver
 - Nuvoton Arbel BMC NPCM8XX SoC clks
 - Convert more clk bindings to YAML

* clk-mobileye:
  clk: eyeq: add EyeQ6H west fixed factor clocks
  clk: eyeq: add EyeQ6H central fixed factor clocks
  clk: eyeq: add EyeQ5 fixed factor clocks
  clk: eyeq: add fixed factor clocks infrastructure
  clk: eyeq: require clock index with phandle in all cases
  clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
  dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
  dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
  clk: eyeq: add driver
  clk: divider: Introduce CLK_DIVIDER_EVEN_INTEGERS flag
  dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes
  Revert "dt-bindings: clock: mobileye,eyeq5-clk: add bindings"

* clk-twl:
  clk: twl: add TWL6030 support
  clk: twl: remove is_prepared

* clk-nuvoton:
  clk: npcm8xx: add clock controller
  reset: npcm: register npcm8xx clock auxiliary bus device
  dt-bindings: reset: npcm: add clock properties

* clk-renesas:
  clk: renesas: vbattb: Add VBATTB clock driver
  clk: Add devm_clk_hw_register_gate_parent_hw()
  clk: renesas: rzg2l: Fix FOUTPOSTDIV clk
  dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
  clk: renesas: r9a08g045: Add power domain for RTC
  clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe
  clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones
  clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup()
  dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
  clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks
  clk: renesas: r9a09g057: Add clock and reset entries for ICU
  clk: renesas: r9a09g057: Add CA55 core clocks
  clk: renesas: Remove duplicate and trailing empty lines

* clk-bindings:
  dt-bindings: clock: actions,owl-cmu: convert to YAML
  dt-bindings: clock: ti: Convert mux.txt to json-schema
  dt-bindings: clock: ti: Convert divider.txt to json-schema
  dt-bindings: clock: ti: Convert interface.txt to json-schema
  dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML
2024-11-18 20:00:28 -08:00
Théo Lebrun
6a46b75a91 dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
Add #defines for Mobileye clock controller:

 - EyeQ5 core 0 thru 3 clocks. Internally:

      EQ5C_PLL_CPU:           already exposed
      └── EQ5C_CPU_OCC:       unexposed, no reason to do so
          ├── EQ5C_CPU_CORE0: new!
          ├── EQ5C_CPU_CORE1: new!
          ├── EQ5C_CPU_CORE2: new!
          └── EQ5C_CPU_CORE3: new!

 - EyeQ5 peripheral clocks. Internally:

      EQ5C_PLL_PER:          already exposed
      ├── EQ5C_PER_OCC:      new!
      │   ├── EQ5C_PER_SPI:  new!
      │   ├── EQ5C_PER_I2C:  new!
      │   ├── EQ5C_PER_GPIO: new!
      │   └── EQ5C_PER_UART: new!
      ├── EQ5C_PER_EMMC:     new!
      └── EQ5C_PER_OCC_PCI:  new!

 - EyeQ6H central OLB. Internally:

      EQ6HC_CENTRAL_PLL_CPU:     new!
      └── EQ6HC_CENTRAL_CPU_OCC: new!

 - EyeQ6H west OLB. Internally:

      EQ6HC_WEST_PLL_PER:          new!
      └── EQ6HC_WEST_PER_OCC:      new!
          └── EQ6HC_WEST_PER_UART: new!

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-2-84cfefb3f485@bootlin.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14 14:52:26 -08:00
Duje Mihanović
f03b086624 dt-bindings: clock: Add Marvell PXA1908 clock bindings
Add dt bindings and documentation for the Marvell PXA1908 clock
controller.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-4-e050609b8d6c@skole.hr
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14 14:32:56 -08:00
Yassine Oudjana
a7479860bb dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers
Add device tree bindings for syscon clock and reset controllers (IMGSYS,
MFGCFG, VDECSYS and VENCSYS).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241106111402.200940-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14 12:52:14 -08:00
Arnd Bergmann
f50f6052c3 Qualcomm Arm64 DeviceTree changes for v6.13
Introduce descriptions of the 8cx Gen3-based Microsoft Surface Pro 9 5G,
 X Elite based Dell XPS 13 9345, the QCS9100 platform and the "Ride"
 development boards thereon, and the SM7325 platform and the Nothing
 Phone 1.
 
 MSM8998 gains support for HDMI. The Lenovo Miix 630 gains support for
 volume keys, audio and sensor DSPs, touchscreen, and its specific WiFi
 calibration variant.
 
 On QCM6490, Fairphone FP5 gains a thermistor adjacent to UFS/RAM, while
 the IDP gains UFS and WiFi support. For QCS6490 changes to Rb3Gen2
 enables WiFi, Venus, PCIe, SD-card, and volume keys. Adreno speedbins
 are adjusted and PMU nodes' compatibles for the two clusters are
 corrected.
 
 The DB845C/RB3 and QRB5165 RB5 vision mezzanines are converted to
 DeviceTree overlays, and both gains CMA heap for libcamera to use.
 
 SA8775P gains GPI DMA support, support for controlling download mode
 (bootloader-assisted ramdump support), additional UARTs, and qcrypto
 support. The "Ride" development board gains WiFi and Bluetooth support.
 
 On SC8280XP (8cx Gen3) another UART is described, used in the
 Microsoft Surface 9 5G. The WiFi/BT combo chip's power management unit
 is described on the CRD and Lenovo ThinkPad X13s.
 
 On SDM630/660 the GPU SMMU and clock controller is added, as is the
 A2Noc and LPASS SMMU, and the DSP-based WiFi device. GPU, modem DSP and
 WiFi is then enabled on the Inforce 6560 development board.
 
 On SM8450 Hardware Development Kit, the WCN6855 is modelled to enable
 WiFi and Bluetooth. A "global" interrupt is defined on SM8450 PCIe RC
 controller, to enable hotplug.
 
 On X Elite, USB Type-C controllers are marked as usb-role-switch
 capable, the GICv3 ITS is enabled for PCIe. TCSR region is described and
 wired up to allow setting and cleaning the download mode
 (bootloader-assisted ramdump) flag, and residency numbers for C4/C5 are
 updated.
 
 USB role switch is enabled on Lenovo ThinkPad T14s and the ASUS Vivobook
 S15. The T14s also gains support for a second source trackpad. The
 Microsoft Surface Laptop gains LID switch and the USB Type-A connector
 attached to the multiport controller is enabled. The CRD has its HID
 device power supplies described.
 
 Application SMMU is flagged as DMA coherent across QDU1000, SC7180,
 SC8180X, SC8280XP, SDM670, SDM845, SM8150, SM8350, SM8450, and X1E80100.
 
 In addition to this, the effort to improve style and binding compliance
 continued.
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Merge tag 'qcom-arm64-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm Arm64 DeviceTree changes for v6.13

Introduce descriptions of the 8cx Gen3-based Microsoft Surface Pro 9 5G,
X Elite based Dell XPS 13 9345, the QCS9100 platform and the "Ride"
development boards thereon, and the SM7325 platform and the Nothing
Phone 1.

MSM8998 gains support for HDMI. The Lenovo Miix 630 gains support for
volume keys, audio and sensor DSPs, touchscreen, and its specific WiFi
calibration variant.

On QCM6490, Fairphone FP5 gains a thermistor adjacent to UFS/RAM, while
the IDP gains UFS and WiFi support. For QCS6490 changes to Rb3Gen2
enables WiFi, Venus, PCIe, SD-card, and volume keys. Adreno speedbins
are adjusted and PMU nodes' compatibles for the two clusters are
corrected.

The DB845C/RB3 and QRB5165 RB5 vision mezzanines are converted to
DeviceTree overlays, and both gains CMA heap for libcamera to use.

SA8775P gains GPI DMA support, support for controlling download mode
(bootloader-assisted ramdump support), additional UARTs, and qcrypto
support. The "Ride" development board gains WiFi and Bluetooth support.

On SC8280XP (8cx Gen3) another UART is described, used in the
Microsoft Surface 9 5G. The WiFi/BT combo chip's power management unit
is described on the CRD and Lenovo ThinkPad X13s.

On SDM630/660 the GPU SMMU and clock controller is added, as is the
A2Noc and LPASS SMMU, and the DSP-based WiFi device. GPU, modem DSP and
WiFi is then enabled on the Inforce 6560 development board.

On SM8450 Hardware Development Kit, the WCN6855 is modelled to enable
WiFi and Bluetooth. A "global" interrupt is defined on SM8450 PCIe RC
controller, to enable hotplug.

On X Elite, USB Type-C controllers are marked as usb-role-switch
capable, the GICv3 ITS is enabled for PCIe. TCSR region is described and
wired up to allow setting and cleaning the download mode
(bootloader-assisted ramdump) flag, and residency numbers for C4/C5 are
updated.

USB role switch is enabled on Lenovo ThinkPad T14s and the ASUS Vivobook
S15. The T14s also gains support for a second source trackpad. The
Microsoft Surface Laptop gains LID switch and the USB Type-A connector
attached to the multiport controller is enabled. The CRD has its HID
device power supplies described.

Application SMMU is flagged as DMA coherent across QDU1000, SC7180,
SC8180X, SC8280XP, SDM670, SDM845, SM8150, SM8350, SM8450, and X1E80100.

In addition to this, the effort to improve style and binding compliance
continued.

* tag 'qcom-arm64-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (120 commits)
  arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Add cma heap for libcamera softisp support
  arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Add cma heap for libcamera softisp support
  arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Drop redundant clock-lanes from camera@1a
  arm64: dts: qcom: sc8280xp-x13s: Drop redundant clock-lanes from camera@10
  arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Convert mezzanine riser to dtso
  arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Convert mezzanine riser to dtbo
  arm64: dts: qcom: sm8450-hdk: model the PMU of the on-board wcn6855
  arm64: dts: qcom: sc8280xp-x13s: model the PMU of the on-board wcn6855
  arm64: dts: qcom: sc8280xp-crd: enable bluetooth
  arm64: dts: qcom: sc8280xp-crd: model the PMU of the on-board wcn6855
  arm64: dts: qcom: qcs9100: Add support for the QCS9100 Ride and Ride Rev3 boards
  dt-bindings: arm: qcom: Document qcs9100-ride and qcs9100-ride Rev3
  arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers
  arm64: dts: qcom: x1e80100-crd: describe HID supplies
  arm64: dts: qcom: msm8998-lenovo-miix-630: add WiFi calibration variant
  arm64: dts: qcom: msm8998-clamshell: enable resin/VolDown
  arm64: dts: qcom: msm8998-lenovo-miix-630: enable VolumeUp button
  arm64: dts: qcom: msm8998-lenovo-miix-630: enable aDSP and SLPI
  arm64: dts: qcom: msm8998-lenovo-miix-630: enable touchscreen
  arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes
  ...

Link: https://lore.kernel.org/r/20241105164901.7787-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-11-12 22:45:37 +01:00
Arnd Bergmann
8cd0d9b997 Renesas DTS updates for v6.13 (take two)
- Add a CPU Operating Performance Points table for the RZ/V2H SoC,
   - Add Battery Backup Function (VBATTB) and RTC support for the RZ/G3S
     SoC and the RZ/G3S SMARC SoM,
   - Add DMAC support for MMC on the RZ/A1H SoC and the Genmai
     development board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.13-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.13 (take two)

  - Add a CPU Operating Performance Points table for the RZ/V2H SoC,
  - Add Battery Backup Function (VBATTB) and RTC support for the RZ/G3S
    SoC and the RZ/G3S SMARC SoM,
  - Add DMAC support for MMC on the RZ/A1H SoC and the Genmai
    development board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.13-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: rzg3s-smarc-som: Enable RTC
  arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB
  arm64: dts: renesas: r9a08g045: Add RTC node
  arm64: dts: renesas: r9a08g045: Add VBATTB node
  arm64: dts: renesas: white-hawk-cpu-common: Add pin control for DSI-eDP IRQ
  ARM: dts: renesas: r7s72100: Add DMA support to MMCIF
  ARM: dts: renesas: r7s72100: Add DMAC node
  arm64: dts: renesas: hihope: Drop #sound-dai-cells
  dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
  dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
  arm64: dts: renesas: r9a09g057: Add OPP table

Link: https://lore.kernel.org/r/cover.1730726155.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-11-12 22:42:35 +01:00
Bjorn Andersson
559dd75eb9 Merge branch '20240822-qcs8300-gcc-v2-1-b310dfa70ad8@quicinc.com' into clk-for-6.13
Merge QCS8300 global clock controller binding through topic branch to
make it available to both clock and DeviceTree branches.
2024-11-05 16:58:56 -08:00
Imran Shaik
43b53bca61 dt-bindings: clock: qcom: Add GCC clocks for QCS8300
Add support for qcom global clock controller bindings for QCS8300 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20240822-qcs8300-gcc-v2-1-b310dfa70ad8@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05 16:58:19 -08:00
Bjorn Andersson
153986098c Merge branch '20241028060506.246606-3-quic_srichara@quicinc.com' into clk-for-6.13
Merge IPQ5424 global clock controller binding through topic branch to
make the constants available for both clock and DeviceTree branches.
2024-11-05 16:33:17 -08:00
Sricharan Ramabadhran
03e525c66d dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding
Add binding for the Qualcomm IPQ5424 Global Clock Controller

Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241028060506.246606-3-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05 16:32:44 -08:00
Bjorn Andersson
f93cea43e5 Merge branch '20241027-sar2130p-clocks-v5-0-ecad2a1432ba@linaro.org' into clk-for-6.13
Merge SAR2130P clock bindings through topic branch, to allow them being
used in both clock and DeviceTree branches.
2024-11-05 16:21:30 -08:00
Konrad Dybcio
111481020a dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles
Expand qcom,sm8450-gpucc bindings to include SAR2130P.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-5-ecad2a1432ba@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05 16:21:11 -08:00
Dmitry Baryshkov
3ee315537e dt-bindings: clock: qcom: document SAR2130P Global Clock Controller
Add bindings for the Global Clock Controller (GCC) present on the
Qualcomm SAR2130P platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-2-ecad2a1432ba@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05 16:19:40 -08:00
Claudiu Beznea
cdfd5daf90 dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
the tamper detector and a small general usage memory of 128B.

The VBATTB controller controls the clock for the RTC on the Renesas
RZ/G3S. The HW block diagram for the clock logic is as follows:

           +----------+ XC   `\
RTXIN  --->|          |----->| \       +----+  VBATTCLK
           | 32K clock|      |  |----->|gate|----------->
           | osc      | XBYP |  |      +----+
RTXOUT --->|          |----->| /
           +----------+      ,/

One could connect as input to this HW block either a crystal or
an external clock device. This is board specific.

After discussions w/ Stephen Boyd the clock tree associated with this
hardware block was exported in Linux as:

input-xtal
  xbyp
  xc
     mux
        vbattclk

where:
- input-xtal is the input clock (connected to RTXIN, RTXOUT pins)
- xc, xbyp are mux inputs
- mux is the internal mux
- vbattclk is the gate clock that feeds in the end the RTC

to allow selecting the input of the MUX though assigned-clock DT
properties, using the already existing clock drivers and avoid adding
other DT properties.

This allows select the input of the mux based on the type of the
connected input clock:
- if the 32768 crystal is connected as input for the VBATTB,
  the input of the mux should be xc
- if an external clock device is connected as input for the VBATTB the
  input of the mux should be xbyp

Add bindings for the VBATTB controller.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20241101095720.2247815-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-03 11:43:21 +01:00
Ryan Chen
76c6217c31 dt-bindings: mfd: aspeed: Support for AST2700
Add reset, clk dt bindings headers, and update compatible
support for AST2700 clk, silicon-id in yaml.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20241023090153.1395220-2-ryan_chen@aspeedtech.com
Signed-off-by: Lee Jones <lee@kernel.org>
2024-11-01 16:11:50 +00:00
Krzysztof Kozlowski
807b1a361d Merge branch 'for-v6.13/clk-dt-bindings' into next/clk 2024-10-26 14:00:02 +02:00
Ivaylo Ivanov
a81dca0572 dt-bindings: clock: samsung: Add Exynos8895 SoC
Provide dt-schema documentation for Samsung Exynos8895 SoC clock
controller CMU blocks:
- CMU_FSYS0/1
- CMU_PERIC0/1
- CMU_PERIS
- CMU_TOP

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Link: https://lore.kernel.org/r/20241023090136.537395-2-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-26 13:58:33 +02:00
Claudiu Beznea
49991cca67 dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
The RTC and VBATTB don't share the MSTOP control bit (but only the bus
clock and the reset signal). As the MSTOP control is modeled though power
domains add power domain ID for the RTC device available on the
Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241019084738.3370489-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25 10:54:21 +02:00
Pengfei Li
f029d87009 dt-bindings: clock: Add i.MX91 clock support
i.MX91 has similar Clock Control Module(CCM) design as i.MX93, only add
few new clock compared to i.MX93.
Add a new compatible string and some new clocks for i.MX91.

Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241023184651.381265-4-pengfei.li_1@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-10-23 22:48:30 +03:00
Pengfei Li
c0813ce2e5 dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition
IMX93_CLK_END should be dropped as it is not part of the ABI.

Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241023184651.381265-3-pengfei.li_1@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-10-23 22:48:29 +03:00
Manikanta Mylavarapu
da040d5603 dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros
Q6 firmware takes care of bringup clocks, so remove them.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240820055618.267554-5-quic_gokulsri@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-23 11:31:10 -05:00
Manikanta Mylavarapu
b3aba04883 dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros
Q6 firmware takes care of bringup clocks, so remove them.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Link: https://lore.kernel.org/r/20240820055618.267554-4-quic_gokulsri@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-23 11:31:10 -05:00
Bjorn Andersson
bbee3fe179 Merge branch '20241011-sa8775p-mm-v4-resend-patches-v5-0-4a9f17dc683a@quicinc.com' into clk-for-6.13
Merge SA8775P multimedia clock bindings through topic branch to allow
the constants to be made available to DeviceTree source as well.
2024-10-22 17:24:04 -05:00
Taniya Das
33b5cd95d8 dt-bindings: clock: qcom: Add SA8775P display clock controllers
Add device tree bindings for the display clock controllers
on Qualcomm SA8775P platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-5-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 17:23:55 -05:00
Taniya Das
9b1873d235 dt-bindings: clock: qcom: Add SA8775P camera clock controller
Add device tree bindings for the camera clock controller
on Qualcomm SA8775P platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-3-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 17:23:55 -05:00
Taniya Das
7867cb6575 dt-bindings: clock: qcom: Add SA8775P video clock controller
Add device tree bindings for the video clock controller on Qualcomm
SA8775P platform.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-1-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 17:23:16 -05:00
Yassine Oudjana
ea1cca0268 dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings
Add clock definitions for the main clock and reset controllers of MT6735
(apmixedsys, topckgen, infracfg and pericfg).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-17 12:24:35 -07:00
Théo Lebrun
bae7aff581 dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes
Add #defines for Mobileye EyeQ6L and EyeQ6H SoC clocks.

Constant prefixes are:
 - EQ6LC_PLL_: EyeQ6L clock PLLs
 - EQ6HC_SOUTH_PLL_: EyeQ6H south OLB PLLs
 - EQ6HC_SOUTH_DIV_: EyeQ6H south OLB divider clocks
 - EQ6HC_ACC_PLL_: EyeQ6H accelerator OLB PLLs

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241007-mbly-clk-v5-2-e9d8994269cb@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-17 11:16:01 -07:00
Krzysztof Kozlowski
56051619c3 Merge branch 'for-v6.13/clk-dt-bindings' into next/clk 2024-10-10 10:46:52 +02:00
Sunyeal Hong
440e3dcd7c dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
Add peric1, misc and hsi0/1 clock definitions.

- CMU_PERIC1 for USI, IC2 and I3C
- CMU_MISC for MISC, GIC and OTP
- HSI0 for PCIE
- HSI1 for USB and MMC

Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241009042110.2379903-2-sunyeal.hong@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-10 10:46:34 +02:00
Danila Tikhonov
61b17d072d dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings
Add new entry to the SM8450 dt-bindings and add SM8475-specific clocks
to SM8450 GCC header file.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05 22:08:40 -05:00
Inbaraj E
2d3e0135ce dt-bindings: clock: samsung: remove define with number of clocks for FSD
Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.
Remove it entirely from the bindings, once Linux drivers stopped using
them.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240917094355.37887-3-inbaraj.e@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-09-30 12:48:37 +02:00
Linus Torvalds
075dbe9f6e soc: convert ep93xx to devicetree
This concludes a long journey towards replacing the old
 board files with devictree description on the Cirrus Logic
 EP93xx platform.
 
 Nikita Shubin has been working on this for a long time,
 for details see the last post on
 https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/
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Merge tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC update from Arnd Bergmann:
 "Convert ep93xx to devicetree

  This concludes a long journey towards replacing the old board files
  with devictree description on the Cirrus Logic EP93xx platform.

  Nikita Shubin has been working on this for a long time, for details
  see the last post on

    https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/"

* tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits)
  dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples
  MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer
  soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config
  net: cirrus: use u8 for addr to calm down sparse
  dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0
  dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe()
  pinctrl: ep93xx: Fix raster pins typo
  spi: ep93xx: update kerneldoc comments for ep93xx_spi
  clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate()
  clk: ep93xx: add module license
  dmaengine: cirrus: remove platform code
  ASoC: cirrus: edb93xx: Delete driver
  ARM: ep93xx: soc: drop defines
  ARM: ep93xx: delete all boardfiles
  ata: pata_ep93xx: remove legacy pinctrl use
  pwm: ep93xx: drop legacy pinctrl
  ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms
  ARM: dts: ep93xx: Add EDB9302 DT
  ARM: dts: ep93xx: add ts7250 board
  ARM: dts: add Cirrus EP93XX SoC .dtsi
  ...
2024-09-26 12:00:25 -07:00
Stephen Boyd
1b189f71e1 Merge branches 'clk-devm', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-devm:
  clk: provide devm_clk_get_optional_enabled_with_rate()
  clk: fixed-rate: add devm_clk_hw_register_fixed_rate_parent_data()

* clk-samsung:
  clk: samsung: add top clock support for ExynosAuto v920 SoC
  clk: samsung: clk-pll: Add support for pll_531x
  dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings
  clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS
  clk: samsung: clk-pll: Add support for pll_1418x
  clk: samsung: exynosautov9: add dpum clock support
  dt-bindings: clock: exynosautov9: add dpum clock
  clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP
  clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix
  dt-bindings: clock: exynos7885: Add indices for USB clocks
  dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices
  dt-bindings: clock: exynos7885: Fix duplicated binding
  clk: samsung: exynos850: Add TMU clock
  dt-bindings: clock: exynos850: Add TMU clock

* clk-rockchip:
  dt-bindings: clock, reset: fix top-comment indentation rk3576 headers
  clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitions
  clk: rockchip: fix error for unknown clocks
  clk: rockchip: rk3588: drop unused code
  clk: rockchip: Add clock controller for the RK3576
  clk: rockchip: Add new pll type pll_rk3588_ddr
  dt-bindings: clock, reset: Add support for rk3576
  dt-bindings: clock: rockchip,rk3588-cru: drop unneeded assigned-clocks
  clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_p
  dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS
  clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage
  clk: rockchip: rk3368: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3328: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3308: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3288: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3228: Drop CLK_NR_CLKS usage
  clk: rockchip: rk3036: Drop CLK_NR_CLKS usage
  clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usage
  clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228

* clk-qcom: (47 commits)
  clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC's
  clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLL
  clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocks
  clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocks
  clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_src
  dt-bindings: usb: qcom,dwc3: Update ipq5332 clock details
  dt-bindings: interconnect: Add Qualcomm IPQ5332 support
  clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocks
  dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions
  clk: qcom: Fix SM_CAMCC_8150 dependencies
  clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_src
  clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq table
  clk: qcom: gcc-sc8180x: Add GPLL9 support
  dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x
  clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180x
  clk: qcom: clk-rpmh: Fix overflow in BCM vote
  dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camcc
  dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videocc
  dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschema
  dt-bindings: clock: Add x1e80100 LPASSCC reset controller
  ...
2024-09-21 14:11:05 -07:00
Stephen Boyd
6629108252 Merge branches 'clk-amlogic', 'clk-microchip' and 'clk-imx' into clk-next
* clk-amlogic:
  clk: meson: introduce symbol namespace for amlogic clocks
  clk: meson: axg-audio: add sm1 earcrx clocks
  clk: meson: axg-audio: setup regmap max_register based on the SoC
  dt-bindings: clock: axg-audio: add earcrx clock ids
  clk: meson: s4: pll: Constify struct regmap_config
  clk: meson: s4: peripherals: Constify struct regmap_config
  clk: meson: c3: pll: Constify struct regmap_config
  clk: meson: c3: peripherals: Constify struct regmap_config
  clk: meson: a1: pll: Constify struct regmap_config
  clk: meson: a1: peripherals: Constify struct regmap_config

* clk-microchip:
  clk: at91: sama7g5: Allocate only the needed amount of memory for PLLs
  clk: at91: sam9x7: add sam9x7 pmc driver
  dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT
  clk: at91: sama7g5: move mux table macros to header file
  clk: at91: sam9x7: add support for HW PLL freq dividers
  clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs
  dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller
  dt-bindings: clocks: atmel,at91sam9x5-sckc: add sam9x7

* clk-imx: (27 commits)
  clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL
  clk: imx95: enable the clock of NETCMIX block control
  dt-bindings: clock: add RMII clock selection
  dt-bindings: clock: add i.MX95 NETCMIX block control
  clk: imx: imx8: Use clk_hw pointer for self registered clock in clk_parent_data
  clk: imx: composite-7ulp: Use NULL instead of 0
  clk: imx: add missing MODULE_DESCRIPTION() macros
  clk: imx: clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate
  clk: imx: fracn-gppll: update rate table
  clk: imx: imx8qxp: Parent should be initialized earlier than the clock
  clk: imx: imx8qxp: Register dc0_bypass0_clk before disp clk
  clk: imx: imx8qxp: Add clock muxes for MIPI and PHY ref clocks
  clk: imx: imx8qxp: Add LVDS bypass clocks
  clk: imx: imx8mm: Change the 'nand_usdhc_bus' clock to non-critical one
  clk: imx: imx8mn: add sai7_ipg_clk clock settings
  clk: imx: add CLK_SET_RATE_PARENT for lcdif_pixel_src for i.MX7D
  clk: imx: Remove CLK_SET_PARENT_GATE for DRAM mux for i.MX7D
  clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
  clk: imx: fracn-gppll: fix fractional part of PLL getting lost
  clk: imx: composite-7ulp: Check the PCC present bit
  ...
2024-09-21 14:10:59 -07:00
Nikita Shubin
eeb3dd5b32 dt-bindings: soc: Add Cirrus EP93xx
Add device tree bindings for the Cirrus Logic EP93xx SoC.

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-12 14:33:10 +00:00
Heiko Stuebner
eb3b3f5205 dt-bindings: clock, reset: fix top-comment indentation rk3576 headers
Block comments should align the * on each line, as checkpatch rightfully
pointed out, so fix that style issue on the newly added rk3576 headers.

Fixes: 49c04453db ("dt-bindings: clock, reset: Add support for rk3576")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20240909223149.85364-1-heiko@sntech.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-09 16:13:05 -07:00
Detlev Casanova
49c04453db dt-bindings: clock, reset: Add support for rk3576
Add clock and reset ID defines for rk3576.

Compared to the downstream bindings written by Elaine, this uses
continous gapless IDs starting at 0. Thus all numbers are
different between downstream and upstream, but names are kept
exactly the same.

Also add documentation for the rk3576 CRU core.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/0102019199a76766-f3a2b53f-d063-458b-b0d1-dfbc2ea1893c-000000@eu-west-1.amazonses.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-29 10:28:16 +02:00
Wei Fang
b4f62001cc dt-bindings: clock: add RMII clock selection
Add RMII clock selection for ENETC0 and ENETC1.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240829011849.364987-3-wei.fang@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-08-29 10:02:16 +03:00
Johan Jonker
fb234516c5 dt-bindings: clock: rockchip: remove CLK_NR_CLKS and CLKPMU_NR_CLKS
CLK_NR_CLKS and CLKPMU_NR_CLKS should not be part of the binding.
Remove since the kernel code no longer uses it.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/a3292ed0-3489-4887-8567-40ea4983c592@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-28 21:25:50 +02:00
Sunyeal Hong
997daa8de6 dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings
Add dt-schema for ExynosAuto v920 SoC clock controller.
Add device tree clock binding definitions for below CMU blocks.

- CMU_TOP
- CMU_PERIC0/1
- CMU_MISC
- CMU_HSI0/1

Signed-off-by: Sunyeal Hong <sunyeal.hong@samsung.com>
Link: https://lore.kernel.org/r/20240821232652.1077701-2-sunyeal.hong@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-23 09:16:41 +02:00
Bjorn Andersson
2cb4fcc4d9 Merge branch '20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr' into clk-for-6.12
Merge updates to MSM8998 GCC binding include file through topic branch,
to make available the newly added constants to both clock and DeviceTree
branch.
2024-08-15 16:10:24 -05:00
AngeloGioacchino Del Regno
015dff12df dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions
Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks,
required to enable audio functionality on MSM8998.

Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC
as a final step to enable the required clock tree for the lpass iommu
and for the audio dsp itself.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 16:10:16 -05:00
Satya Priya Kakitapalli
648b4bde0a dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180x
Add the missing GPLL9 which is required for the gcc sdcc2 clock.

Fixes: 0fadcdfdcf ("dt-bindings: clock: Add SC8180x GCC binding")
Cc: stable@vger.kernel.org
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-2-8b3eaa5fb856@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15 14:14:54 -05:00
Bjorn Andersson
b4c71885e5 Merge branch '20240611133752.2192401-1-quic_ajipan@quicinc.com' into clk-for-6.12
Merge the SM4450 display, camera and GPU bindings through a topic
branch, to make it possible to merge them into the DeviceTree source
branch as well.
2024-08-14 21:05:26 -05:00
Ajit Pandey
47bad234ee dt-bindings: clock: qcom: add GPUCC clocks on SM4450
Add device tree bindings for the graphics clock controller on
Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-7-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14 21:05:15 -05:00