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96f3b97873
The 'syspll' PLL is a general-purpose PLL designed specifically for the CPU clock. It is capable of producing output frequencies within the range of 768MHz to 1536MHz. The 'syspll_in' source clock is an optional parent connection from the peripherals clock controller. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
27 lines
696 B
C
27 lines
696 B
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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* Author: Jian Hu <jian.hu@amlogic.com>
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*
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* Copyright (c) 2023, SberDevices. All Rights Reserved.
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* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
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*/
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#ifndef __A1_PLL_CLKC_H
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#define __A1_PLL_CLKC_H
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#define CLKID_FIXED_PLL_DCO 0
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#define CLKID_FIXED_PLL 1
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#define CLKID_FCLK_DIV2_DIV 2
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#define CLKID_FCLK_DIV3_DIV 3
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#define CLKID_FCLK_DIV5_DIV 4
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#define CLKID_FCLK_DIV7_DIV 5
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#define CLKID_FCLK_DIV2 6
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#define CLKID_FCLK_DIV3 7
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#define CLKID_FCLK_DIV5 8
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#define CLKID_FCLK_DIV7 9
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#define CLKID_HIFI_PLL 10
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#define CLKID_SYS_PLL 11
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#endif /* __A1_PLL_CLKC_H */
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