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f029d87009
i.MX91 has similar Clock Control Module(CCM) design as i.MX93, only add few new clock compared to i.MX93. Add a new compatible string and some new clocks for i.MX91. Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241023184651.381265-4-pengfei.li_1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
214 lines
6.7 KiB
C
214 lines
6.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
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/*
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* Copyright 2022 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H
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#define __DT_BINDINGS_CLOCK_IMX93_CLK_H
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#define IMX93_CLK_DUMMY 0
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#define IMX93_CLK_24M 1
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#define IMX93_CLK_EXT1 2
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#define IMX93_CLK_SYS_PLL_PFD0 3
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#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4
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#define IMX93_CLK_SYS_PLL_PFD1 5
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#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6
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#define IMX93_CLK_SYS_PLL_PFD2 7
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#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8
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#define IMX93_CLK_AUDIO_PLL 9
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#define IMX93_CLK_VIDEO_PLL 10
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#define IMX93_CLK_A55_PERIPH 11
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#define IMX93_CLK_A55_MTR_BUS 12
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#define IMX93_CLK_A55 13
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#define IMX93_CLK_M33 14
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#define IMX93_CLK_BUS_WAKEUP 15
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#define IMX93_CLK_BUS_AON 16
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#define IMX93_CLK_WAKEUP_AXI 17
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#define IMX93_CLK_SWO_TRACE 18
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#define IMX93_CLK_M33_SYSTICK 19
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#define IMX93_CLK_FLEXIO1 20
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#define IMX93_CLK_FLEXIO2 21
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#define IMX93_CLK_LPTMR1 24
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#define IMX93_CLK_LPTMR2 25
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#define IMX93_CLK_TPM2 27
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#define IMX93_CLK_TPM4 29
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#define IMX93_CLK_TPM5 30
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#define IMX93_CLK_TPM6 31
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#define IMX93_CLK_FLEXSPI1 32
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#define IMX93_CLK_CAN1 33
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#define IMX93_CLK_CAN2 34
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#define IMX93_CLK_LPUART1 35
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#define IMX93_CLK_LPUART2 36
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#define IMX93_CLK_LPUART3 37
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#define IMX93_CLK_LPUART4 38
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#define IMX93_CLK_LPUART5 39
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#define IMX93_CLK_LPUART6 40
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#define IMX93_CLK_LPUART7 41
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#define IMX93_CLK_LPUART8 42
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#define IMX93_CLK_LPI2C1 43
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#define IMX93_CLK_LPI2C2 44
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#define IMX93_CLK_LPI2C3 45
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#define IMX93_CLK_LPI2C4 46
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#define IMX93_CLK_LPI2C5 47
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#define IMX93_CLK_LPI2C6 48
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#define IMX93_CLK_LPI2C7 49
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#define IMX93_CLK_LPI2C8 50
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#define IMX93_CLK_LPSPI1 51
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#define IMX93_CLK_LPSPI2 52
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#define IMX93_CLK_LPSPI3 53
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#define IMX93_CLK_LPSPI4 54
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#define IMX93_CLK_LPSPI5 55
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#define IMX93_CLK_LPSPI6 56
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#define IMX93_CLK_LPSPI7 57
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#define IMX93_CLK_LPSPI8 58
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#define IMX93_CLK_I3C1 59
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#define IMX93_CLK_I3C2 60
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#define IMX93_CLK_USDHC1 61
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#define IMX93_CLK_USDHC2 62
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#define IMX93_CLK_USDHC3 63
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#define IMX93_CLK_SAI1 64
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#define IMX93_CLK_SAI2 65
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#define IMX93_CLK_SAI3 66
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#define IMX93_CLK_CCM_CKO1 67
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#define IMX93_CLK_CCM_CKO2 68
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#define IMX93_CLK_CCM_CKO3 69
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#define IMX93_CLK_CCM_CKO4 70
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#define IMX93_CLK_HSIO 71
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#define IMX93_CLK_HSIO_USB_TEST_60M 72
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#define IMX93_CLK_HSIO_ACSCAN_80M 73
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#define IMX93_CLK_HSIO_ACSCAN_480M 74
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#define IMX93_CLK_ML_APB 75
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#define IMX93_CLK_ML 76
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#define IMX93_CLK_MEDIA_AXI 77
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#define IMX93_CLK_MEDIA_APB 78
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#define IMX93_CLK_MEDIA_LDB 79
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#define IMX93_CLK_MEDIA_DISP_PIX 80
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#define IMX93_CLK_CAM_PIX 81
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#define IMX93_CLK_MIPI_TEST_BYTE 82
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#define IMX93_CLK_MIPI_PHY_CFG 83
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#define IMX93_CLK_ADC 84
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#define IMX93_CLK_PDM 85
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#define IMX93_CLK_TSTMR1 86
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#define IMX93_CLK_TSTMR2 87
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#define IMX93_CLK_MQS1 88
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#define IMX93_CLK_MQS2 89
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#define IMX93_CLK_AUDIO_XCVR 90
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#define IMX93_CLK_SPDIF 91
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#define IMX93_CLK_ENET 92
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#define IMX93_CLK_ENET_TIMER1 93
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#define IMX93_CLK_ENET_TIMER2 94
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#define IMX93_CLK_ENET_REF 95
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#define IMX93_CLK_ENET_REF_PHY 96
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#define IMX93_CLK_I3C1_SLOW 97
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#define IMX93_CLK_I3C2_SLOW 98
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#define IMX93_CLK_USB_PHY_BURUNIN 99
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#define IMX93_CLK_PAL_CAME_SCAN 100
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#define IMX93_CLK_A55_GATE 101
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#define IMX93_CLK_CM33_GATE 102
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#define IMX93_CLK_ADC1_GATE 103
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#define IMX93_CLK_WDOG1_GATE 104
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#define IMX93_CLK_WDOG2_GATE 105
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#define IMX93_CLK_WDOG3_GATE 106
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#define IMX93_CLK_WDOG4_GATE 107
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#define IMX93_CLK_WDOG5_GATE 108
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#define IMX93_CLK_SEMA1_GATE 109
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#define IMX93_CLK_SEMA2_GATE 110
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#define IMX93_CLK_MU_A_GATE 111
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#define IMX93_CLK_MU_B_GATE 112
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#define IMX93_CLK_EDMA1_GATE 113
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#define IMX93_CLK_EDMA2_GATE 114
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#define IMX93_CLK_FLEXSPI1_GATE 115
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#define IMX93_CLK_GPIO1_GATE 116
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#define IMX93_CLK_GPIO2_GATE 117
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#define IMX93_CLK_GPIO3_GATE 118
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#define IMX93_CLK_GPIO4_GATE 119
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#define IMX93_CLK_FLEXIO1_GATE 120
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#define IMX93_CLK_FLEXIO2_GATE 121
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#define IMX93_CLK_LPIT1_GATE 122
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#define IMX93_CLK_LPIT2_GATE 123
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#define IMX93_CLK_LPTMR1_GATE 124
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#define IMX93_CLK_LPTMR2_GATE 125
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#define IMX93_CLK_TPM1_GATE 126
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#define IMX93_CLK_TPM2_GATE 127
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#define IMX93_CLK_TPM3_GATE 128
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#define IMX93_CLK_TPM4_GATE 129
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#define IMX93_CLK_TPM5_GATE 130
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#define IMX93_CLK_TPM6_GATE 131
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#define IMX93_CLK_CAN1_GATE 132
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#define IMX93_CLK_CAN2_GATE 133
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#define IMX93_CLK_LPUART1_GATE 134
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#define IMX93_CLK_LPUART2_GATE 135
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#define IMX93_CLK_LPUART3_GATE 136
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#define IMX93_CLK_LPUART4_GATE 137
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#define IMX93_CLK_LPUART5_GATE 138
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#define IMX93_CLK_LPUART6_GATE 139
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#define IMX93_CLK_LPUART7_GATE 140
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#define IMX93_CLK_LPUART8_GATE 141
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#define IMX93_CLK_LPI2C1_GATE 142
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#define IMX93_CLK_LPI2C2_GATE 143
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#define IMX93_CLK_LPI2C3_GATE 144
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#define IMX93_CLK_LPI2C4_GATE 145
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#define IMX93_CLK_LPI2C5_GATE 146
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#define IMX93_CLK_LPI2C6_GATE 147
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#define IMX93_CLK_LPI2C7_GATE 148
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#define IMX93_CLK_LPI2C8_GATE 149
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#define IMX93_CLK_LPSPI1_GATE 150
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#define IMX93_CLK_LPSPI2_GATE 151
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#define IMX93_CLK_LPSPI3_GATE 152
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#define IMX93_CLK_LPSPI4_GATE 153
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#define IMX93_CLK_LPSPI5_GATE 154
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#define IMX93_CLK_LPSPI6_GATE 155
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#define IMX93_CLK_LPSPI7_GATE 156
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#define IMX93_CLK_LPSPI8_GATE 157
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#define IMX93_CLK_I3C1_GATE 158
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#define IMX93_CLK_I3C2_GATE 159
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#define IMX93_CLK_USDHC1_GATE 160
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#define IMX93_CLK_USDHC2_GATE 161
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#define IMX93_CLK_USDHC3_GATE 162
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#define IMX93_CLK_SAI1_GATE 163
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#define IMX93_CLK_SAI2_GATE 164
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#define IMX93_CLK_SAI3_GATE 165
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#define IMX93_CLK_MIPI_CSI_GATE 166
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#define IMX93_CLK_MIPI_DSI_GATE 167
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#define IMX93_CLK_LVDS_GATE 168
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#define IMX93_CLK_LCDIF_GATE 169
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#define IMX93_CLK_PXP_GATE 170
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#define IMX93_CLK_ISI_GATE 171
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#define IMX93_CLK_NIC_MEDIA_GATE 172
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#define IMX93_CLK_USB_CONTROLLER_GATE 173
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#define IMX93_CLK_USB_TEST_60M_GATE 174
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#define IMX93_CLK_HSIO_TROUT_24M_GATE 175
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#define IMX93_CLK_PDM_GATE 176
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#define IMX93_CLK_MQS1_GATE 177
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#define IMX93_CLK_MQS2_GATE 178
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#define IMX93_CLK_AUD_XCVR_GATE 179
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#define IMX93_CLK_SPDIF_GATE 180
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#define IMX93_CLK_HSIO_32K_GATE 181
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#define IMX93_CLK_ENET1_GATE 182
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#define IMX93_CLK_ENET_QOS_GATE 183
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#define IMX93_CLK_SYS_CNT_GATE 184
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#define IMX93_CLK_TSTMR1_GATE 185
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#define IMX93_CLK_TSTMR2_GATE 186
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#define IMX93_CLK_TMC_GATE 187
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#define IMX93_CLK_PMRO_GATE 188
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#define IMX93_CLK_32K 189
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#define IMX93_CLK_SAI1_IPG 190
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#define IMX93_CLK_SAI2_IPG 191
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#define IMX93_CLK_SAI3_IPG 192
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#define IMX93_CLK_MU1_A_GATE 193
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#define IMX93_CLK_MU1_B_GATE 194
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#define IMX93_CLK_MU2_A_GATE 195
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#define IMX93_CLK_MU2_B_GATE 196
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#define IMX93_CLK_NIC_AXI 197
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#define IMX93_CLK_ARM_PLL 198
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#define IMX93_CLK_A55_SEL 199
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#define IMX93_CLK_A55_CORE 200
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#define IMX93_CLK_PDM_IPG 201
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#define IMX91_CLK_ENET1_QOS_TSN 202
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#define IMX91_CLK_ENET_TIMER 203
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#define IMX91_CLK_ENET2_REGULAR 204
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#define IMX91_CLK_ENET2_REGULAR_GATE 205
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#define IMX91_CLK_ENET1_QOS_TSN_GATE 206
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#endif
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