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ea1cca0268
Add clock definitions for the main clock and reset controllers of MT6735 (apmixedsys, topckgen, infracfg and pericfg). Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
80 lines
2.2 KiB
C
80 lines
2.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
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#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H
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#define CLK_TOP_AD_SYS_26M_CK 0
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#define CLK_TOP_CLKPH_MCK_O 1
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#define CLK_TOP_DMPLL 2
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#define CLK_TOP_DPI_CK 3
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#define CLK_TOP_WHPLL_AUDIO_CK 4
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#define CLK_TOP_SYSPLL_D2 5
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#define CLK_TOP_SYSPLL_D3 6
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#define CLK_TOP_SYSPLL_D5 7
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#define CLK_TOP_SYSPLL1_D2 8
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#define CLK_TOP_SYSPLL1_D4 9
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#define CLK_TOP_SYSPLL1_D8 10
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#define CLK_TOP_SYSPLL1_D16 11
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#define CLK_TOP_SYSPLL2_D2 12
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#define CLK_TOP_SYSPLL2_D4 13
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#define CLK_TOP_SYSPLL3_D2 14
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#define CLK_TOP_SYSPLL3_D4 15
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#define CLK_TOP_SYSPLL4_D2 16
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#define CLK_TOP_SYSPLL4_D4 17
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#define CLK_TOP_UNIVPLL_D2 18
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#define CLK_TOP_UNIVPLL_D3 19
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#define CLK_TOP_UNIVPLL_D5 20
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#define CLK_TOP_UNIVPLL_D26 21
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#define CLK_TOP_UNIVPLL1_D2 22
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#define CLK_TOP_UNIVPLL1_D4 23
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#define CLK_TOP_UNIVPLL1_D8 24
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#define CLK_TOP_UNIVPLL2_D2 25
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#define CLK_TOP_UNIVPLL2_D4 26
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#define CLK_TOP_UNIVPLL2_D8 27
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#define CLK_TOP_UNIVPLL3_D2 28
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#define CLK_TOP_UNIVPLL3_D4 29
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#define CLK_TOP_MSDCPLL_D2 30
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#define CLK_TOP_MSDCPLL_D4 31
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#define CLK_TOP_MSDCPLL_D8 32
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#define CLK_TOP_MSDCPLL_D16 33
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#define CLK_TOP_VENCPLL_D3 34
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#define CLK_TOP_TVDPLL_D2 35
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#define CLK_TOP_TVDPLL_D4 36
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#define CLK_TOP_DMPLL_D2 37
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#define CLK_TOP_DMPLL_D4 38
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#define CLK_TOP_DMPLL_D8 39
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#define CLK_TOP_AD_SYS_26M_D2 40
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#define CLK_TOP_AXI_SEL 41
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#define CLK_TOP_MEM_SEL 42
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#define CLK_TOP_DDRPHY_SEL 43
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#define CLK_TOP_MM_SEL 44
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#define CLK_TOP_PWM_SEL 45
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#define CLK_TOP_VDEC_SEL 46
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#define CLK_TOP_MFG_SEL 47
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#define CLK_TOP_CAMTG_SEL 48
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#define CLK_TOP_UART_SEL 49
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#define CLK_TOP_SPI_SEL 50
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#define CLK_TOP_USB20_SEL 51
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#define CLK_TOP_MSDC50_0_SEL 52
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#define CLK_TOP_MSDC30_0_SEL 53
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#define CLK_TOP_MSDC30_1_SEL 54
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#define CLK_TOP_MSDC30_2_SEL 55
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#define CLK_TOP_MSDC30_3_SEL 56
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#define CLK_TOP_AUDIO_SEL 57
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#define CLK_TOP_AUDINTBUS_SEL 58
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#define CLK_TOP_PMICSPI_SEL 59
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#define CLK_TOP_SCP_SEL 60
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#define CLK_TOP_ATB_SEL 61
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#define CLK_TOP_DPI0_SEL 62
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#define CLK_TOP_SCAM_SEL 63
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#define CLK_TOP_MFG13M_SEL 64
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#define CLK_TOP_AUD1_SEL 65
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#define CLK_TOP_AUD2_SEL 66
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#define CLK_TOP_IRDA_SEL 67
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#define CLK_TOP_IRTX_SEL 68
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#define CLK_TOP_DISPPWM_SEL 69
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#endif
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