mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2024-12-29 17:23:36 +00:00
6914b82f37
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220222011534.3502-1-konrad.dybcio@somainline.org
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
|
/*
|
|
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
|
|
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
|
|
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6350_H
|
|
|
|
/* DISP_CC clocks */
|
|
#define DISP_CC_PLL0 0
|
|
#define DISP_CC_MDSS_AHB_CLK 1
|
|
#define DISP_CC_MDSS_AHB_CLK_SRC 2
|
|
#define DISP_CC_MDSS_BYTE0_CLK 3
|
|
#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
|
|
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
|
|
#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
|
|
#define DISP_CC_MDSS_DP_AUX_CLK 7
|
|
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8
|
|
#define DISP_CC_MDSS_DP_CRYPTO_CLK 9
|
|
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10
|
|
#define DISP_CC_MDSS_DP_LINK_CLK 11
|
|
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12
|
|
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13
|
|
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14
|
|
#define DISP_CC_MDSS_DP_PIXEL_CLK 15
|
|
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16
|
|
#define DISP_CC_MDSS_ESC0_CLK 17
|
|
#define DISP_CC_MDSS_ESC0_CLK_SRC 18
|
|
#define DISP_CC_MDSS_MDP_CLK 19
|
|
#define DISP_CC_MDSS_MDP_CLK_SRC 20
|
|
#define DISP_CC_MDSS_MDP_LUT_CLK 21
|
|
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 22
|
|
#define DISP_CC_MDSS_PCLK0_CLK 23
|
|
#define DISP_CC_MDSS_PCLK0_CLK_SRC 24
|
|
#define DISP_CC_MDSS_ROT_CLK 25
|
|
#define DISP_CC_MDSS_ROT_CLK_SRC 26
|
|
#define DISP_CC_MDSS_RSCC_AHB_CLK 27
|
|
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 28
|
|
#define DISP_CC_MDSS_VSYNC_CLK 29
|
|
#define DISP_CC_MDSS_VSYNC_CLK_SRC 30
|
|
#define DISP_CC_SLEEP_CLK 31
|
|
#define DISP_CC_XO_CLK 32
|
|
|
|
/* GDSCs */
|
|
#define MDSS_GDSC 0
|
|
|
|
#endif
|