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e67a004482
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Dmitry Baryshkov <dmityr.baryshkov@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220706154337.2026269-2-robert.foss@linaro.org
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H
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/* GPU_CC clocks */
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#define GPU_CC_AHB_CLK 0
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#define GPU_CC_CB_CLK 1
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#define GPU_CC_CRC_AHB_CLK 2
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#define GPU_CC_CX_APB_CLK 3
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#define GPU_CC_CX_GMU_CLK 4
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#define GPU_CC_CX_QDSS_AT_CLK 5
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#define GPU_CC_CX_QDSS_TRIG_CLK 6
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#define GPU_CC_CX_QDSS_TSCTR_CLK 7
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#define GPU_CC_CX_SNOC_DVM_CLK 8
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#define GPU_CC_CXO_AON_CLK 9
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#define GPU_CC_CXO_CLK 10
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#define GPU_CC_FREQ_MEASURE_CLK 11
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#define GPU_CC_GMU_CLK_SRC 12
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#define GPU_CC_GX_GMU_CLK 13
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#define GPU_CC_GX_QDSS_TSCTR_CLK 14
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#define GPU_CC_GX_VSENSE_CLK 15
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16
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#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17
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#define GPU_CC_HUB_AON_CLK 18
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#define GPU_CC_HUB_CLK_SRC 19
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#define GPU_CC_HUB_CX_INT_CLK 20
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#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21
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#define GPU_CC_MND1X_0_GFX3D_CLK 22
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#define GPU_CC_MND1X_1_GFX3D_CLK 23
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#define GPU_CC_PLL0 24
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#define GPU_CC_PLL1 25
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#define GPU_CC_SLEEP_CLK 26
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/* GPU_CC resets */
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#define GPUCC_GPU_CC_ACD_BCR 0
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#define GPUCC_GPU_CC_CB_BCR 1
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#define GPUCC_GPU_CC_CX_BCR 2
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#define GPUCC_GPU_CC_FAST_HUB_BCR 3
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#define GPUCC_GPU_CC_GFX3D_AON_BCR 4
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#define GPUCC_GPU_CC_GMU_BCR 5
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#define GPUCC_GPU_CC_GX_BCR 6
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#define GPUCC_GPU_CC_XO_BCR 7
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/* GPU_CC GDSCRs */
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#define GPU_CX_GDSC 0
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#define GPU_GX_GDSC 1
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#endif
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