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33b5cd95d8
Add device tree bindings for the display clock controllers on Qualcomm SA8775P platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-5-4a9f17dc683a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
88 lines
3.5 KiB
C
88 lines
3.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
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#define _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
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/* DISP_CC_0/1 clocks */
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#define MDSS_DISP_CC_MDSS_AHB1_CLK 0
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#define MDSS_DISP_CC_MDSS_AHB_CLK 1
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#define MDSS_DISP_CC_MDSS_AHB_CLK_SRC 2
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#define MDSS_DISP_CC_MDSS_BYTE0_CLK 3
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#define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define MDSS_DISP_CC_MDSS_BYTE1_CLK 7
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#define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC 8
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#define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9
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#define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK 10
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#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK 11
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#define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 12
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#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK 13
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#define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC 14
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#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK 15
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#define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16
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#define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17
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#define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18
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#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19
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#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20
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#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21
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#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22
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#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK 23
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#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC 24
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#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK 25
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#define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC 26
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#define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 27
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#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK 28
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#define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 29
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#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK 30
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#define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC 31
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#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK 32
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#define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 33
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#define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 34
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#define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 35
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#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK 36
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#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 37
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#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK 38
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#define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 39
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#define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 40
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#define MDSS_DISP_CC_MDSS_ESC0_CLK 41
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#define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC 42
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#define MDSS_DISP_CC_MDSS_ESC1_CLK 43
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#define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC 44
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#define MDSS_DISP_CC_MDSS_MDP1_CLK 45
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#define MDSS_DISP_CC_MDSS_MDP_CLK 46
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#define MDSS_DISP_CC_MDSS_MDP_CLK_SRC 47
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#define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK 48
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#define MDSS_DISP_CC_MDSS_MDP_LUT_CLK 49
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#define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK 50
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#define MDSS_DISP_CC_MDSS_PCLK0_CLK 51
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#define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC 52
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#define MDSS_DISP_CC_MDSS_PCLK1_CLK 53
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#define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC 54
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#define MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK 55
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#define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK 56
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#define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK 57
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#define MDSS_DISP_CC_MDSS_VSYNC1_CLK 58
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#define MDSS_DISP_CC_MDSS_VSYNC_CLK 59
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#define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC 60
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#define MDSS_DISP_CC_PLL0 61
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#define MDSS_DISP_CC_PLL1 62
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#define MDSS_DISP_CC_SLEEP_CLK 63
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#define MDSS_DISP_CC_SLEEP_CLK_SRC 64
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#define MDSS_DISP_CC_SM_OBS_CLK 65
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#define MDSS_DISP_CC_XO_CLK 66
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#define MDSS_DISP_CC_XO_CLK_SRC 67
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/* DISP_CC_0/1 power domains */
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#define MDSS_DISP_CC_MDSS_CORE_GDSC 0
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#define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC 1
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/* DISP_CC_0/1 resets */
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#define MDSS_DISP_CC_MDSS_CORE_BCR 0
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#define MDSS_DISP_CC_MDSS_RSCC_BCR 1
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#endif
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