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54ce17dd40
Add all RZ/G2N Clock Pulse Generator Core Clock Outputs, as listed in
Table 8.2d ("List of Clocks [RZ/G2N]") of the RZ/G2N Hardware User's
Manual.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1567666360-28035-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
58 lines
1.6 KiB
C
58 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a774b1 CPG Core Clocks */
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#define R8A774B1_CLK_Z 0
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#define R8A774B1_CLK_ZG 1
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#define R8A774B1_CLK_ZTR 2
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#define R8A774B1_CLK_ZTRD2 3
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#define R8A774B1_CLK_ZT 4
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#define R8A774B1_CLK_ZX 5
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#define R8A774B1_CLK_S0D1 6
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#define R8A774B1_CLK_S0D2 7
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#define R8A774B1_CLK_S0D3 8
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#define R8A774B1_CLK_S0D4 9
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#define R8A774B1_CLK_S0D6 10
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#define R8A774B1_CLK_S0D8 11
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#define R8A774B1_CLK_S0D12 12
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#define R8A774B1_CLK_S1D2 13
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#define R8A774B1_CLK_S1D4 14
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#define R8A774B1_CLK_S2D1 15
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#define R8A774B1_CLK_S2D2 16
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#define R8A774B1_CLK_S2D4 17
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#define R8A774B1_CLK_S3D1 18
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#define R8A774B1_CLK_S3D2 19
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#define R8A774B1_CLK_S3D4 20
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#define R8A774B1_CLK_LB 21
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#define R8A774B1_CLK_CL 22
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#define R8A774B1_CLK_ZB3 23
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#define R8A774B1_CLK_ZB3D2 24
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#define R8A774B1_CLK_CR 25
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#define R8A774B1_CLK_DDR 26
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#define R8A774B1_CLK_SD0H 27
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#define R8A774B1_CLK_SD0 28
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#define R8A774B1_CLK_SD1H 29
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#define R8A774B1_CLK_SD1 30
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#define R8A774B1_CLK_SD2H 31
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#define R8A774B1_CLK_SD2 32
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#define R8A774B1_CLK_SD3H 33
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#define R8A774B1_CLK_SD3 34
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#define R8A774B1_CLK_RPC 35
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#define R8A774B1_CLK_RPCD2 36
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#define R8A774B1_CLK_MSO 37
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#define R8A774B1_CLK_HDMI 38
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#define R8A774B1_CLK_CSI0 39
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#define R8A774B1_CLK_CP 40
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#define R8A774B1_CLK_CPEX 41
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#define R8A774B1_CLK_R 42
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#define R8A774B1_CLK_OSC 43
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#define R8A774B1_CLK_CANFD 44
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#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */
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